4x1 MUX [PDF]

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EXPERIMENT NO. 4    EXPERIMENT NAME: Write a VHDL code to implement 4 x 1 MUX using LOGIC GATES, IF ELSE AND WITH SELECT and simulate the design.



RESOURCES USED: Computer System, Xilinx ISE 9.2i



PRINCIPLE: A Multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called a data selector. Multiplexers can also be used to implement Boolean functions of multiple variables.



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VHDL CODE: 1) LOGIC GATE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity full_adder is port ( a : in std_logic; b : in std_logic; cin : in std_logic; -s : out std_logic; cout : out std_logic ); end​ half_adder; architecture Behavioral of full_adder is Begin s cout