![Compal La-6755p, La-6757p (Pawgc, Pawgd) 2010-11-10 Rev 1.0 Schematic [PDF]](https://pdfs.asia/img/200x200/compal-la-6755p-la-6757p-pawgc-pawgd-2010-11-10-rev-10-schematic.jpg)
4 0 1 MB
A
B
C
D
E
1
1
m .ru
Compal Confidential 2
2
ru
PAWGC/D Schematics Document
er Fo
AMD APU Ontario-FT1 + FCH Hudson-M1 + GPU Roberson XT
2010-11-10
3
REV:1.0
C
yb
3
4
4
CIT RD Only
2010/06/30
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/06/30
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Cover Page Size B Date:
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010
Sheet E
1
of
48
A
B
C
D
E
For PAWGC 1. POWER BOARD 2. Card Reader BOARD
Compal confidential File Name : PAWGC/D
For PAWGD 1. POWER BOARD 2. Card reader BOARD 3. 4*LED+SW(3pin) +SW(4pin) BOARD 4. ODD BOARD
1
LVDS Conn.
Memory BUS(DDRIII) 200pin DDRII-SO-DIMM X2
page 10
AMD Brazos APU HDMI Conn. page 11
page 5,6,7
VRAM 64*16 DDR3*4
x4 PCI-E GPP GEN2 x4 UMI Gen. 1 2.5GT/s per lane
page 18 ~ 24
page 8,9
BANK 0, 1, 2, 3
1.5V DDRIII 1333
FT1 BGA 413-Ball 19mm x 19mm
page 12
AMD Robson
Single Channel
m .ru
CRT Conn.
1
2Channel Speaker
Hudson M1
er Fo
WLAN &WiMax
page 13,14,15,16,17
page 30
GIGA LAN AR8151/8152
6*SATA serial
LPC BUS
page 25,26
SPI ROM
EC
page 15
ENE KB930
PCI-E(WLAN)
Audio Jacks Stereo HeadPhone Output Microphone Input
CMOS Camera page 10 BlueTooth CONN page 34 USB PORT 2.0 x3(Left)
USB PORT 2.0 x1(Right)
page 34
page 35
WLAN/WiMAX
3
Card Reader Realtek RTS5139 SD/MMC/MS/MS Pro/XD
Int.KBD page 32
C
WLAN/WiMAX page 30
USB(WiMAX)
yb
page 31
PCI Express Mini card Slot 1
page 27
14*USB2.0
4 * x1 PCI-E 2.0
2
page 27
CX20671
ru
AZALIA
BGA 605-Ball 23mm x 23mm
3
Internal MIC
Audio Codec
2
page 27
Touch Pad
ESATA HDD AND USB CONN (Left) page 34
SPI ROM
page 32
page 33
SATA3.0 HDD CONN page 29
Thermal Sensor SATA ODD CONN page 29
EMC1403 page 28
4
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2010/06/30
Issued Date
2012/06/30
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
4
D
Title
Block Diagrams Size B Date:
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010
Sheet E
2
of
48
C
Description
S1
VIN
Adapter power supply (19V)
N/A
B+
AC or battery power rail for power circuit.
N/A
S5
FCH Hudson-M1 USB Port List
N/A
N/A
USB1.1
N/A
N/A
S3
+APU_CORE
Core voltage for CPU (0.7-1.2V)
ON
OFF
OFF
+APU_CORE_NB
1.0V switched power rail
ON
OFF
OFF
+1.5V
1.5V power rail for CPU VDDIO and DDRIII
ON
ON
OFF
+0.75VS
0.75VS switched power rail for DDR terminator
ON
OFF
OFF
+1.0VS
1.0V switched power rail for NB VDDC & VGA
ON
OFF
OFF
+1.1VS
1.1VS switched power rail
ON
OFF
OFF
+1.8VS
1.8V switched power rail
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3V_LAN
3.3V power rail for LAN
ON ON(WOL)
+3VS
3.3V switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
OFF
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
+1.1VALW
1.1V always on power rail
ON
ON
ON*
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
EC SM Bus1 address
EC SM Bus2 address
Device
Address
HEX
Smart Battery
0001-011xb
15H
SM Bus Controller 0 Device
Address
HEX
EMC1412-2 (dGPU)
Device
1111-100xb
F8H
EMC1403-2(DDR,WLAN)
1001-101xb
9AH
SB-TSI
1001-100xb
98H
(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)
Address
HEX
APU SIC/SID (FCH_SMB3) H_THERMTRIP# (FCH_ALERT#)
SM Bus Controller 1 Device
(FCH_SMB0)
Address
HEX
DDR DIMM1 (FCH_SMB0)
1001-000xb
90
DDR DIMM2 (FCH_SMB0)
1001-001xb
92
PCIE0
Port0
NC
Port1
NC
PCIE1 PCIE2
SATA0 GPU PCIE x4
HDD
SATA1
ODD
SATA2
eSATA
SATA3
NC
1
USB2.0
PCIE3
Port0
Left USB1
PCIE0
LAN
SATA4
NC
Port1
USB Camera
PCIE1
WLAN
SATA5
NC
Port2
Left(Combo)
PCIE2
NC
Port3
Left USB2
PCIE3
NC
Port4
Right USB
Port5
BT
Port6
CardReader
Port7
Mini-PCIE
Port8
NC
Port9
NC
Port10
NC
BOM Structure
Port11
NC
UMA@ PX@
Port12
NC
Port13
NC
2
: UMA only : DIS muxluss - PX3@ : PX3.0 only - BACO@ : Baco only
GIGA@ : AR8151 8152@ : AR8152 CMOS@ : USB camera HDMI@ : HDMI function nonHDMI@ : w/o HDMI function ESATA@: eSATA function BT@ : BT function ME@ : ME components X76@, H1G@, H512@, S1G@, S512@ : VRAM 45@ : 45 Level HWM@ : hardware monitor function nonHWM@: w/o hardware monitor function
3
C
WLAN (FCH_SMB0)
FCH Hudson-M1 SATA Port List
yb
3
Brazos PCIE Port List
er Fo
2
E
m .ru
1
Power Plane
FCH
Voltage Rails
D
APU
B
ru
A
4
4
2010/06/30
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/06/30
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Notes List Size B Date:
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010
Sheet E
3
of
48
5
4
3
2
Power-Up/Down Sequence
PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.
BACO option :
2. VDDR3 should ramp-up before or simultaneously with VDDC. D
PE_GPIO0 : High ->Normal operation (dGPU is not reset on BACO mode) PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. 4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up.
Note: Do not drive any IOs before VDDR3 is ramped up.
PCIE_VDDC(1.0V) C
VDDR1(1.5VGS)
Voltage
PX 3.0
BACO Mode Max current
PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD, DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI, DPLL_PVDD, MPV18, and SPV18
1.8V
OFF
ON
1679mA
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and SPV10
1.0V
OFF
ON
575mA
PCIE_VDDC
1.0V
OFF
ON
2A
VDDR3 , and A2VDD
3.3V
OFF
ON
190mA
BIF_VDDC (current consumption = [email protected], in BACO mode)
Same as VDDC
OFF
ON Same as PCIE_VDDC
70mA
VDDR1
1.5V
OFF
OFF
2.8A
VDDC/VDDCI
1.12V
OFF
OFF
12.9A
ru
VDDC/VDDCI(1.12V)
dGPU Power Pins
m .ru
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).)
VDDR3(3.3VGS)
VDD_CT(1.8V)
iGPU
er Fo
PERSTb REFCLK B
Straps Reset
PE_GPIO0
PX_mode
+3.3VALW
+1.0V
+1.8V
MOS
Regulator
SI4800
C
+3.3VGS
B
1 +1.0VGS
+1.5V
3
Regulator
4
2 +B
+1.8VGS
+1.5VGS
SI4800
5
+VGA_CORE
PWRGOOD
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/30
Deciphered Date
2012/07/14
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
BACO Switch
A
Issued Date
5
C
BIF_VDDC
T4+16clock
A
PE_EN
dGPU
D
PE_GPIO1
yb
Straps Valid Global ASIC Reset
1
Without BACO option :
3
2
dGPU Block Diagram Size B Date:
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010
Sheet 1
4
of
48
5
4
3
2
1
2 2
0.1U_0402_16V7K 0.1U_0402_16V7K
HDMI_TX0P_C HDMI_TX0N_C
D10 C10
(11) HDMI_CLKP (11) HDMI_CLKN
C514 1 C515 1
2 2
0.1U_0402_16V7K 0.1U_0402_16V7K
HDMI_CLKP_C HDMI_CLKN_C
A10 B10
+3VS
2 10K_0402_5%
HDMI_DATA
R812 1
2 10K_0402_5%
HDMI_CLK
R410 1
2 1K_0402_5%
APU_PROCHOT#
R411 1
2 1K_0402_5%
APU_ALERT#_R
R412 1
2 1K_0402_5%
APU_SIC
R414 1
2 1K_0402_5%
APU_SID
B5 A5
(10) LVDS_A1 (10) LVDS_A1#
D6 C6
(10) LVDS_A0 (10) LVDS_A0#
A6 B6
(10) LVDS_ACLK (10) LVDS_ACLK#
D8 C8
R808 1
@
DISP_CLK DISP_CLK#
D2 D1
APU_SVC APU_SVD
J1 J2
SVC SVD
P3 P4
SIC SID
(44) (44)
2 0_0402_5% APU_PROCHOT# 2 0_0402_5%
T3 T4
(15) APU_ALERT#_FCH (31) APU_ALERT#_EC
Connection to EC, FCH input
APU_PROCHOT# U1 APU_THERMTRIP# U2 APU_ALERT#_R T2 R418 1 @ 2 0_0402_5% R873 1 2 0_0402_5% APU_TDI N2 APU_TDO need to pull-down N1 APU_TCK P1 APU_TMS P2 APU_TRST# M4 T93PAD APU_DBRDY M3 T94PAD Close to APU APU_DBREQ# M1
(44) APU_VDDNB_RUN_FB_H (44) APU_VDD0_RUN_FB_H
T77PAD
(44) APU_VDD0_RUN_FB_L
F4 G1 F3 F1
B4 W11 V5
+3VS
1 2
H_THERMTRIP# (14)
C
3
MMBT3904_NL_SOT23-3 1 R427 @
PROCHOT_L THERMTRIP_L ALERT_L TDI TDO TCK TMS TRST_L DBRDY DBREQ_L
LTDP0_HPD
VDDCR_NB_SENSE VDDCR_CPU_SENSE VDDIO_MEM_S_SENSE
DAC_RED DAC_REDB DAC_GREEN DAC_GREENB DAC_BLUE DAC_BLUEB
2 150_0402_1% APU_ENBKL (10) APU_ENVDD (10) APU_BLPWM (10)
HDMI_CLK HDMI_DATA
HDMI_DET (11)
A3 B3
EDID_CLK EDID_DATA
D3
R406 1
C12 D13 A12 B12 A13 B13
DAC_HSYNC DAC_VSYNC
DAC_SCL DAC_SDA
F2 D4
DAC_ZVSS
D12
TEST4 TEST5 TEST6 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST25_H TEST25_L TEST28_H TEST28_L TEST31 TEST33_H TEST33_L TEST34_H TEST34_L TEST35 TEST36 TEST37
R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5
RSVD_1 RSVD_2 RSVD_3
2 0_0402_5%
If FCH internal pull-up disabled, level-shifter could be deleted. Need BIOS to disable internal pull-up!!
EDID_CLK (10) EDID_DATA (10) 2 100K_0402_5%
R407 1
2 150_0402_1%
R409 1
2 150_0402_1%
R413 1
PAD T66 PAD T67
TEST15
1
C
1
6
EC_SMB_DA
Q80A 2N7002DW-T/R7_SOT363-6
5
1 R431
APU_TRST#
Vgs(th): min 1.0V Typ 1.6V Max 2.0V
4
3
Q80B 2N7002DW-T/R7_SOT363-6 1 R434 5
CRT_HSYNC (12) CRT_VSYNC (12) CRT_DDC_CLK (12) CRT_DDC_DATA (12)
AMD check list update 20101110
R415 1 @ 2 1K_0402_5% PAD T69 PAD T95 TEST18 R416 1 2 1K_0402_5% TEST19 R417 1 2 1K_0402_5% TEST25_H R419 1 2 510_0402_1% TEST_25_L TEST28_H PAD T71 TEST28_L PAD T72 TEST31 PAD T73 TEST33_H C516 1 R420 1 2 0.1U_0402_16V4Z TEST33_L C517 1 R421 1 2 0.1U_0402_16V4Z Delete Test point for layout limitation 20100818 TEST35 R422 1 2 1K_0402_5% TEST36 nonHDMI@ TEST37 R958 1 2 1K_0402_5% PAD T76 +1.8VS HDMI@
C
2 51_0402_1% 2 51_0402_1%
Pull-high to enable HDMI function 20100812 TEST38 DMAACTIVE_L
K3 T1
ALLOW_STOP# (13) R423 1
2 1K_0402_5%
+1.8VS
B
AMD Debug
need to pop for HDT debug 20101012 @ 0_0402_5% R846 1 2
1 R429 1 R430
@
FCH_SID
2 0_0402_5% EC_SMB_DA2 2 0_0402_5%
APU_TCK
R843 2
1 1K_0402_5%
APU_TMS
R844 2
1 1K_0402_5%
APU_TDI
R845 2
1 1K_0402_5%
APU_TDO APU_TRST#_R
APU_PWRGD +1.8VS
R847 2 @
1 10K_0402_5%
LDT_RST#
R848 2 @
1 10K_0402_5%
APU_DBRDY
R849 2 @
1 10K_0402_5%
APU_DBREQ#
R850 1 @
2 300_0402_5%
J108_PLLTST0
R851 1 @
2 0_0402_5%
TEST_19
J108_PLLTST1
R852 1 @
2 0_0402_5%
TEST_18
If Q80 or R429, R432 implemented, R747 & R748 need to be mounted
Please be noted about TEST_18 and TEST_19 FCH_SID
(14)
T0 FCH
EC_SMB_DA2 (19,29,31) TO
A
need to pop for HDT debug 20101012
EC
2 0_0402_5%
@ APU_SIC
DAC_BLU (12)
PAD T68
@ 1
DAC_GRN (12)
2 499_0402_1%
2
2
R428 10K_0402_5% @
A
DAC_RED (12)
2 150_0402_1%
R408 1
+1.8VS
2N7002DW-T/R7
+3VS
APU_SID
D
HDMI_CLK (11) HDMI_DATA (11)
C1
E1 E2
VSS_SENSE
2
Q79 1
E
APU_THERMTRIP#
RESET_L PWROK
yb
1
B
2
1K_0402_5%
DISP_CLKIN_H DISP_CLKIN_L
R842
R425
CLKIN_H CLKIN_L
LTDP0_AUXP LTDP0_AUXN
B2 C2
R398 1
ONTARIO-2M161000-1.6G_BGA413
R424 10K_0402_5%
2 B
LTDP0_TXP3 LTDP0_TXN3
APU_CLK APU_CLK#
(13) LDT_RST# (13) APU_PWRGD
R807 1
LTDP0_TXP2 LTDP0_TXN2
(13) (13)
C
(31) EC_PROCHOT#
LTDP0_TXP1 LTDP0_TXN1
(13) (13)
TDP1_AUXP TDP1_AUXN TDP1_HPD
LTDP0_TXP0 LTDP0_TXN0
V2 V1
APU_SIC APU_SID
(13) FCH_PROCHOT#
TDP1_TXP3 TDP1_TXN3
H3 G2 H2 H1
ru
R811 1
(10) LVDS_A2 (10) LVDS_A2#
TDP1_TXP2 TDP1_TXN2
DP_ZVSS DP_BLON DP_DIGON DP_VARY_BL
m .ru
C512 1 C513 1
DP MISC
(11) HDMI_TX0P (11) HDMI_TX0N
TDP1_TXP1 TDP1_TXN1
VGA DAC
B9 A9
TEST
2 2
DISPLAYPORT 0
(11) HDMI_TX1P (11) HDMI_TX1N
TDP1_TXP0 TDP1_TXN0
CLK
APU_DBREQ# APU_SVC APU_SVD LDT_RST# APU_PWRGD TEST_25_L TEST36
HDMI_TX1P_C HDMI_TX1N_C
SER
300_0402_5% 1K_0402_5% 1K_0402_5% 300_0402_5% 300_0402_5% 510_0402_1% 1K_0402_5%
0.1U_0402_16V7K 0.1U_0402_16V7K
CTRL
1 2 2 1 1 2 2
C510 1 C511 1
A8 B8
JTAG
2 1 1 2 2 1 1
HDMI_TX2P_C HDMI_TX2N_C
1K_0402_5%
R404 R399 R400 R405 R401 R402 R403
0.1U_0402_16V7K 0.1U_0402_16V7K
C508 1 C509 1
er Fo
D
2 2
(11) HDMI_TX2P (11) HDMI_TX2N
DISPLAYPORT 1
U22B +1.8VS
EC_SMB_CK
@ 1 R432 1 R433
FCH_SIC 2 0_0402_5% EC_SMB_CK2 2 0_0402_5%
FCH_SIC
(14)
T0 FCH
EC_SMB_CK2 (19,29,31) TO EC
Compal Secret Data
Security Classification 2010/06/30
Issued Date
2012/06/30
Deciphered Date
4
3
Compal Electronics, Inc. FT1 CTRL/DP/CRT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2 0_0402_5%
Title
2
Size Document Number Custom Date:
Rev 1.0
LA6755P/7P
Tuesday, November 30, 2010
Sheet 1
5
of
48
A
B
C
D
E
U22E
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3
(8) (8) (9) (9)
DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB#
F15 E15
DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1
W19 V15 U19 W15
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB#
T17 W16 U17 V16
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
(8,9) DDR_A_RAS# (8,9) DDR_A_CAS# (8,9) DDR_A_WE#
L23 N17
U18 V19 V17
M_DQS_H0 M_DQS_L0 M_DQS_H1 M_DQS_L1 M_DQS_H2 M_DQS_L2 M_DQS_H3 M_DQS_L3 M_DQS_H4 M_DQS_L4 M_DQS_H5 M_DQS_L5 M_DQS_H6 M_DQS_L6 M_DQS_H7 M_DQS_L7
M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31 M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39 M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47
M_CLK_H0 M_CLK_L0 M_CLK_H1 M_CLK_L1 M_CLK_H2 M_CLK_L2 M_CLK_H3 M_CLK_L3
M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55
M_RESET_L M_EVENT_L M_CKE0 M_CKE1
M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63
M0_ODT0 M0_ODT1 M1_ODT0 M1_ODT1 M0_CS_L0 M0_CS_L1 M1_CS_L0 M1_CS_L1
M_VREF
M_RAS_L M_CAS_L M_WE_L M_ZVDDIO_MEM_S ONTARIO-2M161000-1.6G_BGA413
C23 D23 F23 F22 C22 D22 F20 F21
DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23
H21 H23 K22 K21 G23 H20 K20 K23
DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31
N23 P21 T20 T23 M20 P20 R23 T22
DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39
V20 V21 Y23 Y22 T21 U23 W23 Y21
DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47
Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18
DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55
AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15
DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
M23
+MEM_VREF
M22
R437
2
(8,9)
DDR_A_DM[0..7]
(8,9) (8,9)
4
U22A
(18) PCIE_CRX_GTX_P0 (18) PCIE_CRX_GTX_N0 (18) PCIE_CRX_GTX_P1 (18) PCIE_CRX_GTX_N1 (18) PCIE_CRX_GTX_P2 (18) PCIE_CRX_GTX_N2 (18) PCIE_CRX_GTX_P3 (18) PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0
AA6 Y6
PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1
AB4 AC4
PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2
AA1 AA2
PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3
Y4 Y3
1 2 R435 2K_0402_1%
+1.0VS
P_ZVDD_10
Y14
P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3
P_GPP_TXP0 P_GPP_TXN0 P_GPP_TXP1 P_GPP_TXN1 P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3
P_ZVDD_10
P_ZVSS
AB6 PCIE_CTX_C_GRX_P0 C518 1 AC6 PCIE_CTX_C_GRX_N0 C519 1
2 0.1U_0402_16V7K 2 0.1U_0402_16V7K
PCIE_CTX_GRX_P0 (18) PCIE_CTX_GRX_N0 (18)
AB3 PCIE_CTX_C_GRX_P1 C520 1 AC3 PCIE_CTX_C_GRX_N1 C521 1
2 0.1U_0402_16V7K 2 0.1U_0402_16V7K
PCIE_CTX_GRX_P1 (18) PCIE_CTX_GRX_N1 (18)
Y1 Y2
PCIE_CTX_C_GRX_P2 C522 1 PCIE_CTX_C_GRX_N2 C523 1
2 0.1U_0402_16V7K 2 0.1U_0402_16V7K
PCIE_CTX_GRX_P2 (18) PCIE_CTX_GRX_N2 (18)
V3 V4
PCIE_CTX_C_GRX_P3 C524 1 PCIE_CTX_C_GRX_N3 C525 1
2 0.1U_0402_16V7K 2 0.1U_0402_16V7K
PCIE_CTX_GRX_P3 (18) PCIE_CTX_GRX_N3 (18)
AA14 P_ZVSS
R436 1
2
3
1.27K_0402_1%
Less than 1"
Less than 1"
AA12 Y12
(13) UMI_RX0P (13) UMI_RX0N
P_UMI_RXP0 P_UMI_RXN0
(13) UMI_RX1P (13) UMI_RX1N
AA10 Y10
(13) UMI_RX2P (13) UMI_RX2N
AB10 AC10
(13) UMI_RX3P (13) UMI_RX3N
AC7 AB7
1
P_UMI_RXP1 P_UMI_RXN1 P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3
P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3
AB12 AC12
UMI_TX0P_C UMI_TX0N_C
C526 1 C527 1
2 2
0.1U_0402_16V7K 0.1U_0402_16V7K
AC11 AB11
UMI_TX1P_C UMI_TX1N_C
C528 1 C529 1
2 2
0.1U_0402_16V7K 0.1U_0402_16V7K
AA8 Y8
UMI_TX2P_C UMI_TX2N_C
C530 1 C531 1
2 2
0.1U_0402_16V7K 0.1U_0402_16V7K
AB8 AC8
UMI_TX3P_C UMI_TX3N_C
C532 1 C533 1
2 2
0.1U_0402_16V7K 0.1U_0402_16V7K
UMI_TX0P (13) UMI_TX0N (13) UMI_TX1P (13) UMI_TX1N (13) UMI_TX2P (13) UMI_TX2N (13) UMI_TX3P (13) UMI_TX3N (13)
ONTARIO-2M161000-1.6G_BGA413
2
+1.5V
39.2_0402_1%
2
C
+1.5V
DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15
DDR_A_DM[0..7]
DDR_A_D[0..63] DDR_A_MA[0..15]
PCIE I/F
M17 M16 M19 M18 N18 N19 L18 L17
DDR_CKE0 DDR_CKE1
(8,9) DDR_CKE0 (8,9) DDR_CKE1
2
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3 DDR_RST# DDR_EVENT#
(8,9) DDR_RST# (8,9) DDR_EVENT#
(8) (8) (9) (9)
A16 B16 B20 A20 E23 E22 J22 J23 R22 P22 W22 V22 AC20 AC21 AB16 AC16
M_DM0 M_DM1 M_DM2 M_DM3 M_DM4 M_DM5 M_DM6 M_DM7
M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23
C18 A19 B21 D20 A18 B18 A21 C20
DDR_A_D[0..63] DDR_A_MA[0..15]
UMI I/F
(8) (8) (8) (8) (9) (9) (9) (9)
DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7
M_BANK0 M_BANK1 M_BANK2
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7
m .ru
3
D15 B19 D21 H22 P23 V23 AB20 AA16
M_DATA8 M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15
B14 A15 A17 D18 A14 C14 C16 D16
ru
(8,9) DDR_A_DQS0 (8,9) DDR_A_DQS#0 (8,9) DDR_A_DQS1 (8,9) DDR_A_DQS#1 (8,9) DDR_A_DQS2 (8,9) DDR_A_DQS#2 (8,9) DDR_A_DQS3 (8,9) DDR_A_DQS#3 (8,9) DDR_A_DQS4 (8,9) DDR_A_DQS#4 (8,9) DDR_A_DQS5 (8,9) DDR_A_DQS#5 (8,9) DDR_A_DQS6 (8,9) DDR_A_DQS#6 (8,9) DDR_A_DQS7 (8,9) DDR_A_DQS#7
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7
DDR SYSTEM MEMORY
R18 T18 F16
(8,9) DDR_A_BS0 (8,9) DDR_A_BS1 (8,9) DDR_A_BS2
M_ADD0 M_ADD1 M_ADD2 M_ADD3 M_ADD4 M_ADD5 M_ADD6 M_ADD7 M_ADD8 M_ADD9 M_ADD10 M_ADD11 M_ADD12 M_ADD13 M_ADD14 M_ADD15
er Fo
4
R17 H19 J17 H18 H17 G17 H15 G18 F19 E19 T19 F17 E18 W17 E16 G15
yb
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
+1.5V
DDR_EVENT#
1
R438 1K_0402_1%
2 1K_0402_5%
+MEM_VREF
2
R444 1
1
R439 1K_0402_1%
C535
1 1
1
1
C534
2
1000P_0402_50V7K
2
0.1U_0402_16V4Z
Place within 1000 mils to APU 20100526
Compal Secret Data
Security Classification Issued Date
2010/06/30
2012/0630
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. FT1 DDRIII/UMI/PCIE
Size Document Number Custom Date:
Rev 1.0
LA6755P/7P
Tuesday, November 30, 2010
Sheet E
6
of
48
5
4
3
2
1
+APU_CORE +1.8VS
2
10U_0603_6.3V6M
1U_0402_6.3V6K C549
1U_0402_6.3V6K C548
1U_0402_6.3V6K C547
1U_0402_6.3V6K C538
0.1U_0402_16V7K C546
180P_0402_50V8J C537
C545
m .ru
1U_0402_6.3V6K C558
C556
180P_0402_50V8J C557
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
1
1
FBMA-L11-201209-221LMA30T_0805
L32
2
1
2
1
10U_0603_6.3V6M
2
1
10U_0603_6.3V6M C574
2
1
1U_0402_6.3V6K C573
2
1
1U_0402_6.3V6K C572
2
1
0.1U_0402_16V7K C571
1
0.1U_0402_16V7K C570
2
1
2
0.5A
VDD_33
1
1U_0402_6.3V6K C567
2
0.1U_0402_16V7K C566
1
FBMA-L11-201209-221LMA30T_0805
Change from SM010014520 to SD002000080 20100816
2
Near CPU Socket
C
+3VS
ONTARIO-2M161000-1.6G_BGA413
A4
1
C598
2
1
2
1
1
2
B
+1.5V
2
2
Issued Date
3
2010/06/30
Deciphered Date
2012/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
2
2
2
1
C615
1
C614
1
C613
C612
1
180P_0402_50V8J
2
A
2
Compal Electronics, Inc. P07-FT1 PWR/VSS
Size C Date:
2
1
180P_0402_50V8J
2
C611
C610
1
180P_0402_50V8J
2
C609
1
180P_0402_50V8J
2
Compal Secret Data
Security Classification
Near CPU Socket
1
0.1U_0402_16V7K
@
1
0.1U_0402_16V7K
C625
+
C608
+1.8VS
0.1U_0402_16V7K
POWER
(S ELE CAP 330U 6.3V M 6.3X5.9 LESR15M VU)*1=(SF000002000) 20100813 4
D
By case (Along split)
C624
C623
@
1
22U_0805_6.3V6M
C622
330U_2.5V_M
10U_0603_6.3V6M
C619
330U_D2_2.5VY_R9M
C618
(330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00) 5
+ 2
Near CPU Socket
+1.0VS
unpop for PVT 20101004 1
2
U13 W13 V12 T12
VDD_10_1 VDD_10_2 VDD_10_3 VDD_10_4
180P_0402_50V8J C565
C564 +VDD_10
C603
C601
C600
1
1
2
0.1U_0402_16V7K
2
0.1U_0402_16V7K
1
1
2
2
N13 N20 N22 P10 P14 R4 R7 R20 T6 T9 T11 T13 U4 U5 U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11
1U_0402_6.3V6K
2
A
1
2
0.1U_0402_16V7K
+1.5V
Near CPU Socket
+
1
+1.0VS has been raised to +1.05VS for AMD design guide 45339_R1.02 update 20101004
VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSSBG_DAC
er Fo 1
C602
2
POWER
+APU_CORE_NB
1
1
10U_0603_6.3V6M
2
1
FBMA-L11-201209-221LMA30T_0805
2
1
5.5A
180P_0402_50V8J
1
C597
C590
2
330U_6.3V_M
@
1
2
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49
10U_0603_6.3V6M
1
yb C599
2
C616
+
10U_0603_6.3V6M
C607
1
330U_D2E_2.5VM_R9M
2
330U_D2E_2.5VM_R9M
C606
330U_D2E_2.5VM_R9M
C605
2
+
0.1U_0402_16V7K
2
POWER 1
1
2
U22D A7 B7 B11 B17 B22 C4 D5 D7 D9 D11 D14 B15 D17 D19 E7 E9 E12 E20 F8 F11 F13 G4 G5 G7 G9 G12 G20 G22 H6 H11 H13 J4 J5 J7 J20 K10 K14 L4 L6 L8 L11 L13 L20 L22 M7 N4 N6 N8 N11
Change from SM010014520 to SD002000080 20100816
C
C621
+ 2
220U_B2_2.5VM_R35
C620
10U_0603_6.3V6M
2
1
+APU_CORE
+
1
+1.0VS
1
+VDDL_10
C568
VDDIO_MEM_S_1 VDDIO_MEM_S_2 VDDIO_MEM_S_3 VDDIO_MEM_S_4 VDDIO_MEM_S_5 VDDIO_MEM_S_6 VDDIO_MEM_S_7 VDDIO_MEM_S_8 VDDIO_MEM_S_9 VDDIO_MEM_S_10 VDDIO_MEM_S_11
1U_0402_6.3V6K
C595
2
2
@
1
1
C596
+1.5V
B
POWER
U11
VDDPL_10
2
C589
2
1U_0402_6.3V6K
C588
1
10U_0603_6.3V6M
2
180P_0402_50V8J
1
180P_0402_50V8J
C587
C586
1U_0402_6.3V6K
2
1U_0402_6.3V6K
2
1U_0402_6.3V6K
C585 C594
1
1
0.1U_0402_16V7K
2
1U_0402_6.3V6K
C584 C593
C583 C592
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
1
2
0.1U_0402_16V7K
2
1
1
2
0.1U_0402_16V7K
1
1
2
0.1U_0402_16V7K
C582 C591
2
2
1
L31
ONTARIO-2M161000-1.6G_BGA413 1
2
1
ru
C579
2
G16 G19 E17 J16 L16 L19 N16 R16 R19 W18 U16
1
1U_0402_6.3V6K
2
1
2
2
2A
10U_0603_6.3V6M
C578
1
10U_0603_6.3V6M
C577
2
10U_0603_6.3V6M
C576
10U_0603_6.3V6M
2
1
1
0.2A
DP Phy/IO
10U_0603_6.3V6M
2
1
2
+VDD_18_DAC
POWER
DDR3
C575
1
2
1
L30 W9
VDD_18_DAC
PCIE/IO/DDR3 Phy
+1.5V
C
2
1
Change from SM010014520 to SD002000080 20100816 +1.8VS
180P_0402_50V8J C569
+APU_CORE_NB
VDDCR_NB_1 VDDCR_NB_2 VDDCR_NB_3 VDDCR_NB_4 VDDCR_NB_5 VDDCR_NB_6 VDDCR_NB_7 VDDCR_NB_8 VDDCR_NB_9 VDDCR_NB_10 VDDCR_NB_11 VDDCR_NB_12 VDDCR_NB_13 VDDCR_NB_14 VDDCR_NB_15 VDDCR_NB_16 VDDCR_NB_17 VDDCR_NB_18 VDDCR_NB_19 VDDCR_NB_20 VDDCR_NB_21 VDDCR_NB_22
1
0.15A
10A E8 E11 E13 F9 F12 G11 G13 H9 H12 K11 K13 L10 L12 L14 M11 M12 M13 N10 N12 N14 P11 P13
1
2
C580
10U_0603_6.3V6M
C540 C555
180P_0402_50V8J
+APU_CORE_NB
U8 W8 U6 U9 W6 T7 V7
VDD_18_1 VDD_18_2 VDD_18_3 VDD_18_4 VDD_18_5 VDD_18_6 VDD_18_7
0.1U_0402_16V7K C581
2
2
VDDCR_CPU_1 VDDCR_CPU_2 VDDCR_CPU_3 VDDCR_CPU_4 VDDCR_CPU_5 VDDCR_CPU_6 VDDCR_CPU_7 VDDCR_CPU_8 VDDCR_CPU_9 VDDCR_CPU_10 VDDCR_CPU_11 VDDCR_CPU_12 VDDCR_CPU_13 VDDCR_CPU_14 VDDCR_CPU_15
L29 2 1 FBMA-L11-201209-221LMA30T_0805
180P_0402_50V8J
C563
1
1
E5 E6 F5 F7 G6 G8 H5 H7 J6 J8 L7 M6 M8 N7 R8
0.1U_0402_16V7K
2
10U_0603_6.3V6M
C544 C554
1
2
180P_0402_50V8J
C543
10U_0603_6.3V6M
10U_0603_6.3V6M
C542
2
1U_0402_6.3V6K
C553 C562
1
0.1U_0402_16V7K
C541
10U_0603_6.3V6M 1U_0402_6.3V6K
C552 C561
2
0.1U_0402_16V7K
C536
10U_0603_6.3V6M 1U_0402_6.3V6K
C551 C560
0.1U_0402_16V7K
10U_0603_6.3V6M
C539 C550 C559
1
2
2
1
DIS PLL
2
2
1
2
1
GPU AND NB CORE
2
1
1
2
1
DAC
1
2
2
1
+VDD_18
GND
2
1
1
CPU CORE
1
1
2
1U_0402_6.3V6K
2
0.1U_0402_16V7K
1
2A TSense/PLL/DP/PCIE/IO
D
U22C
11A
+APU_CORE
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010 1
Sheet
7
of
48
5
4
+1.5V
DDR_A_MA3 DDR_A_MA1 (6) DDR_A_CLK0 (6) DDR_A_CLK#0 DDR_A_MA10 (6,9) DDR_A_BS0 (6,9) DDR_A_WE# (6,9) DDR_A_CAS# DDR_A_MA13 (6) DDR_CS1_DIMMA#
DDR_A_D32 DDR_A_D33 (6,9) DDR_A_DQS#4 (6,9) DDR_A_DQS4
B
DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 (6,9) DDR_A_DQS#6 (6,9) DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7
2
1 R446 10K_0402_5%
205 207
GND1 BOSS1
2
2 1
1
2
2
DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 (6,9) DDR_A_DQS3 (6,9) DDR_A_D30 DDR_A_D31
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
GND2 BOSS2
1
+1.5V
DDR_CKE1 (6,9) DDR_A_MA15 DDR_A_MA14
2
DDR_A_MA11 DDR_A_MA7
0.1U_0402_16V4Z 2
C628
1 0.1U_0402_16V4Z
DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_CLK1 (6) DDR_A_CLK#1 (6) DDR_A_BS1 (6,9) DDR_A_RAS# (6,9)
C629
1
2
0.1U_0402_16V4Z 2
C630
1 0.1U_0402_16V4Z
2
C631
1
0.1U_0402_16V4Z 2
C632
1 0.1U_0402_16V4Z
DDR_CS0_DIMMA# (6) DDR_A_ODT0 (6)
0.1U_0402_16V4Z 2
2
C633
C634 @ 1 0.1U_0402_16V4Z
1
1
0.1U_0402_16V4Z 2
2
C635 @
C636 @ 1 0.1U_0402_16V4Z
1
C
0.1U_0402_16V4Z 2
2
C637 @
C638 @ 1 0.1U_0402_16V4Z
CRB 0.1u X1
4.7u X1
CRB
1
C639 @
100U
DDR_A_ODT1 (6)
X2
+1.5V +0.75VS
+VREF_CA
DDR_A_D36 DDR_A_D37
DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45
1
2
1
2
@
2
1
2
1
1
2
1 + 2
B
20100729
DDR_A_DQS#5 (6,9) DDR_A_DQS5 (6,9)
Place near JDIMM1
DDR_A_D46 DDR_A_D47
SF000002Y00
DDR_A_D52 DDR_A_D53
DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61
DDR_A_DQS#7 (6,9) DDR_A_DQS7 (6,9)
DDR_A_D62 DDR_A_D63
+0.75VS
Compal Secret Data
Security Classification
DDR3 SO-DIMM A Reverse Type
4
A
DDR_EVENT# (6,9) FCH_SMDAT0 (9,14,30) FCH_SMCLK0 (9,14,30)
206 208
LCN_DAN06-K4406-0103
5
1
DDR_A_D22 DDR_A_D23
2
2
1
0.1U_0402_16V4Z
1
C647
C646
+3VS
2.2U_0603_6.3V4Z
A
DDR_A_D58 DDR_A_D59 R445 10K_0402_5% 1 2
Combine to one?
DDR_A_DM2
C643
DDR_A_MA8 DDR_A_MA5
CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT
DDR_A_D20 DDR_A_D21
220U_6.3V_M
DDR_A_MA12 DDR_A_MA9
CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT
R443 1K_0402_1%
4.7U_0603_6.3V6K
(6,9) DDR_A_BS2
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
D
R442 1K_0402_1%
DDR_RST# (6,9) DDR_A_D14 DDR_A_D15
C642
(6,9) DDR_CKE0 C
DDR_A_DM1
0.1U_0402_16V4Z
DDR_A_D26 DDR_A_D27
+VREF_CA
C641
DDR_A_DM3
R441 1K_0402_1%
+VREF_DQ
DDR_A_D12 DDR_A_D13
0.1U_0402_16V4Z
DDR_A_D24 DDR_A_D25
R440 1K_0402_1%
DDR_A_DM[0..7] (6,9)
C640
DDR_A_D18 DDR_A_D19
+1.5V
DDR_A_MA[0..15] (6,9)
DDR_A_DM[0..7]
DDR_A_D6 DDR_A_D7
m .ru
(6,9) DDR_A_DQS#2 (6,9) DDR_A_DQS2
DDR_A_MA[0..15]
DDR_A_DQS#0 (6,9) DDR_A_DQS0 (6,9)
+1.5V (6,9)
ru
DDR_A_D16 DDR_A_D17
DDR_A_D[0..63]
0.1U_0402_16V4Z
DDR_A_D10 DDR_A_D11
DDR_A_D[0..63]
C644
(6,9) DDR_A_DQS#1 (6,9) DDR_A_DQS1
DDR_A_D4 DDR_A_D5
1000P_0402_50V7K
DDR_A_D8 DDR_A_D9
VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
er Fo
DDR_A_D2 DDR_A_D3
VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS
ME@
C645
D
DDR_A_DM0
1
yb
2
DDR_A_D0 DDR_A_D1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
C
C627
1
1000P_0402_50V7K
2
0.1U_0402_16V4Z
C626
1
2
+1.5V JDIMM1
+VREF_DQ
3
Issued Date
2010/06/30
2012/06/30
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3
2
Title
Compal Electronics, Inc. DDR3 SODIMM-I Socket
Size Document Number Custom Date:
Rev 1.0
LA6755P/7P
Tuesday, November 30, 2010
Sheet 1
8
of
48
5
4
+1.5V
(6,8) DDR_A_DQS#1 (6,8) DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 (6,8) DDR_A_DQS#2 (6,8) DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27
DDR_A_DQS#0 (6,8) DDR_A_DQS0 (6,8)
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_RST# (6,8) DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 (6,8) DDR_A_DQS3 (6,8)
+1.5V
DDR_A_D30 DDR_A_D31 2
0.1U_0402_16V4Z 2
(6,8) DDR_A_WE# (6,8) DDR_A_CAS# DDR_A_MA13 (6) DDR_CS1_DIMMB#
DDR_A_D32 DDR_A_D33 (6,8) DDR_A_DQS#4 (6,8) DDR_A_DQS4
B
DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 (6,8) DDR_A_DQS#6 (6,8) DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 For DRAM strap pin reservation 20100817 R961 1 R448 1
@
DDR_A_D58 DDR_A_D59
2 10K_0402_5% 2 10K_0402_5%
+3VS
1 C667 2.2U_0603_6.3V4Z
1
2
C668 2 0.1U_0402_16V4Z
only one 4.7k
@
2
R449 10K_0402_5%
205
G1
DDR_A_MA2 DDR_A_MA0 DDR_B_CLK3 (6) DDR_B_CLK#3 (6)
C655
1 0.1U_0402_16V4Z
1
C656 @
1 1 0.1U_0402_16V4Z
C657 @
0.1U_0402_16V4Z 2 2 C658 @
1 0.1U_0402_16V4Z
1
C659 @
2 C660 @
1 0.1U_0402_16V4Z
CRB 0.1u X1
C661 0.1U_0402_16V4Z @
1
C
4,7uX1
+0.75VS
2
DDR_A_BS1 (6,8) DDR_A_RAS# (6,8)
@
DDR_CS0_DIMMB# (6) DDR_B_ODT0 (6)
1
2
1
1
2
DDR_B_ODT1 (6)
+VREF_CA
DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45
1
2
Place near JDIMM2
1
2
B
DDR_A_DQS#5 (6,8) DDR_A_DQS5 (6,8)
DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53
DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61
DDR_A_DQS#7 (6,8) DDR_A_DQS7 (6,8)
DDR_A_D62 DDR_A_D63 DDR_EVENT# (6,8) FCH_SMDAT0 (8,14,30) FCH_SMCLK0 (8,14,30)
A
+0.75VS
LCN_DAN06-K4806-0103
R962 10K_0402_5%
DDR3 SO-DIMM B Reverse Type
For DRAM strap pin reservation 20100817
5
1 1 0.1U_0402_16V4Z
C654
ru
G2
206
DDR_A_MA6 DDR_A_MA4
1
CRB
1
2
A
1
C653
0.1U_0402_16V4Z 2 2
C666
DDR_A_MA10 (6,8) DDR_A_BS0
DDR_A_MA11 DDR_A_MA7
1000P_0402_50V7K
(6) DDR_B_CLK2 (6) DDR_B_CLK#2
DDR_A_MA15 DDR_A_MA14
C665
DDR_A_MA3 DDR_A_MA1
1 0.1U_0402_16V4Z
DDR_CKE1 (6,8)
C652
0.1U_0402_16V4Z 2 2
er Fo
DDR_A_MA8 DDR_A_MA5
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
0.1U_0402_16V4Z
DDR_A_MA12 DDR_A_MA9
CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2
C651
0.1U_0402_16V4Z 2 2
2
yb
(6,8) DDR_A_BS2
CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1
D
DDR_A_DM[0..7] (6,8)
DDR_A_DM1
C
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
(6,8) DDR_CKE0
(6,8)
DDR_A_MA[0..15] (6,8)
DDR_A_D12 DDR_A_D13
C650 C
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_D6 DDR_A_D7
C664
DDR_A_D8 DDR_A_D9
DDR_A_D4 DDR_A_D5
4.7U_0603_6.3V6K
DDR_A_D2 DDR_A_D3
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
C663
DDR_A_DM0
VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26
0.1U_0402_16V4Z
2
VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25
C662
C648 C649 2
ME@
0.1U_0402_16V4Z
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
DDR_A_D0 DDR_A_D1
1
m .ru
1
1000P_0402_50V7K
0.1U_0402_16V4Z
D
1
2
+1.5V JDIMM2
+VREF_DQ
3
Compal Secret Data
Security Classification 2010/06/30
Issued Date
2012/06/30
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
3
2
Title
Compal Electronics, Inc. DDR3 SODIMM-II Socket
Size Document Number Custom Date:
Rev 1.0
LA6755P/7P
Tuesday, November 30, 2010
Sheet 1
9
of
48
5
4
3
2
1
LCD POWER CIRCUIT +LCDVDD
+5VALW
1
+3VS
D
R458 150_0603_1%
LVDS_A0 LVDS_A0#
1
3
2
1 2 G
2
1
2
2
1
2
1
Change footprint 20100812
LVDS_A2 LVDS_A2# LVDS_ACLK LVDS_ACLK#
2
(5) APU_ENVDD
IN
3
1
Q82 AP2301GN-HF_SOT23-3
C670
W=60mils
0.1U_0402_16V4Z +LCDVDD 1
Q83 DTC124EKAT146_SC59-3
C671 4.7U_0603_6.3V6K
2
pop R490 instead of R491 20100727
R477 1
+LEDVDD
AMD check list update 20101110
2
+5VS
R487 2K_0402_5%
GNDGND
USB20_N1 (14) USB20_P1 (14)
1
CMOS
1 R484
LVDS_A1# LVDS_A1 LVDS_A2# LVDS_A2
(31)
470P_0402_50V7K
B
R485 10K_0402_5%
Q84 +5VS
R927 1 @
+3VS
R928 1 CMOS@ 2 0_0402_5%
+5VS_CMOS
2 0_0402_5%
AP2301GN-HF_SOT23-3
3
1 @ C679
CMOS@
100K_0402_5%
1
2
+5VALW
R488
20100728
R938 0_0402_5% @
2
20100728
2
IN
3
A
2010/06/30
Issued Date
2
R880 150K_0402_5%
CMOS@
2
C676 0.1U_0402_16V4Z 2 CMOS@
+3VS_CMOS 1 C681 10U_0805_10V4Z 2 CMOS@
Q85 DTC124EKAT146_SC59-3 CMOS@
2012/06/30
Deciphered Date
1 R489 0_0603_5% CMOS@
0.1U_0402_16V4Z
CMOS@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3
CMOS1 C680 1 2
Compal Secret Data
Security Classification
+CMOS_PW
1
CMOS@ Change footprint 20100812
2
DISPOFF#
(31) CMOS_OFF#
4
DISPOFF#
2
RB751V_SOD323 D4 @
CMOS Camera
For EMI
5
2 0_0402_5%
1
BKOFF#
LVDS_ACLK# LVDS_ACLK
31
@ R483 10K_0402_5%
2
LVDS_A0# LVDS_A0
C
470P_0402_50V7K
2
1
USB20_N1 USB20_P1
APU_BLPWM
1 @ C677
+3VS
+3VS_CMOS
ACES_87142-3041-BS ME@
2
2
R486 2K_0402_5% EDID_CLK EDID_DATA
32
1
1
B
JLVDS1 1 1 3 3 5 5 7 7 9 9 11 11 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29
(31)
2
CE_EN
C674 4.7U_0805_25V6-K
1
(31)
1
CE_EN INVTPWM DISPOFF#
2
0.1U_0402_16V4Z
2
+3VS
2
1
(60 MIL)
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1
yb
+LCDVDD_CONN
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1
C672
C
ENBKL
2 0_0805_5%
er Fo
C673 680P_0402_50V7K @
2
R480 100K_0402_1%
B+
1 R479
1
2 Change footprint 20100812
0_0402_5%
2
ru
(5) APU_ENBKL
1
2
INVTPWM
1
2 0_0402_5% 2 0_0402_5%
OUT
C
@
GND
1 R491 1 R490
(31) INVT_PWM
2
FBMA-L11-201209-221LMA30T_0805
R473 @ 100K_0402_5%
(5) APU_BLPWM
+LCDVDD_CONN
L33
1
(5) LVDS_ACLK (5) LVDS_ACLK#
@ 680P_0402_50V7K C675
Change footprint 20100812
C669 4.7U_0603_6.3V6K
S LVDS_A1 LVDS_A1#
1
LVDS_A2 LVDS_A2#
Q81 2N7002H_SOT23-3
220K_0402_5%
OUT
LVDS_A1 LVDS_A1#
(5) (5)
R462
GND
(5) (5)
D
LVDS_A0 LVDS_A0#
3
(5) (5)
EDID_CLK EDID_DATA
EDID_CLK EDID_DATA
D
W=60mils Change footprint 20100812
m .ru
(5) (5)
R459 100K_0402_5%
Title
A
Compal Electronics, Inc. LVDS/CAMERA
Size B Date:
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010
Sheet 1
10
of
48
5
4
3
2
1
+5VS (5) (5) (5) (5) (5) (5) (5) (5)
R513 R514 R515 R516 R517 R518 R519 R520
HDMI_CLKP HDMI_CLKN HDMI_TX0P HDMI_TX0N HDMI_TX1P HDMI_TX1N HDMI_TX2P HDMI_TX2N
1 1 1 1 1 1 1 1
HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@
2 2 2 2 2 2 2 2
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
HDMI_CLK+_CONN HDMI_CLK-_CONN HDMI_TX0+_CONN HDMI_TX0-_CONN HDMI_TX1+_CONN HDMI_TX1-_CONN HDMI_TX2+_CONN HDMI_TX2-_CONN
+5VS
3
3 HDMIDAT_R
1
1
@ D5 BAT54S-7-F_SOT23-3
2
HDMICLK_R
@ D6 BAT54S-7-F_SOT23-3
2
D
D
+3VS
@ L34 HDMI_CLK+_CONN
4
3
3
HDMI_CLK-_CONN
HDMI_CLK-_CONN
1 R501
HDMI_TX0+_CONN
WCM-2012-900T_4P
1 R502
HDMI_TX0-_CONN
@ L35 HDMI_TX0P
1
1
2
2
HDMI_TX0+_CONN
1 R503
HDMI_TX1+_CONN
1 R505
HDMI_TX0N
4
4
3
3
HDMI_TX0-_CONN
HDMI_TX1-_CONN
1 R506
HDMI_TX2+_CONN
WCM-2012-900T_4P
1 R508
HDMI_TX2-_CONN
C
HDMI_TX1P
1
HDMI_TX1N
4
1 4
2
2
HDMI_TX1+_CONN
3
3
HDMI_TX1-_CONN
1 R509
499_0402_1% 499_0402_1%
499_0402_1%
2
4
3
2
S
Q87 2N7002H_SOT23-3 HDMI@
@ R512 100K_0402_5%
HDMI_TX2+_CONN
NEAR CONNECT 3
D
2 G 3
4
1
HDMI_TX2-_CONN
er Fo
WCM-2012-900T_4P
B
R524 1
2
yb 2
1
@ R816
2 0_0402_5%
D7 1
+5VS
+5VS_HDMI 1
HDMI@ R522 2K_0402_5%
2
RB491D_SC59-3 HDMI@
HDMI@ F2 1.1A_6V_SMD1812P110TF
C690 0.1U_0402_16V4Z HDMI@ B
HDMI@ R523 2K_0402_5%
2
AMD check list update 20101110
HDMI_HPD
JHDMI1 HDMI_HPD
@ D8 BAT54S-7-F_SOT23-3
HDMIDAT_R HDMICLK_R HDMI_CLK-_CONN
1
2
2
0_0805_5%
HDMI_CLK+_CONN HDMI_TX0-_CONN
@ R528 100K_0402_5%
HDMI_TX0+_CONN HDMI_TX1-_CONN
2
R530 100K_0402_5% HDMI@
@ R815
HDMI_HPD
@ R527 200K_0402_5% 1
1 3
R525 1 2 150K_0402_5% @
1
HDMI_DET
C
(5)
2 B
E
1 2
C
0_0402_5%
1
Add fuse for safety requirement +5VS_HDMI_F 20100923
3
+3VS
C @ Q88 MMBT3904_NL_SOT23-3
HDMIDAT_R
3
@ R521
+5VS
0_0402_5% HDMI@
4
2N7002KDWH_SOT363-6 Q86B HDMI@
2
HDMI_TX2N
1
(5) HDMI_DATA
499_0402_1%
1
@ L37 HDMI_TX2P
HDMICLK_R
6
2N7002KDWH_SOT363-6 Q86A HDMI@
499_0402_1%
+5VS
WCM-2012-900T_4P
1
(5) HDMI_CLK
499_0402_1%
1
@ L36
499_0402_1%
2
4
Change footprint 20100812
1
HDMI_CLKN
499_0402_1%
5
2 HDMI@ 2 HDMI@ 2 HDMI@ 2 HDMI@ 2 HDMI@ 2 HDMI@ 2 HDMI@ 2 HDMI@
2
1 R500
2
HDMI_CLK+_CONN
2
2
1
2
1
1
m .ru
1
ru
HDMI_CLKP
HDMI_TX1+_CONN HDMI_TX2-_CONN HDMI_TX2+_CONN
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKG1 CK_shield G2 CK+ G3 D0G4 D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+
20 21 22 23
SUYIN_100042GR019M23DZL ME@ A
A
2010/06/30
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2012/06/30
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
HDMI Connector Size Document Number Custom Date:
Rev 1.0
LA6755P/7P
Tuesday, November 30, 2010
Sheet 1
11
of
48
(5)
DAC_GRN
(5)
DAC_BLU
C
FCM1608CF-121T03 0603 1 2 L38 FCM1608CF-121T03 0603 1 2 L39 FCM1608CF-121T03 0603 1 2 L40 1 1
DAC_RED DAC_GRN DAC_BLU
1
DAC_RED
1
(5)
1
1
B
1 R533 150_0402_1%
2
R532 150_0402_1%
2
2
R531 150_0402_1%
1 C692
2
C693
2
2
C694 10P_0402_50V8J
10P_0402_50V8J 10P_0402_50V8J
CLOSE TO CONN
D
E
RED
1
GREEN BLUE
1
C697
1 C695
2
2
2
C696 10P_0402_50V8J
10P_0402_50V8J10P_0402_50V8J
+5VS
+5VS
3
3
m .ru
A
1
+5VS
3
BLUE
2
R537
1
2
1
G
A
CRT_HSYNC_1
4
Y
3 +CRT_VCC
1
2
R543
1
1K_0402_5%
5 P G
A
OE#
2
(5) CRT_VSYNC
1
2
CRT_VSYNC_1
4
Y
3
@ C702 10P_0402_50V8J
4
(5) CRT_DDC_CLK
2 4
F1
1
1
2 1
RB491D_SC59-3
W=40mils
@ C703 100P_0402_50V8J
@
2 0_0402_5%
1 R965
@
2 0_0402_5%
JCRT1 RED CRT_DDC_DAT_CONN GREEN
JVGA_VS
1
1
2
2
CRT_DDC_CLK_CONN @ C704 68P_0402_50V8K
1
2
Compal Secret Data
Security Classification 2010/06/30
Issued Date
Deciphered Date
2012/06/30
C
Title
G G
16 17
C698
CONTE_80431-5K1-152
100P_0402_50V8J
ME@
4
Compal Electronics, Inc. CRT Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
2
6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
CRT_DDC_CLK_CONN
6
1 R964
3
C691 0.1U_0402_16V4Z
1.1A_6V_SMD1812P110TF
JVGA_HS BLUE
AMD check list update 20101110
A
@ D13 BAT54S-7-F_SOT23-3
CRT Connector
+CRT_VCC
2
2N7002KDW H_SOT363-6 Q89B
2N7002KDW H_SOT363-6 Q89A
2
2 @ D12 BAT54S-7-F_SOT23-3
D14
CRT_DDC_DAT_CONN
(5) CRT_DDC_DATA
1
JVGA_VS
1
2
+5VS
yb
3
3 JVGA_HS
1
R549 2K_0402_5%
C
5
Change footprint 20100812
+5VS
3
2
R548 2K_0402_5%
2
R547 2K_0402_5%
1
1
+CRT_VCC
2
R546 2K_0402_5%
2
+3VS
1
1
+3VS
+5VS
1
2
3
@ D11
JVGA_VS
1 2 L42 FCM1608CF-121T03 0603
U24 SN74AHCT1G125DCKR_SC70-5
@ D10 BAT54S-7-F_SOT23-3
@ C700 10P_0402_50V8J
2
1 C701 0.1U_0402_16V4Z
JVGA_HS
1 2 L41 FCM1608CF-121T03 0603
U23 SN74AHCT1G125DCKR_SC70-5
BAT54S-7-F_SOT23-3
2
ru
2
(5) CRT_HSYNC
er Fo
P
5
2 1
2
1K_0402_5%
OE#
C699 0.1U_0402_16V4Z
RED
1
2
@ D9 BAT54S-7-F_SOT23-3
+CRT_VCC
GREEN
1
D
Size Document Number Custom Date:
Rev 1.0
LA6755P/7P
Tuesday, November 30, 2010
Sheet E
12
of
48
A
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
PCIE_FTX_DRX_P0 PCIE_FTX_DRX_N0 PCIE_FTX_DRX_P1 PCIE_FTX_DRX_N1
2
close to FCH within 1" R564 1 R565 1
DISP_CLK DISP_CLK#
2 0_0402_5% 2 0_0402_5%
M23 P23
DISP_CLK_R DISP_CLK#_R
U29 U28
2 0_0402_5% 2 0_0402_5%
(26) CLK_PCIE_LAN (26) CLK_PCIE_LAN#
R571 1 R572 1
2 0_0402_5% 2 0_0402_5%
LAN WLAN
(30) CLK_PCIE_WLAN (30) CLK_PCIE_WLAN#
R573 1 R574 1
2 0_0402_5% 2 0_0402_5%
V21 T21
CLK_PCIE_VGA_R CLK_PCIE_VGA#_R
V23 T23
CLK_PCIE_LAN_R CLK_PCIE_LAN#_R
L29 L28
CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R
N29 N28
M29 M28
3
NB_DISP_CLKP NB_DISP_CLKN NB_HT_CLKP NB_HT_CLKN
GPP_CLK0P GPP_CLK0N GPP_CLK1P GPP_CLK1N GPP_CLK2P GPP_CLK2N GPP_CLK3P GPP_CLK3N GPP_CLK4P GPP_CLK4N
yb
L24 L23
SLT_GFX_CLKP SLT_GFX_CLKN
P25 M25 P29 P28
N26 N27
C C722 22P_0402_50V8J 1 2
L26
25M_X1
Y5
1M_0603_5% 25M_CLK_X2 R576
L27
25M_X2
2
@ R562 20M_0402_5% @R562 1 2 Change from 22P to 18P for RTC correction 20101012 C719 RTC_32KHO 1 2
H24 H25 J27 J26 H29 H28 G28 J25 AA18 AB19
32K_X2 RTCCLK INTRUDER_ALERT_L VDDBT_RTC_G
R563 20M_0603_5%
OSC
NC
3
1
OSC
NC
2
32.768KHZ_12.5PF_9H03200413 RTC_32KHI
PE_GPIO1 (20,21,43)
+3VS
APU_PWRGD
3
1
H_PWRGD_L (44)
SB_ARST#_GATE FDV301N_NL_SOT23-3 Q90
For PX function reserved
1
2 0_0402_5%
R575 1 R854 1
LPCCLK0 (17)
2 22_0402_5% 2 0_0402_5%
@
2
LPC_CLK0_EC (31) CLK_PCI_DB (30)
LPC_AD0 (30,31) LPC_AD1 (30,31) LPC_AD2 (30,31) LPC_AD3 (30,31) LPC_FRAME# (30,31)
@ C1011 100P_0402_50V8J
3
Reserve for EMI for PVT build 20101005
SERIRQ (31)
ALLOW_STOP# (5) FCH_PROCHOT# (5) APU_PWRGD (5) LDT_RST# (5)
C1
RTC_32KHI
C2
RTC_32KHO
D2 B2 B1
@ 1 R920 @ 1 R921
SUSCLK
2 0_0402_5%
FCH_RTCX1_OUT (31)
2 0_0402_5%
FCH_RTCX2_OUT (31)
(31)
W=20mils
+RTCBATT 1 R577
2 510_0402_5%
1 C723 2
2012/06/30
CLRP1 @ SHORT PADS
4
for Clear CMOS
Title
Compal Electronics, Inc. FCH PCIE/PCI/ACPI/LPC/RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C
4
R568 10K_0402_5%
G21 H21 K19 G22 J24
Deciphered Date
2
Y4
18P_0402_50V8J
Compal Secret Data 2010/06/30
Issued Date
B
Close to SB
(17) (17) (17) (17) (17)
+1.8VS
21807-A11-HUDSON-M1_FCBGA605
Security Classification
A
20101012
18P_0402_50V8J
25MHZ_20PF_7A25000012
4
2 100K_0402_5%
C720 1 2
2
C721 22P_0402_50V8J
ALLOW_LDTSTP/DMA_ACTIVE_L PROCHOT_L LDT_PG LDT_STP_L LDT_RST_L 32K_X1
25M_CLK_X1
PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27
14M_25M_48M_OSC
1
2
GPP_CLK8P GPP_CLK8N
PX@ 2 100K_0402_5%
CLK_PCI_DB_R (17)
GPP_CLK7P GPP_CLK7N
RTC
1
L25
GPP_CLK6P GPP_CLK6N
AJ6 AG6 AG4 AJ4
@
PE_GPIO0 R918 1
PE_GPIO0 (18)
R853 1
LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME_L LDRQ0_L LDRQ1_L/CLK_REQ6_L/GPIO49 SERIRQ/GPIO48
CPU
T29 T28
GPP_CLK5P GPP_CLK5N
INTE_L/GPIO32 INTF_L/GPIO33 INTG_L/GPIO34 INTH_L/GPIO35
LPC
T25 V25
CPU_HT_CLKP CPU_HT_CLKN
PE_GPIO1 R919 1
D
R569 1 R570 1
PCIE_RCLKP/NB_LNK_CLKP PCIE_RCLKN/NB_LNK_CLKN
1
S
(18) CLK_PCIE_VGA (18) CLK_PCIE_VGA#
APU_CLK_R APU_CLK#_R
PAD T92 AA1 AA4 AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2 AE9 AD9 AC11 AF6 AF4 AF3 AH2 AG2 AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5 AF5 AE6 AE4 AE11 AH5 AH4 AC12 AD12 AJ5 AH6 AB12 AB11 AD7
G
2 0_0402_5% 2 0_0402_5%
APU_CLK APU_CLK#
GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N
CLOCK GENERATOR
R566 1 R567 1
(5) (5)
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N
er Fo
T26 T27
PCI_CLK3 (17) PCI_CLK4 (17)
V2
10K_0402_5%
1
PCIE_CALRP PCIE_CALRN
AA28 AA29 Y29 Y28 Y26 Y27 W28 W29 AA22 Y21 AA25 AA24 W23 V24 W24 W25
PCIE_FRX_DTX_P0 PCIE_FRX_DTX_N0 PCIE_FRX_DTX_P1 PCIE_FRX_DTX_N1
(5) (5)
AD29 AD28
PCI_CLK1 (17)
1
590_0402_1% 2K_0402_1%
2 2 2 2
AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31 CBE0_L CBE1_L CBE2_L CBE3_L FRAME_L DEVSEL_L IRDY_L TRDY_L PAR STOP_L PERR_L SERR_L REQ0_L REQ1_L/GPIO40 REQ2_L/CLK_REQ8_L/GPIO41 REQ3_L/CLK_REQ5_L/GPIO42 GNT0_L GNT1_L/GPO44 GNT2_L/GPO45 GNT3_L/CLK_REQ7_L/GPIO46 CLKRUN_L LOCK_L
PCI I/F
(26) (26) (30) (30)
PCIE_FTX_C_DRX_P0 PCIE_FTX_C_DRX_N0 PCIE_FTX_C_DRX_P1 PCIE_FTX_C_DRX_N1
1 1
PAD T96 PCI_CLK2
2
(26) (26) (30) (30)
1 1 1 1
UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N
PCIRST_L
W2 W1 W3 W4 Y1
1
LAN WLAN
2 2 C715 C716 C717 C718
UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N
AE24 AE23 AD25 AD24 AC24 AC25 AB25 AB24
PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38 PCICLK4/14M_OSC/GPO39
2
R560 R561
+PCIE_VDDAN
PCIE_RST_L A_RST_L
2
UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N
AD26 AD27 AC28 AC29 AB29 AB28 AB26 AB27
1
(6) (6) (6) (6) (6) (6) (6) (6)
UMI_RX0P_C UMI_RX0N_C UMI_RX1P_C UMI_RX1N_C UMI_RX2P_C UMI_RX2N_C UMI_RX3P_C UMI_RX3N_C
PCI EXPRESS I/F
update for PX function 20100811
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
2 2 2 2 2 2 2 2
P1 L1
2
PLT_RST# (26,30,31)
UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N
1 1 1 1 1 1 1 1
U26E A_RST#
10K_0402_5%
1 PX@ 2 R559 0_0603_5%
(6) (6) (6) (6) (6) (6) (6) (6)
C707 C708 C709 C710 C711 C712 C713 C714
1 33_0402_5%
1
NC7SZ08P5X_NL_SC70-5
R557 2
R558
3
PLT_RST#
R554
150P_0402_50V8J C706 1 2
PX_RST# (18)
2
4
1U_0402_6.3V4Z
Y A
m .ru
5 B
2 1
E
Watchdog timer on NB_PWRGD enable for pull-up +3VS disable for pull-down 20100527 @
T78 PAD
PCI CLKS
R555 100K_0402_5%
D
ru
1
update for PX function 20100811
@ U25
1
PLT_RST#
C
1
0.1U_0402_16V4Z SB_ARST#_GATE 2
P
2
B
+3VALW
C705
G
@
D
Size Document Number Custom Date:
Rev 1.0
LA6755P/7P
Tuesday, November 30, 2010
Sheet E
13
of
48
A
B
C
D
E
+3VALW
U26A
G1
(31) EC_RSMRST# 20100802 R580 2
@
(33) SATA_DET# (26) LAN_CLKREQ#
1 0_0402_5%
R581 2
1 0_0402_5%
5 P 4 2
ICH_POK (31)
A
1
VGATE (31,44)
@ NC7SZ08P5X_NL_SC70-5 C725 U27 @ 0.1U_0402_16V7K
2
1
1
2
@ (19) PEG_CLKREQ# C1009 100P_0402_50V8J
@
@
USB_OC7#
R583 1 R585 1
2 33_0402_5% 2 33_0402_5%
R593
yb
10K_0402_5% R910
10K_0402_5% R911 2 BACO@ 1
nonHDMI@ 2 1
10K_0402_5% R912 PX@ 1 2
R596
R913
0_0402_5%
SD028000080 PX3@
2 10K_0402_5%
1
2 10K_0402_5%
1
C
10K_0402_5% R913
10K_0402_5% R914 2 UMA@ 1
2 HDMI@ 1
10K_0402_5% R915 2 UMA@ 1
R600
BOARD Config.
2 10K_0402_5% 2 10K_0402_5%
T85 T86
PAD PAD
GPIO187 E23 GPIO188 E24 F21 G29
GPIO189 GPIO190 GPIO191
For BRD Config.
GPIO189
GPIO190
GPIO191
T1 T4 L6 L5 T9 U1 U3 T2 U2 T5 V5 P5 M5 P9 T7 P7 M7 P4 M9 V7
D27 F28 F29 E27
AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO167 AZ_SDIN1/GPIO168 AZ_SDIN2/GPIO169 AZ_SDIN3/GPIO170 AZ_SYNC AZ_RST_L GBE_COL GBE_CRS GBE_MDCK GBE_MDIO GBE_RXCLK GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0 GBE_RXCTL/RXDV GBE_RXERR GBE_TXCLK GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0 GBE_TXCTL/TXEN GBE_PHY_PD GBE_PHY_RST_L GBE_PHY_INTR
GBE LAN
+3VALW +3VALW +3VALW
GPIO189 GPIO190 GPIO191
M3 N1 L2 M2 M1 M4 N2 P2
2 10K_0402_5%
1
BLINK/USB_OC7_L/GEVENT18_L USB_OC6_L/IR_TX1/GEVENT6_L USB_OC5_L/IR_TX0/GEVENT17_L USB_OC4_L/IR_RX0/GEVENT16_L USB_OC3_L/AC_PRES/TDO/GEVENT15_L USB_OC2_L/TCK/GEVENT14_L USB_OC1_L/TDI/GEVENT13_L USB_OC0_L/TRST_L/GEVENT12_L
J10 H11
1
H9 J8
USB_HSD13P USB_HSD13N
B12 A12
USB_HSD12P USB_HSD12N
F11 E11
USB_HSD11P USB_HSD11N
E14 E12
Root
USB_HSD10P USB_HSD10N
J12 J14
USB_HSD9P USB_HSD9N
A13 B13
USB_HSD8P USB_HSD8N
D13 C13
USB_HSD7P USB_HSD7N
G12 G14
USB20_P7 (30) USB20_N7 (30)
USB_HSD6P USB_HSD6N
G16 G18
USB20_P6 (34) USB20_N6 (34)
USB_HSD5P USB_HSD5N
D16 C16
USB20_P5 (33) USB20_N5 (33)
USB_HSD4P USB_HSD4N
B14 A14
USB20_P4 (34) USB20_N4 (34)
USB_HSD3P USB_HSD3N
E18 E16
USB20_P3 (33) USB20_N3 (33)
USB_HSD2P USB_HSD2N
J16 J18
USB20_P2 (33) USB20_N2 (33)
B17 A17
USB20_P1 (10) USB20_N1 (10)
A16 B16
USB20_P0 (33) USB20_N0 (33)
PS2_DAT/SDA4/GPIO187 PS2_CLK/SCL4/GPIO188 SPI_CS2_L/GBE_STAT2/GPIO166 FC_RST_L/GPO160
USB_HSD1P USB_HSD1N USB_HSD0P USB_HSD0N
SCL2/GPIO193 SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196 EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/GPIO199 EC_PWM3/EC_TIMER3/GPIO200
EMBEDDED CTRL
R5911 R5921 +3VALW
HDA_BITCLK HDA_SDOUT HDA_SDIN0
2 33_0402_5% HDA_SYNC 2 33_0402_5% HDA_RST#
R589 1 R590 1
(28) HDA_SYNC_AUDIO (28) HDA_RST_AUDIO#
3
H3 D1 E4 D4 E8 F7 E7 F8
USB_OC5#
(46) ODD_DA#_FCH (46) ODD_DETECT# (34) USB_OC2# (33) USB_OC1# (33) USB_OC0#
(28) HDA_BITCLK_AUDIO (28) HDA_SDOUT_AUDIO (28) HDA_SDIN0
Pull-down for enable high performance mode 20100527 (required for M1)
1 0_0402_5%
CLK_REQ4_L/SATA_IS0_L/GPIO64 CLK_REQ3_L/SATA_IS1_L/GPIO63 SMARTVOLT1/SATA_IS2_L/GPIO50 CLK_REQ0_L/SATA_IS3_L/GPIO60 SATA_IS4_L/FANOUT3/GPIO55 SATA_IS5_L/FANIN3/GPIO59 SPKR_GPIO66 SCL0_GPIO43 SDA0_GPIO47 SCL1_GPIO227 SDA1_GPIO228 CLK_REQ2_L/FANIN4_GPIO62 CLK_REQ1_L/FANOUT4_GPIO61 IR_LED_L/LLB_L/GPIO184 SMARTVOLT2/SHUTDOWN_L/GPIO51 DDR3_RST_L/GEVENT7_L GBE_LED0/GPIO183 GBE_LED1/GEVENT9_L GBE_LED2/GEVENT10_L GBE_STAT0/GEVENT11_L CLK_REQG_L/GPIO65_OSCIN
HD AUDIO
@
PEG_CLKREQ#_R 2 10K_0402_5% FCH_SMCLK1 2 10K_0402_5% FCH_SMDAT1 2 10K_0402_5% EC_RSMRST# 2 2.2K_0402_5% HDA_BITCLK 2 10K_0402_5% HDA_SDIN0 2 10K_0402_5% HDA_SDOUT 2 10K_0402_5%
@
(31) EC_LID_OUT#
Reserve for EMI for PVT build 20101005 1 R823 1 R587 1 R588 1 R606 1 R607 1 R608 1 R609
2
USB_FSD0P/GPIO185 USB_FSD0N
USB OC
Reserve for EMI for PVT build 20101005
R582
RSMRST_L
er Fo
@ C1008 100P_0402_50V8J
1
2
3
2
(30) WLAN_CLKREQ#
B
Y G
(44) FCH_PWRGD
USB_FSD1P/GPIO186 USB_FSD1N
USB 2.0
+3VS @ C724 0.1U_0402_16V7K 1 2
2 11.8K_0402_1%
10mils and >> BACO mode Low >>> Normal Operation
1 2 0_0402_5% @
+5VS
3
S
2 G
PX_EN
R906
2
1
D
3
(19)
(18,40,43) VGA_PWRGD
R907 10K_0402_5% BACO@
2
R340 10K_0402_5% @ PX_MODE_AND
+5VS +3VGS
1
1
D
3
2
RobsonXT-S3 BACO Size B Date:
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010
Sheet 1
20
of
48
5
4
3
2
1
+VGA_PCIE TO +1.0VGS
+3.3VS TO +3.3VGS
+1.0VS
+1.0VGS @
D
S
1 2 39K_0402_5%
Q120 2N7002H_SOT23-3 PX@
2 G
Change footprint 20100812
C
+1.5VGS J3
S
Q74 2N7002H_SOT23-3 PX@
C344 0.1U_0603_25V7K 2 PX@
1 2 1 3
C
+1.8VGS
1
2
4
R348 470_0603_5% @
+VSB
1
For VGA power sequence 20100816
2
R350 300K_0402_5% PX@
PE_GPIO1#
yb
Change footprint 20100812
For VGA power sequence 20100816 PX@ R352 1 2 47K_0402_5% R354 Q78 0_0402_5% @ 2N7002H_SOT23-3 PX@
D
D
S
2 G
2 1 R833 2 PE_GPIO1# G 0_0402_5% Q76 @ 2N7002_SOT23 @
S
1
2
C352 0.1U_0603_25V7K PX@
B
Change footprint 20100812
C
PE_GPIO1# 1 R830 2 0_0402_5% PX3@
1
20100728
2
R346 0_0402_5% @
C976 0.1U_0603_25V7K PX@
Change from SB00000GV00 to SB548000210 J5 20101125 Change footprint U13 20100812 PX@ DMN3030LSS-13_SOP8L-8 8 1 7 2 1 1 1 6 3 C348 C349 C350 5 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z 2 PX@ 2 PX@ 2 PX@
1
2 G 3
PX_MODE# 1 R829 2 0_0402_5% BACO@
D
1
1
B
2
2
1
3
S
PX@ R345 2 1 150K_0402_5%
2
Need to pop for BACO function Should be unpop for PX3.0 20100728
2 1 R827 2 PX_MODE# G 0_0402_5% Q73 @ 2N7002_SOT23 1 R828 2 PE_GPIO1# @ 0_0402_5% @
PE_GPIO1#
2MM
1
D
S
@
R343 470_0603_5% @
1
20100728 R344 20K_0402_5% PX@
1
+1.8VS
2
+VSB
R944 0_0402_5% @
+1.8VS TO +1.8VGS
er Fo
4
+1.5V TO +1.5VGS
3
2 1 1 @ JUMP_43X79 Change from SB00000GV00 to SB548000210 20101125 Change footprint 20100812 U11 PX@ DMN3030LSS-13_SOP8L-8 8 1 7 2 1 1 1 C341 C342 6 3 C340 10U_0805_10V4Z 1U_0603_10V4Z 5 10U_0805_10V4Z PX@ PX@ 2 PX@ 2 2
ru
2
PX@
For VGA PWR sequence 20100928
PX@ R856
@ 2 1 R879 2 G 0_0402_5% Q125 2N7002_SOT23 @
1
2 0_0402_5%
PE_GPIO1#
+1.5V
D
For VGA power sequence 20100816
R839 20K_0402_5% PX@
R877 470_0603_5% @
1
R878
2
3
PE_GPIO1# 1
2
1
C985
4
2 1
+5VS
2 G Q124 2N7002_SOT23 @
@ Change footprint 20100812
10U_0805_10V4Z
1
PX@ C983
PX@
S
1
D
2
2
Change footprint 20100812
C351 0.1U_0603_25V7K PX@
1
1
C999 10U_0805_10V4Z 2 PX@
D
Change footprint 20100812
20K_0402_5% Q121 2N7002H_SOT23-3 PX@
PX@ U47 DMN3030LSS-13_SOP8L-8 8 1 7 2 6 3 5
1
1
S
2
3
D
2
PX@ R857
2 Q65 PX@ AP2301GN-HF_SOT23-3
R876 470_0603_5% @
m .ru
3
1
1
3
1
2
3
C982
PX@ R840 51K_0402_5%
1
1U_0603_10V4Z
10U_0805_10V4Z
J4
1
2MM
2 G
Change from SB00000GV00 to SB548000210 20101125 Change footprint 20100917
J2
PX@
2MM
1
For VGA power sequence 20100816
PE_GPIO1
1
@
2 D
2
C984
+3VGS
1U_0603_10V4Z
+3VS
+5VALW
+3VALW
1
Update design 20101001
+3VALW
BACO@ R924 100K_0402_5%
BACO@ R925 100K_0402_5%
PX_MODE# D
2 G 3
1
1
(20,43) PX_MODE
2
IN
1 2
2 2
3
(13,20,43) PE_GPIO1
OUT
Q123 DTC124EKAT146_SC59-3 PX@
GND
PE_GPIO1#
A
1
PX@ R875 100K_0402_5%
S
A
Q127 2N7002H_SOT23-3 BACO@ Change footprint 20100812
BOM structure update 20101001
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2010/06/30
Issued Date
Deciphered Date
2012/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
RobsonXT-S3 DC Interface Size Document Number Custom
Rev 1.0
LA6755P/7P
Date: Tuesday, November 30, 2010
Sheet 1
21
of
48
5
4
3
2
change from SM010032020 to SD013000080 20101012
DPA_VDD18#1 DPA_VDD18#2
AG20 AG21
DPE_VDD10#1 DPE_VDD10#2
DPA_VDD10#1 DPA_VDD10#2
AF6 AF7
AG14 AH14 AM14 AM16 AM18
DPE_VSSR#1 DPE_VSSR#2 DPE_VSSR#3 DPE_VSSR#4 DPE_VSSR#5
DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5
AE1 AE3 AG1 AG6 AH5
AF16 AG17
DPF_VDD18#1 DPF_VDD18#2
DPB_VDD18#1 DPB_VDD18#2
AF22 AG22
DPF_VDD10#1 DPF_VDD10#2
DPB_VDD10#1 DPB_VDD10#2
AF8 AF9
AF23 AG23 AM20 AM22 AM24
DPF_VSSR#1 DPF_VSSR#2 DPF_VSSR#3 DPF_VSSR#4 DPF_VSSR#5
DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5
AF10 AG9 AH8 AM6 AM8
110mA
+DPEF_VDD18
+DPEF_VDD10
AF17
+DPEF_VDD18
DPAB_CALR
20mA
DP PLL POWER
DPA_PVDD DPA_PVSS
20mA
AG19 AF20
1
D
+1.0VGS PX@ L21 1 2 MBK1608121YZF_0603
2
2
+DPAB_VDD18
AE13 AF13
AE10
20mA
DPE_PVDD DPE_PVSS
1
PX@ L19 +1.8VGS 2 1 MBK1608121YZF_0603
C
+DPAB_VDD10
ru
DPEF_CALR
AG18 AF19
B
2
er Fo
1 150_0402_1%
+DPEF_VDD18
1
110mA
PX@ R355 2
2
total:220mA
+DPAB_VDD10
130mA
C
2
10U_0603_6.3V6M
DPE_VDD18#1 DPE_VDD18#2
+DPEF_VDD10
AE11 AF11
1
10U_0603_6.3V6M
130mA
1U_0402_6.3V4Z C359 PX@
2
DP A/B POWER
0.1U_0402_10V6K C358 PX@
C357 PX@
DP E/F POWER AG15 AG16
1
1U_0402_6.3V4Z C364 PX@
2
U8G
total:300mA
0.1U_0402_10V6K C363 PX@
2
1
1
m .ru
2
1
+DPAB_VDD18
0.1U_0402_10V6K
1
+DPEF_VDD18
C362 PX@
2
total:240mA@LVDS total:220mA@DP C356 PX@
PX@ L20 2 1 MBK1608121YZF_0603
1U_0402_6.3V4Z C361 PX@
+1.0VGS
2
1
0.1U_0402_10V6K
2
1
1U_0402_6.3V4Z C355 PX@
1
C353 PX@
D
change from SM010032020 to SD013000080 20101012
total:440mA@LVDS total:300mA@DP 10U_0603_6.3V6M C354 PX@
PX@ L18 2 1 MBK1608121YZF_0603
10U_0603_6.3V6M C360 PX@
+1.8VGS
1
DPB_PVDD DPB_PVSS
2 150_0402_1% +DPAB_VDD18
AG8 AG7
20mA
DPF_PVDD DPF_PVSS
R356 1 PX@
B
+DPAB_VDD18
AG10 AG11
216-0774207-A11ROB_FCBGA631
C
yb
PX@
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/30
Deciphered Date
2012/06/30
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
RobsonXT-S3 DP PWR Size B Date:
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010
Sheet 1
22
of
48
5
4
3
2
1
+1.5VGS
+PCIE_VDDR
L16
+1.8VGS
AM30 +MPV18
75mA L8
+SPV18
75mA H7
+SPV10
120mAH8
2
B
1
2
1
2
0.1U_0402_10V6K
1
1U_0402_6.3V4Z C458 PX@
+1.0VGS PX@ L28 1 2 BLM15BD121SN1D_0402
10U_0603_6.3V6M C457 PX@
J7
C456 PX@
2
0.1U_0402_10V6K
1
C455 PX@
2
1U_0402_6.3V4Z
1
C454 PX@
2
10U_0603_6.3V6M
C453 PX@
1
PCIE_PVDD
SPV18 SPV10 SPVSS
2
10U_0603_6.3V6M
1
2
10U_0603_6.3V6M
1
2
1U_0402_6.3V4Z C384 PX@
1U_0402_6.3V4Z C383 PX@
1
+VGA_CORE
2
1
2
1
2
22U_0805_6.3V6M
2
1
22U_0805_6.3V6M PX@ C426
2
1
10U_0603_6.3V6M PX@ C425
2
1
PX@ C423
2
1
10U_0603_6.3V6M PX@ C424
2
1
1U_0402_6.3V4Z
2
1
1U_0402_6.3V4Z PX@ C420
2
1
1U_0402_6.3V4Z PX@ C419
2
1
1U_0402_6.3V4Z PX@ C418
2
1
1U_0402_6.3V4Z PX@ C416
1
1U_0402_6.3V4Z PX@ C415
11.8A(RMS)/12.9A(Peak)
delete 5 capacitors for new CRB reference 20100722
New Ref circuit 20100722
+BIF_VDDC
1
BIF_VDDC#1 BIF_VDDC#2
NC_MPV18
1U_0402_6.3V4Z C388 PX@
C385 PX@ C398 PX@
1U_0402_6.3V4Z C399 PX@
2
NC_VSSRHA
PX@ L26 1 2 BLM15BD121SN1D_0402
1
NC_VDDRHA
PLL
For Seymour, PCIE_PVDD is PCIE_VDDR.
+1.0VGS
1
er Fo
2
L17
0.1U_0402_10V6K
1
C449 PX@
2
1U_0402_6.3V4Z
1
C447 PX@
C446 PX@
2
10U_0603_6.3V6M
MEM CLK 1
D
m .ru
NC#3 NC#4
2
U8E
ru
V11 U11
NC#1 NC#2
2
ISOLATED CORE I/O
VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8
R21 U21
M13 M15 M16 M17 M18 M20 M21 N20
2
2
+VGA_CORE PX@ 1 2 L27 0_0603_5%
+VDDCI
2A(RMS)/3A(Peak)
1
2
1
2
1
2
1
2
10U_0603_6.3V6M
AA11 AA12
VDDR4#1 VDDR4#2 VDDR4#3
2
C452 PX@
0.1U_0402_10V6K
C430 PX@
C429 PX@ PX@ L25 1 2 BLM15BD121SN1D_0402
2
V12 Y12 U12
POWER
2
1U_0402_6.3V4Z
170mA 1
1
1U_0402_6.3V4Z
PX@
VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4
AA15 N15 N17 R13 R16 R18 Y21 T12 T15 T17 T20 U13 U16 U18 V21 V15 V17 V20 Y13 Y16 Y18 M11 M12
1
1U_0402_6.3V4Z C461 PX@
AA17 AA18 AB17 AB18
change from SM010009U00 to SD028000080 20101012
1
VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8 VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23
CORE
I/O
60mA
L24 1 2 BLM15BD121SN1D_0402
VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4
2
1
1920mA
PX@ C413
AA20 AA21 AB20 AB21
L23 L24 L25 L26 M22 N22 N23 N24 R22 T22 U22 V22
2
C451 PX@
2
LEVEL TRANSLATION
17mA
AB23 AC23 AD24 AE24 AE25 AE26 AF25 AG26
1U_0402_6.3V4Z
2
1
1U_0402_6.3V4Z
1
1U_0402_6.3V4Z C411 PX@
10U_0603_6.3V6M C410 PX@
1
2
C
PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8 PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12
+3VGS
C409 PX@
2
0.1U_0402_10V6K
2
1
C408 PX@
2
1
1U_0402_6.3V4Z
C404 PX@
1
PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8
C459 PX@
+VDDC_CT
110mA C405 PX@
PX@ L23 1 2 BLM15BD121SN1D_0402
VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17
1
1U_0402_6.3V4Z C460 PX@
change from SM010009U00 to SD028000080 20101012
10U_0603_6.3V6M
+1.8VGS
H13 H16 H19 J10 J23 J24 J9 K10 K23 K24 K9 L11 L12 L13 L20 L21 L22
0.1U_0402_10V6K C387 PX@
1
PCIE
1U_0402_6.3V4Z PX@ C414
MEM I/O
D
change from SM010032020 to SD013000080 20101012 +1.8VGS PX@ 2 1 L22 MBK1608121YZF_0603
504mA
U8D
1U_0402_6.3V4Z C380 PX@
2
1U_0402_6.3V4Z C403 PX@
2
1U_0402_6.3V4Z PX@ C417
2
1
1U_0402_6.3V4Z C466 PX@
2
1
0.1U_0402_10V6K
2
1
0.1U_0402_10V6K C392 PX@
2
1
0.1U_0402_10V6K C381 PX@
2
1
0.1U_0402_10V6K C391 PX@
2
1
0.1U_0402_10V6K C390 PX@
2
1
1U_0402_6.3V4Z C389 PX@
1
1U_0402_6.3V4Z C374 PX@
1
1U_0402_6.3V4Z C373 PX@
2
1U_0402_6.3V4Z C372 PX@
2
1
1U_0402_6.3V4Z C371 PX@
2
1
10U_0603_6.3V6M C370 PX@
1
22U_0805_6.3V6M C369 PX@
C365 PX@
2
22U_0805_6.3V6M C366 PX@
2.3A(RMS)/2.8A(Peak) 1
AA27 AB24 AB32 AC24 AC26 AC27 AD25 AD32 AE27 AF32 AG27 AH32 K28 K32 L27 M32 N25 N27 P25 P32 R27 T25 T32 U25 U27 V32 W25 W26 W27 Y25 Y32
M6 N11 N12 N13 N16 N18 N21 P6 P9 R12 R15 R17 R20 T13 T16 T18 T21 T6 U15 U17 U20 U9 V13 V16 V18 Y10 Y15 Y17 Y20 R11 T11
change from SM01000BZ00 to SD013000080 20100722
PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31
GND#56 GND#57 GND#58 GND#59 GND#60 GND#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86
GND
GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8 GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55
VSS_MECH#1 VSS_MECH#2 VSS_MECH#3
A3 A30 AA13 AA16 AB10 AB15 AB6 AC9 AD6 AD8 AE7 AG12 AH10 AH28 B10 B12 B14 B16 B18 B20 B22 B24 B26 B6 B8 C1 C32 E28 F10 F12 F14 F16 F18 F2 F20 F22 F24 F26 F6 F8 G10 G27 G31 G8 H14 H17 H2 H20 H6 J27 J31 K11 K2 K22 K6
C
A32 AM1 AM32
216-0774207-A11ROB_FCBGA631
B
216-0774207-A11ROB_FCBGA631
1u
10u
1.5VGS
VDDR1
10
10
5
1.8VGS
PCIE_VDDR
2
3
1
VGA_core
PCIE_VDDC
7
1
VDDC
25
6
VDDCI
6
2
1 C1005
0.1u
+
@
2
330U_D2E_2.5VM_R9M
dist.
reserve a 330u capacitor for PWR rwquest 20100920
C
Source
yb
+VGA_COREP
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/30
Deciphered Date
2012/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
RobsonXT-S3 PWR/GND Size C Date:
5
4
3
2
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010 1
Sheet
23
of
48
5
4
3
2
U8C M_DA[63..0] GDDR5/DDR3
(25) M_DQM[7..0]
M_DQS[7..0]
(25) M_DQS[7..0]
M_DQS#[7..0]
(25) M_DQS#[7..0]
C
+1.5VGS
1
1
+1.5VGS
R365 40.2_0402_1% PX@
2
2
R363 40.2_0402_1% PX@
R367 100_0402_1% PX@
1
2
C468 0.1U_0402_16V4Z PX@
2
R371 10K_0402_5% PX@ 1
R882 0_0402_5% @
R366 PX@ 1 2 0_0402_5%
R369 PX@ 1 2 51_0402_5% 1
2
DRAM_RST#_R C469 120P_0402_50V8J PX@ +1.5VGS
+1.5VGS
check!
MVREFDA MVREFSA
K26 J26
yb
2
(25) DRAM_RST#
1
B
DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63
R368 1 PX@ R370 1 PX@
2 243_0402_1% J25 2 243_0402_1% K25
DRAM_RST#_R
@ C470 1 2 1 2
C
R372 1 R373 1 A
@ @
2 51.1_0402_1% 2 51.1_0402_1%
MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA0_6 MAA0_7/MAA0_7 MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_13/BA2 MAA1_6/MAA_14/BA0 MAA1_7/MAA_15/BA1
K17 J20 H23 G23 G24 H24 J19 K19 J14 K14 J11 J13 H11 G11 J16 L15
M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_BA2 M_BA0 M_BA1
WCKA0_0/DQMA_0 WCKA0B_0/DQMA_1 WCKA0_1/DQMA_2 WCKA0B_1/DQMA_3 WCKA1_0/DQMA_4 WCKA1B_0/DQMA_5 WCKA1_1/DQMA_6 WCKA1B_1/DQMA_7
E32 E30 A21 C21 E13 D12 E3 F4
M_DQM0 M_DQM1 M_DQM2 M_DQM3 M_DQM4 M_DQM5 M_DQM6 M_DQM7
EDCA0_0/RDQSA_0 EDCA0_1/RDQSA_1 EDCA0_2/RDQSA_2 EDCA0_3/RDQSA_3 EDCA1_0/RDQSA_4 EDCA1_1/RDQSA_5 EDCA1_2/RDQSA_6 EDCA1_3/RDQSA_7
H28 C27 A23 E19 E15 D10 D6 G5
M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7
DDBIA0_0/WDQSA_0 DDBIA0_1/WDQSA_1 DDBIA0_2/WDQSA_2 DDBIA0_3/WDQSA_3 DDBIA1_0/WDQSA_4 DDBIA1_1/WDQSA_5 DDBIA1_2/WDQSA_6 DDBIA1_3/WDQSA_7
H27 A27 C23 C19 C15 E9 C5 H4
M_DQS#0 M_DQS#1 M_DQS#2 M_DQS#3 M_DQS#4 M_DQS#5 M_DQS#6 M_DQS#7
ADBIA0/ODTA0 ADBIA1/ODTA1
L18 K16
VRAM_ODT0 VRAM_ODT1
CLKA0 CLKA0B
H26 H25
M_CLK0 M_CLK#0
CLKA1 CLKA1B
G9 H9
M_CLK1 M_CLK#1
RASA0B RASA1B
G22 G17
M_RAS#0 M_RAS#1
CASA0B CASA1B
G19 G16
M_CAS#0 M_CAS#1
CSA0B_0 CSA0B_1
H22 J22
M_CS#0
CSA1B_0 CSA1B_1
G13 K13
M_CS#1
MVREFDA MVREFSA
CKEA0 CKEA1
K20 J17
M_CKE0 M_CKE1
MEM_CALRN0 MEM_CALRP0
WEA0B WEA1B
G25 H10
M_WE#0 M_WE#1
MAA1_8 MAA0_8
G14 G20
M_MA13
er Fo
2
C467 0.1U_0402_16V4Z PX@
2
2
R364 100_0402_1% PX@
1
MVREFSA
1
MVREFDA 1
K27 J29 H30 H32 G29 F28 F32 F30 C30 F27 A28 C28 E27 G26 D26 F25 A25 C25 E25 D24 E23 F23 D22 F21 E21 D20 F19 A19 D18 F17 A17 C17 E17 D16 F15 A15 D14 F13 A13 C13 E11 A11 C11 F11 A9 C9 F9 D8 E7 A7 C7 F7 A5 E5 C3 E1 G7 G6 G1 G3 J6 J1 J3 J5
ru
M_DQM[7..0]
GDDR5/DDR3
M_DA0 M_DA1 M_DA2 M_DA3 M_DA4 M_DA5 M_DA6 M_DA7 M_DA8 M_DA9 M_DA10 M_DA11 M_DA12 M_DA13 M_DA14 M_DA15 M_DA16 M_DA17 M_DA18 M_DA19 M_DA20 M_DA21 M_DA22 M_DA23 M_DA24 M_DA25 M_DA26 M_DA27 M_DA28 M_DA29 M_DA30 M_DA31 M_DA32 M_DA33 M_DA34 M_DA35 M_DA36 M_DA37 M_DA38 M_DA39 M_DA40 M_DA41 M_DA42 M_DA43 M_DA44 M_DA45 M_DA46 M_DA47 M_DA48 M_DA49 M_DA50 M_DA51 M_DA52 M_DA53 M_DA54 M_DA55 M_DA56 M_DA57 M_DA58 M_DA59 M_DA60 M_DA61 M_DA62 M_DA63
MEMORY INTERFACE
M_MA[13..0]
(25) M_MA[13..0]
0.1U_0402_16V4Z 0.1U_0402_16V4Z
GDDR5 L10
DRAM_RST
K8 L7
CLKTESTA CLKTESTB
R357 R358 R359 R360 R361 R362
1 1 1 1 1 1
X76@ 2 X76@ 2 X76@ 2 X76@ 2 X76@ 2 X76@ 2
VRAM_ID0
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
VRAM_ID0 (19)
VRAM_ID1
VRAM_ID1 (19)
VRAM_ID2
VRAM_ID2 (19)
D
Vendor M_BA2 M_BA0 M_BA1
(25) (25) (25)
m .ru
(25) M_DA[63..0]
D
1
+1.8VGS
VRAM_ID0 VRAM_ID1 VRAM_ID2
Hynix 512MB PN:SA000032460
1
0
0
Hynix 1GB PN:SA00003VS20
1
0
1
Samsung 512MB PN:SA000035700
0
1
0
Samsung 1GB PN:SA00003MQ20
0
1
1
C
ZZZ
ZZZ
Hynix
Samsung
H1G@ X7624938L01
VRAM_ODT0 (25) VRAM_ODT1 (25)
S1G@ X7624938L02
0706 update
M_CLK0 (25) M_CLK#0 (25)
update X76 PN
M_CLK1 (25) M_CLK#1 (25)
ZZZ
ZZZ
M_RAS#0 (25) M_RAS#1 (25)
B
M_CAS#0 (25) M_CAS#1 (25) M_CS#0
(25)
M_CS#1
(25)
Hynix
H512@ X7624938L03
Samsung
S512@ X7624938L04
M_CKE0 (25) M_CKE1 (25) M_WE#0 (25) M_WE#1 (25)
A
@ C471
Route 50ohms single-ended/100ohm diff and keep short debug only, for clock observation,if not need, DNI.
216-0774207-A11ROB_FCBGA631
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/06/30
Deciphered Date
2012/06/30
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
RobsonXT-S3 MEM Interface Size B Date:
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010
Sheet 1
24
of
48
5
4
3
2
(24) M_DA[63..0]
M_MA[13..0]
M_DQS[7..0] M_DQS#[7..0]
L9
NC/ODT1 NC/CS1 NC/CE1 NCZQ1
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
NC NC NC NC
PX@ R375 243_0402_1%
B2 B10 D2 D9 E3 E9 F10 G2 G10
+1.5VGS
+1.5VGS
PX@ 2 56_0402_1%
NC NC NC NC
B2 B10 D2 D9 E3 E9 F10 G2 G10
PX@ 2 56_0402_1% PX@ 2 56_0402_1%
G4 B8
PX@ R376 243_0402_1%
2
R388 2 1 4.99K_0402_1%
1
PX@
PX@
VREFC_A2 1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
DQSL DQSU
RESET ZQ/ZQ0
J2 L2 J10 L10
NC/ODT1 NC/CS1 NC/CE1 NCZQ1
A1 A11 T1 T11
2
1
2
M_CLK1 M_CLK#1 M_CKE1
J8 K8 K10
+1.5VGS
A2 A9 C2 C10 D3 E10 F2 H3 H10
VRAM_ODT1 K2 M_CS#1 L3 M_RAS#1 J4 M_CAS#1 K4 M_WE#1 L4 M_DQS6 M_DQS7
F4 C8
A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10
M_DQM6 M_DQM7
E8 D4
M_DQS#6 M_DQS#7
G4 B8
DRAM_RST# T3 L9
NC NC NC NC
PX@ R377 243_0402_1%
B2 B10 D2 D9 E3 E9 F10 G2 G10
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
J2 L2 J10 L10 A1 A11 T1 T11
100-BALL SDRAM DDR3 64MX16 H5TQ1G63BFR-12C FBGA X76@
D
M_DA57 M_DA58 M_DA60 M_DA61 M_DA63 M_DA62 M_DA56 M_DA59
D8 C4 C9 C3 A8 A3 B9 A4
+1.5VGS
BA0 BA1 BA2
VDD VDD VDD VDD VDD VDD VDD VDD VDD
CK CK CKE/CKE0 ODT/ODT0 CS RAS CAS WE
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DQSL DQSU DML DMU
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
DQSL DQSU
RESET ZQ/ZQ0
B3 D10 G8 K3 K9 N2 N10 R2 R10
+1.5VGS
A2 A9 C2 C10 D3 E10 F2 H3 H10
C
A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10
NC/ODT1 NC/CS1 NC/CE1 NCZQ1
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
NC NC NC NC
B2 B10 D2 D9 E3 E9 F10 G2 G10
100-BALL SDRAM DDR3 64MX16 H5TQ1G63BFR-12C FBGA X76@
+1.5VGS
+1.5VGS
+1.5VGS
+1.5VGS B
PX@
PX@
VREFD_Q2 PX@
PX@
PX@
VREFC_A3 PX@
1
PX@
2
PX@
VREFD_Q3 PX@
PX@
1
2
VREFC_A4 PX@
PX@
1
2
VREFD_Q4 PX@
PX@
1
2
+1.5VGS
1 PX@ C507 0.01U_0402_16V7K
+1.5VGS
10U_0603_6.3V6M 1 C488 PX@
2
C489 PX@
1
10U_0603_6.3V6M 1 1
10U_0603_6.3V6M 1 1
C490 @
C491 PX@
2 10U_0603_6.3V6M
2
C480 PX@
+1.5VGS
1U_0402_6.3V4Z 1 1
C481 PX@
C492 PX@
2 2 2 10U_0603_6.3V6M10U_0603_6.3V6M
2
C482 @
1U_0402_6.3V4Z
M_CLK#0 1 R396
DML DMU
L9
PX@
yb C473
PX@
0.1U_0402_10V6K
PX@
2
M_CLK0 1 R394
E8 D4
+1.5VGS
VREFC_A1
R387 2 1 4.99K_0402_1%
C472
0.1U_0402_10V6K
2
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
PX@
C
M_CLK#1 1 R397
1
NC/ODT1 NC/CS1 NC/CE1 NCZQ1
R380 2 1 4.99K_0402_1%
R379 2 1 4.99K_0402_1%
R378 2 1 4.99K_0402_1% R386 2 1 4.99K_0402_1%
PX@ 2 56_0402_1%
PX@
M_DQM4 M_DQM5
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DQSL DQSU
DRAM_RST# T3
+1.5VGS
PX@
VREFD_Q1 PX@
F4 C8
ODT/ODT0 CS RAS CAS WE
100-BALL SDRAM DDR3 64MX16 H5TQ1G63BFR-12C FBGA X76@
B
PX@
J2 L2 J10 L10
A1 A11 T1 T11
100-BALL SDRAM DDR3 64MX16 H5TQ1G63BFR-12C FBGA X76@
M_DQS4 M_DQS5
M_DQS#4 M_DQS#5
er Fo
A1 A11 T1 T11
M_CLK1 1 R395
ZQ/ZQ0
2
J2 L2 J10 L10
2
PX@ R374 243_0402_1%
RESET
VRAM_ODT1K2 M_CS#1 L3 M_RAS#1 J4 M_CAS#1 K4 M_WE#1 L4
M3 N9 M4
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
M_DA54 M_DA52 M_DA53 M_DA48 M_DA51 M_DA49 M_DA55 M_DA50
E4 F8 F3 F9 H4 H9 G3 H8
C479
DRAM_RST# T3
DQSL DQSU
A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10
(24) VRAM_ODT1 (24) M_CS#1 (24) M_RAS#1 (24) M_CAS#1 (24) M_WE#1
CK CK CKE/CKE0
M_BA0 M_BA1 M_BA2
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3
0.1U_0402_10V6K
G4 B8
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
M_CLK1 J8 M_CLK#1 K8 M_CKE1 K10
B3 D10 G8 K3 K9 N2 N10 R2 R10
VDD VDD VDD VDD VDD VDD VDD VDD VDD
VREFCA VREFDQ
R385 2 1 4.99K_0402_1%
M_DQS#3 M_DQS#1
DML DMU
+1.5VGS
BA0 BA1 BA2
N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8
R393 2 1 4.99K_0402_1%
E8 D4
DQSL DQSU
M3 N9 M4
M_CLK1 M_CLK#1 M_CKE1
(24) (24) (24)
+1.5VGS
A2 A9 C2 C10 D3 E10 F2 H3 H10
1
ZQ/ZQ0
M_DQM3 M_DQM1
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13
C478
RESET
A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10
1
L9
F4 C8
ODT/ODT0 CS RAS CAS WE
M_DA47 M_DA42 M_DA46 M_DA41 M_DA45 M_DA40 M_DA43 M_DA44
M9 H2
0.1U_0402_10V6K
T3
(24) DRAM_RST#
DQSL DQSU
M_DQS3 M_DQS1
CK CK CKE/CKE0
M_BA0 M_BA1 M_BA2
B3 D10 G8 K3 K9 N2 N10 R2 R10
D8 C4 C9 C3 A8 A3 B9 A4
VREFC_A4 VREFD_Q4
R384 2 1 4.99K_0402_1%
G4 B8
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VRAM_ODT0 K2 M_CS#0 L3 M_RAS#0 J4 M_CAS#0 K4 M_WE#0 L4
VDD VDD VDD VDD VDD VDD VDD VDD VDD
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
M_DA35 M_DA34 M_DA36 M_DA37 M_DA32 M_DA38 M_DA33 M_DA39
R392 2 1 4.99K_0402_1%
M_DQS#2 M_DQS#0
DML DMU
A2 A9 C2 C10 D3 E10 F2 H3 H10
+1.5VGS
BA0 BA1 BA2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3
E4 F8 F3 F9 H4 H9 G3 H8
1
E8 D4
J8 K8 K10
N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
2
M_DQM2 M_DQM0
DQSL DQSU
M_CLK0 M_CLK#0 M_CKE0 +1.5VGS
M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13
U21
VREFCA VREFDQ
C477
F4 C8
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
M3 N9 M4
M_DA14 M_DA10 M_DA15 M_DA11 M_DA12 M_DA8 M_DA13 M_DA9
M9 H2
0.1U_0402_10V6K
M_DQS2 M_DQS0
ODT/ODT0 CS RAS CAS WE
M_BA0 M_BA1 M_BA2
D8 C4 C9 C3 A8 A3 B9 A4
VREFC_A3 VREFD_Q3
R383 2 1 4.99K_0402_1%
C
CK CK CKE/CKE0
B3 D10 G8 K3 K9 N2 N10 R2 R10
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
M_DA26 M_DA28 M_DA27 M_DA30 M_DA24 M_DA29 M_DA25 M_DA31
R391 2 1 4.99K_0402_1%
VRAM_ODT0K2 M_CS#0 L3 M_RAS#0 J4 M_CAS#0 K4 M_WE#0 L4
VDD VDD VDD VDD VDD VDD VDD VDD VDD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3
E4 F8 F3 F9 H4 H9 G3 H8
0.1U_0402_10V6K
(24) VRAM_ODT0 (24) M_CS#0 (24) M_RAS#0 (24) M_CAS#0 (24) M_WE#0
+1.5VGS
BA0 BA1 BA2
N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
m .ru
M_CLK0 J8 M_CLK#0 K8 M_CKE0 K10
M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13
U18
VREFCA VREFDQ
C476
M_CLK0 M_CLK#0 M_CKE0
M_DA0 M_DA4 M_DA6 M_DA7 M_DA3 M_DA1 M_DA2 M_DA5
M9 H2
R382 2 1 4.99K_0402_1%
(24) (24) (24)
D8 C4 C9 C3 A8 A3 B9 A4
VREFC_A2 VREFD_Q2
R390 2 1 4.99K_0402_1%
M3 N9 M4
M_BA0 M_BA1 M_BA2
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
M_DA19 M_DA20 M_DA21 M_DA18 M_DA23 M_DA17 M_DA22 M_DA16
1
M_BA0 M_BA1 M_BA2
(24) (24) (24)
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3
E4 F8 F3 F9 H4 H9 G3 H8
2
N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
C475
M_MA0 M_MA1 M_MA2 M_MA3 M_MA4 M_MA5 M_MA6 M_MA7 M_MA8 M_MA9 M_MA10 M_MA11 M_MA12 M_MA13
U20
VREFCA VREFDQ
0.1U_0402_10V6K
D
M9 H2
ru
U19 VREFC_A1 VREFD_Q1
R381 2 1 4.99K_0402_1%
(24) M_DQS#[7..0]
M_DQM[7..0]
R389 2 1 4.99K_0402_1%
(24) M_DQS[7..0]
C474
(24) M_DQM[7..0]
0.1U_0402_10V6K
(24) M_MA[13..0]
A
1
M_DA[63..0]
2
C483 PX@
1U_0402_6.3V4Z 1 1
2
C493 PX@
1U_0402_6.3V4Z
2
C494 @
1U_0402_6.3V4Z 1 1
2
C495 PX@
1U_0402_6.3V4Z
2
C496 PX@
1U_0402_6.3V4Z 1 1
2
C497 PX@
1U_0402_6.3V4Z
2
C498 @
1U_0402_6.3V4Z 1 1
2
C499 PX@
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z 1 1 C500 PX@
2
C501 PX@
1U_0402_6.3V4Z
2
C484 @
1U_0402_6.3V4Z 1 1
2
C485 PX@
1U_0402_6.3V4Z
2
C486 PX@
1U_0402_6.3V4Z 1 1
2
C502 PX@
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z 1 1
C503 PX@
2
C504 PX@
1U_0402_6.3V4Z
2
C505 PX@
1U_0402_6.3V4Z 1 1
2
C487 PX@
2
1U_0402_6.3V4Z
A
1 PX@ C506 0.01U_0402_16V7K 2
VRAM P/N : Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! ) update VRAM PN
Issued Date
0619 update
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! )
2010/06/30
Deciphered Date
2012/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
RobsonXT-S3 VRAM Size C Date:
5
4
3
2
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010 1
Sheet
25
of
48
5
4
3
2
1
+1.7_VDDCT +1.7_LX
2
Atheros request can't disable LAN power
1
2
@
1
2
Close to Pin40
Pin
+1.7_LX 2 4.7UH_SIA4012-4R7M_20%
1 L56
1000P_0402_50V7K
@
JUMP_43X79
D
1
C786
2
2
C785
1
C784
1
10U_0805_10V4Z
+1.7_VDDCT
Description
Chip Default
H:Over Clock Enable
LED0
L:Over Clock Disable
Note: Place Close to LAN chip L56 DCR< 0.15 ohm Rate current of L33 > 1A
H
*
H:SWR Switch mode regulator Select LED2
*
AR8151 Pin23=LED2.
D
--
no overclocking PD 5.1K R650 5.1K_0402_5% 1 2
LED0,1,2 intel Pull UP
RX_N
(13) PCIE_FTX_C_DRX_P0
35
RX_P
(13) CLK_PCIE_LAN# (13) CLK_PCIE_LAN
32 33
REFCLK_N REFCLK_P
LAN_XTALO LAN_XTALI R657 1 GIGA@ 2 0_0402_5%
(14) LAN_CLKREQ#
CLKREQ_LAN#_R 0.1U_0402_16V4Z 1 2 C796 8152@
+1.1_AVDDL +1.1_AVDDL
C806 0.1U_0402_16V4Z
7 8
10
LAN_RBIAS
LX
XTLO XTLI
VDDCT
4
CLKREQ# AVDDL AVDDL AVDDL AVDDL AVDDL_REG
1
40 5
+1.7_VDDCT
+1.7_VDDCT
DVDDL DVDDL_REG
24 37
+1.1_DVDDL C797 1 C798 1 C800 1
AVDDH AVDDH AVDDH_REG
16 22 9
+2.7_AVDDH +2.7_AVDDH
GND
AR8151-AL1A_QFN40_5X5 GIGA@
2
LAN_XTALI
LAN_XTALO
Near Pin6
Y6
1
2 2.37K_0402_1%
2
2
1
2
Near Pin9
2 0.1U_0402_16V4Z 2 1U_0402_6.3V4Z 2 0.1U_0402_16V4Z
Near
1
2
Near Pin22
1
2
C
LAN_CLKREQ#
(27) (27) (27) (27) (27) (27) (27) (27)
C791 & C792 Close pin1 < 200mil C794 & 795 Close pin < 400mil
+1.7_LX
+1.7_LX
1
41
1 R654
+3V_LAN
VDD33
1
+3V_LAN
1
2
1
2
@
1
2
1
2
C799 0.1U_0402_16V4Z B
Pin37
1
2
Place Close to LAN chip
Near Pin16
MDI0+
R658 1
MDI0-
R659 1
MDI1+
R660 1
MDI1-
R661 1
MDI2+
R662 1 GIGA@ R663 1 GIGA@ R664 1 GIGA@ R665 1 GIGA@
25MHZ_20PF_7A25000012
1
2
C
A
RBIAS
yb
2
TEST_RST TESTMODE
27P_0402_50V8J
Near Near Near Near Pin13 Pin19 Pin31 Pin34
C805
2
1
1U_0402_6.3V4Z
C804
2
1
0.1U_0402_16V4Z
C803
2
1
0.1U_0402_16V4Z
GIGA@
1
28 27
13 19 31 34 6
+1.1_AVDDL
0.1U_0402_16V4Z
2
C802
GIGA@ C801
1
0.1U_0402_16V4Z
B
SMCLK SMDATA
C807
@ LAN_CLKREQ# 1 R926 2 10K_0402_5%
W AKE#
25 26
C808
+3VALW
PERST#
3
MDI0MDI0+ MDI1MDI1+ MDI2MDI2+ MDI3MDI3+
0.1U_0402_16V4Z
(31) LAN_WAKE#
2
MDI0MDI0+ MDI1MDI1+ MDI2MDI2+ MDI3MDI3+
er Fo
PCIE_WAKE#
12 11 15 14 18 17 21 20
R651 1 8152@ 2 0_0402_5%
1
2
27P_0402_50V8J
2 0_0402_5%
C816
@
C815
R652 1
TRXN0 TRXP0 TRXN1 TRXP1 TRXN2 TRXP2 TRXN3 TRXP3
ACTIVITY (27) LAN_LINK# (27)
1U_0402_6.3V4Z
PLT_RST#
(13,30,31) PLT_RST# (14,30) FCH_PCIE_WAKE#
8151-AL1A
38 39 23
C794
36
LED_0 LED_1 LED_2
1U_0402_6.3V4Z
(13) PCIE_FTX_C_DRX_N0
Atheros
C792
TX_P
C810 GIGA@
TX_N
2 0.1U_0402_16V7K PCIE_FRX_DTX_P0_C 30
0.1U_0402_16V4Z
2 0.1U_0402_16V7K PCIE_FRX_DTX_N0_C 29
C7901
C809
C7891
(13) PCIE_FRX_DTX_P0
0.1U_0402_16V4Z
(13) PCIE_FRX_DTX_N0
C
ru
U29
0.1U_0402_16V4Z
S IC AR8152-AL1E QFN 40P E-LAN CTRL
Place Close to Chip
10U_0805_10V4Z C795
8152@
C791
U29
m .ru
AR8152, Pin23 is CLKREQ
10U_0805_10V4Z
+3V_LAN J6
0.1U_0402_16V4Z
+3VALW
Power On strapping
MDI2MDI3+ MDI3-
49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2 49.9_0402_1% 2
@ C811 1000P_0402_50V7K
1
2 C812 0.1U_0402_16V4Z
1
2 C814 0.1U_0402_16V4Z
1
2 C818 0.1U_0402_16V4Z GIGA@ @ C819 1000P_0402_50V7K
1
2 C820 0.1U_0402_16V4Z GIGA@
@ C813 1000P_0402_50V7K
@ C817 1000P_0402_50V7K
A
8152 no mount MDI3+,MDI3-,MDI2-,MDI2+ resister and cap Configure
Configure Pin4 AR8152
VDDCT_REG
AR8151
CLKREQn
R657
C796
* * 5
Pin23 CLKREQn
R651
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
*
2010/06/30
2012/06/30
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LED[2] 4
3
2
Title
LAN-AR8151/8152 Size Document Number Custom Date:
Rev 1.0
LA6755P/7P
Tuesday, November 30, 2010
Sheet 1
26
of
48
5
4
3
2
1
R916 +1.7_VDDCT
2
1 0_0603_5% @ C996 1U_0402_6.3V4Z
1
2
Place Close to T88 D
D
T88
MDI1+ D1 @
(26) (26)
MDI1+ MDI1-
(26) (26)
MDI0+ MDI0-
MDI1+ MDI1-
1 2 3 4 5 6 7 8
MDI0+ MDI0-
RX+ RXCT NC NC CT TX+ TX-
GND
5 4 3 2 1
T97 MDI0-
(26) (26)
MDI2+ MDI2-
(26) (26)
MDI3+ MDI3-
MDI2+ MDI2-
1 2 3 4 5 6 7 8
MDI0+
Reserve D1 for EMI go rural solution 20101006
C
MDI3+ MDI3-
GIGA@
RD+ RDCT NC NC CT TD+ TD-
MDO1+ MDO1MCT0
16 15 14 13 12 11 10 9
MCT1 MDO0+ MDO0@ C1013 22U_1206_10V7K
350uH_NS0013LF
5 4 3 2 1
11
6 7 8 9 10
6 7 8 9 10
TCLAMP3302N.TCT_SLP2626P10-10
RD+ RDCT NC NC CT TD+ TD-
1
1
R666
2
1 75_0402_5%
R667
2
1 75_0402_5%
@ C1012 22U_1206_10V7K
m .ru
MDI1-
RX+ RXCT NC NC CT TX+ TX-
16 15 14 13 12 11 10 9
2
2
MDO2+ MDO2MCT2
Reserve gas tube for EMI go rural solution 20101006
R668 2 GIGA@ 1 75_0402_5%
MCT3 MDO3+ MDO3-
R669 2 GIGA@ 1 75_0402_5% C822
1
C
2
ru 2
C993
2
C992
C991
C990
2
1000P_1206_2KV7K
1
0.1U_0402_16V4Z
GIGA@
GIGA@
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
er Fo
1
0.1U_0402_16V4Z
350uH_NS0013LF
2
RJ45 Conn.
Place close to TCT pin
LAN_LINK#
R671
@ C994 470P_0402_50V7K
1 220_0402_5%
2
1
C
LAN_LINK_LED#_R
+3V_LAN
2
yb
B
JRJ1 (26)
12
Green LED-
11
Green LED+
MDO3-
8
MDO3+
7
PR4+
MDO1-
6
PR2-
MDO2-
5
PR3-
MDO2+
4
PR3+
MDO1+
3
PR2+
MDO0-
2
PR1-
MDO0+
1
PR1+
10 (26)
R670
ACTIVITY
@ C995 470P_0402_50V7K
1 220_0402_5%
2
ACTIVITY_R
9
SHLD2
16
SHLD1
15
SHLD2
14
SHLD1
13
PR4-
B
Yellow LEDYellow LED+ LIYO_101007-08203-033 ME@
1
2
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2010/06/30
Issued Date
Deciphered Date
2012/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
LAN_Transformer Size Document Number Custom Date:
Rev 1.0
LA6755P/7P
Tuesday, November 30, 2010
Sheet 1
27
of
48
5
4
3
2
1
CX20671 High Definition Audio Codec SoC With Integrated Class-D Stereo Amplifier. An integrated 5 V to 3.3 V Low-dropout voltage regulator (LDO). An integrated 3.3 V to 1.8V Low-dropout voltage regulator (LDO).
HDA_RST_AUDIO#
EMI
HDA_SYNC_AUDIO HDA_SDOUT_AUDIO 1 R672 2 0_0402_5%
2
@
HDA_BITCLK_AUDIO
1 22P_0402_50V8J C826
2
@
1 22P_0402_50V8J C825
D
1 22P_0402_50V8J C824
22P_0402_50V8J C823
1
2
@
2 D
Cheange to pop for PVT for EMI solution 20101006
+LDO_OUT_3.3V_R
2
1
2
+LDO_OUT_3.3V
AVDD_3.3 pinis output of internal LDO. NOT connect to external supply.
Layout Note:Path from +5VS to LPW R_5.0 RPW R_5.0 must be very low resistance ( White Right --> Orange
1
2
2 470_0402_5%
1
White
2 300_0402_5%
1 R764
+5VALW
19-213A-T1D-CP2Q2HY-3T_W HITE @
1
1
B
LED3
2
White
RB751V_SOD323 @ D18 (33) BT_LED#
2
BATT_CHG_LED# D17
(30) W LAN_LED#
+3VALW
Change design to two LED 20101005
LED5 (31) CHARGE_LED0#
1 R765
HT-191UD5_AMBER
1
2
2 300_0402_5%
1 R766
+5VS
2 300_0402_5%
1 R767
+5VS
19-213A-T1D-CP2Q2HY-3T_W HITE
2
RB751V_SOD323
(31) RF_LED#
R874 1
2 0_0402_5%
LED4
White (15) HDD_LED#
GND GND
1
2
19-213A-T1D-CP2Q2HY-3T_W HITE
15 14
S
A
+3VS
Compal Secret Data
Security Classification 2010/06/30
Issued Date
Deciphered Date
2012/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
D
2
ALLTO_C18518-11305-L ME@
3
D
1
(14) ODD_DA#_FCH
3
OUTPUT
2 G
A
LA6755P
1 2 3 4 5 6 7
R881 1
+3VS
S-5711ACDL-M3T1S_SOT23-3
2 R757
(31) KILL_SW #_EC
JODD1
SATA ODD Conn. (15) SATA_DTX_C_IRX_N1 (15) SATA_DTX_C_IRX_P1
2 100K_0402_5%
Kill Switch
yb
1
R756 1
+3VALW
(31,34) PW R_LED#
2
SMT1-05_4P
2
GND GND
JTP1
2
B
8 7
PACDN042Y3R_SOT23-3
2
TP_CLK TP_DATA SW /L SW /R
@ C935 100P_0402_50V8J
3
6 5
2
1
@ C934 100P_0402_50V8J
1
er Fo
0.1U_0402_16V4Z
1
+VCC_LID
2 0_0402_5%
C931 0.1U_0402_16V4Z
ru
ME@ ACES_88058-060N
C933
TP_CLK TP_DATA
1 R755
+3VALW
Kill
+5VS
(31) (31)
Lid Switch
GND2 GND1
2
KSO[0..15]
ME@ ACES_88514-2401
(31)
1
KSI[0..7]
m .ru
KSI[0..7]
1
VDD
4
GND
5
4
3
2
Title
Compal Electronics, Inc. 14" ONLY
Size B Date:
Document Number
Rev 1.0
LA6755P/7P Tuesday, November 30, 2010
Sheet 1
46
of
48
5
4
3
2
1
ZZZ
ZZZ1
ZZZ2
ZZZ3
ZZZ4
ZZZ5
PCB
LA6757P
CR2032_0
CR2032_0
CR2032_0
CR2032_0
JKB1
KSI[0..7] KSO[0..17]
KSO17
C1000 1
2 @ 100P_0402_50V8J
KSO16
C1001 1
2 @ 100P_0402_50V8J
KSO1
C906 1
2 @ 100P_0402_50V8J
KSO7
C908 1
2 @ 100P_0402_50V8J
D
KSO2
C905 1
2 @ 100P_0402_50V8J
KSO15 KSO6
C909 1
2 @ 100P_0402_50V8J
KSI2
C910 1
2 @ 100P_0402_50V8J
KSO8
C911 1
2 @ 100P_0402_50V8J
KSO5
C912 1
2 @ 100P_0402_50V8J
KSO13
C913 1
2 @ 100P_0402_50V8J
KSI3
C914 1
2 @ 100P_0402_50V8J
KSO12
C915 1
2 @ 100P_0402_50V8J
KSO14
C916 1
2 @ 100P_0402_50V8J
KSO11
C917 1
2 @ 100P_0402_50V8J
KSI7
KSO10
C919 1
2 @ 100P_0402_50V8J
KSI6
C920 1
2 @ 100P_0402_50V8J
KSI5
C922 1
2 @ 100P_0402_50V8J
C926 1
2 @ 100P_0402_50V8J
KSO3 KSO4
C923 1
2 @ 100P_0402_50V8J
KSI4
KSI0
C925 1
2 @ 100P_0402_50V8J
KSO9
KSO0
KSI1
C928 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
D
m .ru
KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15 KSO16 KSO17
GND GND
31 32
ACES_88514-3001 ME@
2 @ 100P_0402_50V8J
C
D17
1
RF_LED#_R
2
ru
@
C
RB751V_SOD323 D18
@
1
R937 1
2
RB751V_SOD323 C933
SMT1-05_4P
2
4
1
3
2
KILL_SW #_R
1 R939 1 @ R940
1 R706
SMT1-05_4P
2 0_0402_5% 2 0_0402_5%
B
C875 1 2 0.01U_0402_16V7K C876 1 2 0.01U_0402_16V7K R881 1 2 0_0402_5% R809 1 @ 2 ODD_DETECT#_R 0_0402_5%
C 6 5
6 5
1
@
GND GND ACES_88058-060N ME@
yb
D26
1 2 3 4 5 6
er Fo
7 8
B
2 0_0402_5%
SATA_DTX_IRX_N1 SATA_DTX_IRX_P1
ODD_DA#_R
@ Q118 2N7002_SOT23
4
SW /R
1
3
S
3 SW 4
2 G
SW 3
1
D
SW /L
1 2 3 4 5 6
TP_CLK TP_DATA SW /L SW /R
2
2
@ C935 100P_0402_50V8J
JTP1
PACDN042Y3R_SOT23-3
1
3
2
@ C934 100P_0402_50V8J
RF_LED#_R
1 2 R874 0_0402_5%
0.1U_0402_16V4Z
1
2 100K_0402_5%
LID_SW #
A
A
Compal Secret Data
Security Classification 2010/06/30
Issued Date
Deciphered Date
2012/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. 15" ONLY
Size B Date:
Document Number
Rev 1.0
LA6757P Tuesday, November 30, 2010
Sheet 1
46
of
48
5
4
3
2
PHASE
PAGE
Modification list
PURPOSE
0.2
P08
C643 change to OS-CON type
For cost down purpose
0.2
P10
pop R490, unpop R491
LVDS PWM controls by EC
0.2
P10
Add CE_EN @ JLVDS1.16 and U33.98
For color engine function
0.2
P10
R488 pull-up to +5VALW
For C38 module design
0.2
P10
Add R938
For CMOS cost down purpose
0.2
P12
JCRT1 change foot-print from DC060003O00 to DC060004S00
Foot-print is wrong
0.2
P14
SATA_DET# change from U26.AE19 to U26.AB21
For corresponding SATA port assigned
0.2
P16
Delete R635
Our codec consumes +3V
0.2
P18
Add R936
For VGA_PWRGD reservation
0.2
P20
Q69 ~ Q72 change to N-MOS
Follow BACO suggestion SCH
0.2
P21
R840 pull-up change to +5VALW and R857 change to 20K ohms
For +3VGS sequence design
0.2
P21
Delete Q122, Add U47, C999, R944
For +1.0VGS DC power design
0.2
P23
L27 change to 0 ohms
For new reference circuit
0.2
P23
Delete GND connection of U8.N11 and U8.N12
For new reference circuit
0.2
P21
R344 change to 20K ohms
Prevent Q74 damage
0.2
P28
J7 foot-print update
Base on DFX request
0.2
P28
Add net CLK_PCI_DB_R and unpop R854
for EMI concern
0.2
P28
Modify PC_Beep circuit
Base on vender suggestion
0.2
P23
Delete C421, C422, C431, C432, C433
For new reference circuit
0.2
P31
R734 pull-high change to +5VALW
For USB ports ACIN leakage
0.2
P31
Add BATT_SEL_EC at U33.103
For Battery selection reservation
0.2
P33
Add R941
For further cost down purpose
0.2
P33
Add R942, R943, C998
For SATA_DET# function design
0.2
P28
Delete C851, C855
0.2
P34
Change JP7 to JPWRB1 and JP8 to JCR1
0.2
P34
Del U45, R890 ~ R899, J12, CHR_ON# (U33.70)
0.2
P35
Delete C974
0.2
P19
Add R945, R946
0.2
P13
Delete T79, T80
0.2
P28
Add R947, R948
0.2
P28
Delete C857, R694
0.2
P28
L57 ~ L60 change to 0_0603_5%
0.2
P28
R672 change to 0ohm and location to be series on HDA_BITCLK_AUDIO
For EMI solution reservation base on vender suggetion
0.2
P14
Kill_SW# change from U26.G24 to U26.K1
Kill_SW# function needs event pin
0.2
P31
Add R949, C1002
0.2
P28
Add R950 @ +3VS, R951 @ +LDO_OUT_3.3V, R952 @ +5VS
1
A
P28
Add R953
0.2
P29
Add R954, R955
0.2
P13 P18
Add C1003, U48, R956, R957 Delete R556, R841, R889, D28
0.2
P05
Add R958
0.2
P28
Add R959
0.2
P32
Add R960 and c1004
0.2
P09
Add R961 and R962
0.2
P05
Delete T74, T75
0.3
P29 P46
change +5V_ODD to +5VS_ODD
ru
Deleting USB charge function Deleting unnecessary part for +1.1VS
er Fo
0.2
For standard naming
For HDMI Audio strap For layout space needed for SATA calibration
For EMI solution reservation base on vender suggetion To delete redundant part base on vender suggestion Base on vender suggestion
Requirement of implementing SUSCLK For PC Beep circuit
For customer request (PWR consumption) For PX GPU_RST# function For enabling HDMI function For EMI reservation For EMI reservation For DDR SO-DIMMB strap pin reservation For layout limitation For better net name
0.3
P32
R760 change to 100ohm bead and R761 change back to 15ohm resistor
0.3
P21
U47 change to SB00000GV00 footprint
For correct symbol
0.3
P05
R958 change to HDMI@ and R422 change to nonHDMI@
For SKU without HDMI function
0.3
P21
Add PX_MODE off page
For design correction
For correct EMI solution
2010/06/30
Issued Date
5
A
Compal Secret Data
Security Classification
Change footprint 20100812
B
For customer request (PWR consumption)
yb
B
C
For useless AGND bridge
C
C
D
m .ru
D
Deciphered Date
2012/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
: For cost down purpose to change parts 4
3
2
Title
Compal Electronics, Inc. HW-PIR1
Size B Date:
Document Number
Rev 1.0
LA-6755P Tuesday, November 30, 2010
Sheet 1
47
of
48
5
4
3
2
PHASE
PAGE
Modification list
PURPOSE
0.2
P08
C643 change to OS-CON type
For cost down purpose
0.2
P10
pop R490, unpop R491
LVDS PWM controls by EC
0.2
P10
Add CE_EN @ JLVDS1.16 and U33.98
For color engine function
0.2
P10
R488 pull-up to +5VALW
For C38 module design
0.2
P10
Add R938
For CMOS cost down purpose
0.2
P12
JCRT1 change foot-print from DC060003O00 to DC060004S00
Foot-print is wrong
0.2
P14
SATA_DET# change from U26.AE19 to U26.AB21
For corresponding SATA port assigned
0.2
P16
Delete R635
Our codec consumes +3V
0.2
P18
Add R936
For VGA_PWRGD reservation
0.2
P20
Q69 ~ Q72 change to N-MOS
Follow BACO suggestion SCH
0.2
P21
R840 pull-up change to +5VALW and R857 change to 20K ohms
For +3VGS sequence design
0.2
P21
Delete Q122, Add U47, C999, R944
For +1.0VGS DC power design
0.2
P23
L27 change to 0 ohms
For new reference circuit
0.2
P23
Delete GND connection of U8.N11 and U8.N12
For new reference circuit
0.2
P21
R344 change to 20K ohms
Prevent Q74 damage
0.2
P28
J7 foot-print update
Base on DFX request
0.2
P28
Add net CLK_PCI_DB_R and unpop R854
for EMI concern
0.2
P28
Modify PC_Beep circuit
Base on vender suggestion
0.2
P23
Delete C421, C422, C431, C432, C433
For new reference circuit
0.2
P31
R734 pull-high change to +5VALW
For USB ports ACIN leakage
0.2
P31
Add BATT_SEL_EC at U33.103
For Battery selection reservation
0.2
P33
Add R941
For further cost down purpose
0.2
P33
Add R942, R943, C998
For SATA_DET# function design
0.2
P28
Delete C851, C855
0.2
P34
Change JP7 to JPWRB1 and JP8 to JCR1
0.2
P34
Del U45, R890 ~ R899, J12, CHR_ON# (U33.70)
0.2
P35
Delete C974
0.2
P19
Add R945, R946
0.2
P13
Delete T79, T80
0.2
P28
Add R947, R948
0.2
P28
Delete C857, R694
0.2
P28
L57 ~ L60 change to 0_0603_5%
0.2
P28
R672 change to 0ohm and location to be series on HDA_BITCLK_AUDIO
For EMI solution reservation base on vender suggetion
0.2
P14
Kill_SW# change from U26.G24 to U26.K1
Kill_SW# function needs event pin
1
A
ru For standard naming
Deleting USB charge function For HDMI Audio strap For layout space needed for SATA calibration
For EMI solution reservation base on vender suggetion To delete redundant part base on vender suggestion Base on vender suggestion
0.2
P31
Add R949, C1002
0.2
P28
Add R950 @ +3VS, R951 @ +LDO_OUT_3.3V, R952 @ +5VS
0.2
P28
Add R953
0.2
P29
Add R954, R955
0.2
P13 P18
Add C1003, U48, R956, R957 Delete R556, R841, R889, D28
0.2
P05
Add R958
0.2
P28
Add R959
0.2
P32
Add R960 and c1004
0.2
P09
Add R961 and R962
0.2
P05
Delete T74, T75
er Fo
Deleting unnecessary part for +1.1VS
Requirement of implementing SUSCLK
B
For customer request (PWR consumption) For PC Beep circuit For customer request (PWR consumption)
yb
B
C
For useless AGND bridge
For PX GPU_RST# function For enabling HDMI function For EMI reservation For EMI reservation
C
C
D
m .ru
D
For DDR SO-DIMMB strap pin reservation For layout limitation
15 only part 0.2
P46
A
Add C1000, C1001
For 15" 30pin KB connector
Compal Secret Data
Security Classification 2010/06/30
Issued Date
Change footprint 20100812
2012/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
: For cost down purpose to change parts 5
Deciphered Date
4
3
2
Title
Compal Electronics, Inc. HW-PIR
Size B Date:
Document Number
Rev 1.0
LA6757P Tuesday, November 30, 2010
Sheet 1
47
of
48
5
4
3
Modification list
2
PHASE
PAGE
0.3
P14
R603 and R604 change to pop
For SM Bus pull-high
0.3
P23
Reserve C1005
For PWR team request reserving a 330u capcitor
1
PURPOSE
0.3
P33
C939 change to 5.9H OS-con
For cost saving
0.3
P33
R902 and R942 change to unpop
For eSATA function deletion
0.3
P29
U32 change PN to SA000046C00
For main source PN concern
0.3
P05
Delete JHDT1
For layout limitation
0.3
P11
Add F2 and change SM-BUS pull high net name to +5VS_HDMI_F
For safety team requirement
0.3
P21
change J3 footprint
For larger jumper footprint
D
P21
R856 change from 20K to 39K
For VGA power sequence
0.3
P11
Add net name +5VS_HDMI_F
For power trace indecation
0.3
P20
Change Q69 ~ Q72 PN
For design correction
0.3
P28
Add R963
For 20671-21Z update
0.3
P28
Change U31 PN to SA00003K410
For 20671-21Z PN
0.3
P20
U10.5, U46.5, and U44.5 change from +3VS to +3VGS
For BACO circuit update
0.3
P28
Delete R951
For unnecessary part deletion
0.3
P07
C623 change to unpop
Base on AMD checklist
0.3
P16
Delete C734, add C1006, C1007
For ME concern
0.3
P21
R924 cahgne pull-up from +3VS to +3VALW
For BACO design correction
0.3
P21
R925 change to pop
For BACO design correction
0.3
P14
Reserve C1008 at FCH_PWRGD
For EMI request
0.3
P14
Reserve C1009 at VGATE
For EMI request
0.3
P31
Reserve C1010 at VR_ON
For EMI request For EMI request
P13
Reserve C1011 at H_PWRGD_L
0.3
P28
pop C849, C850, R692, R693, R696, C826
0.3
P27
Add C1012, C1013
0.3
P27
Add D1
0.3
P28
update R672 location
0.3
P07
Delete C617
0.3
P28
Pop D30, D31, unpop R953
0.3
P31
R751 and R752 change from 4.7K ohm to 2.2K ohm
0.3
P13
C719, C720 change from 22P to 18P
C
ru
0.3
For EMI request
For EMI request (gas discharge tube)
For EMI request (ESD diode) For EMI request (RC to GND for codec BIT_CLK) For EMI solution space needed For FCH PC-beep function For PWR team request For RTC design
14" only part 0.3
P46
Change one dual-diode LED2 to two single diode LED2 and LED5
For design change
1.0
P5
unpop R415
AMD checklist update
1.0
P10
R486, R487 change pull-high to +5VS
1.0
P11
R522, R523 change from 2.2K to 2K
1.0
P12
reserve R964, R965, change R546 ~ R549 from 4.7K to 2K
1.0
P31
BATT_LEN# added to U33.38
1.0
P20
Delete R341
1.0
P21
Delete R837, R832, R836
1.0
P28
Delete R947, R948, R950, R952
1.0
P29
Delete R955, R954, R810
1.0
P30
unpop C887, C888
1.0
P25
unpop C494, C484, C498, C482, C490
B
AMD checklist update AMD checklist update
yb
AMD checklist update PWR team request For design update For design update For design update For design update
C
B
m .ru
0.3
er Fo
C
D
For design update For design update
A
A
Compal Secret Data
Security Classification 2010/06/30
Issued Date
Change footprint 20100812 5
Deciphered Date
2012/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
: For cost down purpose to change parts 4
3
2
Title
Compal Electronics, Inc. HW-PIR2
Size B Date:
Document Number
Rev 1.0
LA-6755P Tuesday, November 30, 2010
Sheet 1
48
of
48
5
A
PAGE
Modification list
PURPOSE
0.3
change +5V_ODD to +5VS_ODD
For better net name
0.3
P29 P46 P32
R760 change to 100ohm bead and R761 change back to 15ohm resistor
For correct EMI solution
0.3
P21
U47 change to SB00000GV00 footprint
For correct symbol
0.3
P05
R958 change to HDMI@ and R422 change to nonHDMI@
For SKU without HDMI function
0.3
P21
Add PX_MODE off page
For design correction
0.3
P14
R603 and R604 change to pop
For SM Bus pull-high
0.3
P23
Reserve C1005
For PWR team request reserving a 330u capcitor
P33
C939 change to 5.9H OS-con
For cost saving
P33
R902 and R942 change to unpop
For eSATA function deletion
0.3
P29
U32 change PN to SA000046C00
For main source PN concern
0.3
P05
Delete JHDT1
For layout limitation
0.3
P11
Add F2 and change SM-BUS pull high net name to +5VS_HDMI_F
For safety team requirement
0.3
P21
change J3 footprint
For larger jumper footprint
0.3
P21
R856 change from 20K to 39K
For VGA power sequence
0.3
P11
Add net name +5VS_HDMI_F
For power trace indecation
0.3
P20
Change Q69 ~ Q72 PN
For design correction
0.3
P28
Add R963
For 20671-21Z update
0.3
P28
Change U31 PN to SA00003K410
For 20671-21Z PN
0.3
P20
U10.5, U46.5, and U44.5 change from +3VS to +3VGS
For BACO circuit update
0.3
P28
Delete R951
For unnecessary part deletion
0.3
P07
C623 change to unpop
Base on AMD checklist For ME concern
P16
Delete C734, add C1006, C1007
P21
R924 cahgne pull-up from +3VS to +3VALW
0.3
P21
R925 change to pop
0.3
P14
Reserve C1008 at FCH_PWRGD
0.3
P14
Reserve C1009 at VGATE
0.3
P31
Reserve C1010 at VR_ON
0.3
P13
Reserve C1011 at H_PWRGD_L
0.3
P28
pop C849, C850, R692, R693, R696, C826
0.3
P27
Add C1012, C1013
0.3
P27
Add D1
0.3
P28
update R672 location
0.3
P07
Delete C617
0.3
P28
Pop D30, D31, unpop R953
0.3
P31
R751 and R752 change from 4.7K ohm to 2.2K ohm
0.3
P13
C719, C720 change from 22P to 18P
For BACO design correction For BACO design correction
For EMI request For EMI request For EMI request For EMI request For EMI request
For EMI request (gas discharge tube)
For EMI request (ESD diode) For EMI request (RC to GND for codec BIT_CLK) For EMI solution space needed For FCH PC-beep function
1.0
P5
unpop R415
P10
R486, R487 change pull-high to +5VS
1.0
P11
R522, R523 change from 2.2K to 2K
1.0
P12
Add R964, R965, change R548, R549 from 4.7K to 2K unpop R546, R547, Q89
AMD checklist update AMD checklist update AMD checklist update AMD checklist update
1.0
P31
BATT_LEN# added to U33.38
1.0
P46
Kill_SW#_R change from JLED1.5 to JLED1.12
Design change update
PWR team request For design update
1.0
P20
Delete R341
1.0
P21
Delete R837, R832, R836
1.0
P28
Delete R947, R948, R950, R952
1.0
P29
Delete R955, R954, R810
1.0
P30
unpop C887, C888
For design update
1.0
P25
unpop C494, C484, C498, C482, C490
For design update
For design update For design update For design update
A
Compal Secret Data
Security Classification 2010/06/30
Issued Date
5
B
For PWR team request For RTC design
1.0
Change footprint 20100812
C
ru
0.3 0.3
D
m .ru
0.3 0.3
1
er Fo
B
2
PHASE
yb
C
3
C
D
4
Deciphered Date
2012/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
: For cost down purpose to change parts 4
3
2
Title
Compal Electronics, Inc. HW-PIR2
Size B Date:
Document Number
Rev 1.0
LA6757P Tuesday, November 30, 2010
Sheet 1
48
of
48
