Lenovo Ideapad 3-14ITL6 - 15ITL6 - 17ITL6 LCFC HS460 - HS560 - HS760 NM-D471 - NM-D472 - NM-D473 Rev 0.1 [PDF]

Citation preview

A



B



C



D



E



1



1



LCFC NM-D471/NM-D472/NM-D473 HS460&HS560&HS760 MB Schematics Document



2



2



Tiger Lake UP3 with DDR4 + Slot-DIMM



2020-06 REV:0.1 3



4



3



14'-



NM-D471



15'-



NM-D472



17'-



NM-D473



4



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: A



B



C



D



Document Number



Rev 0.1



Cover Page Tuesday, November 10, 2020 E



Sheet



1



of



110



A



B



C



D



NV N18S: U_GPU_GB2E_64 Package: FCBGA595 NV N17S: U_GPU_GB2D_64 Package: FCBGA595 1



PCI-Express 4x Gen3



VRAM: 256*32 GDDR5*2: 2GB



Memory Bus (Channel A)



DDR4 SLOT-DIMM



Memory Bus (Channel B)



DDR4 Memory Down



USB3.0x1 USB2.0x1



USB3.0 Conn



USB2.0x1



Repeater for HDMI reserve



Finger Printer



eDP x2



eDP Conn



USB2.0x1 SATA x1



Redriver for 17''



NGFF SSD



PCI-Express 4x Gen3



USB3.0x1 USB2.0x1



BGA-1499 45.5mm*25mm



WLAN&BT



Type-C Conn USB3.1 Gen1



USB2.0x1 USB2.0x2



PCI-Express (option for V14V15)



SPK Conn. Realtek ALC3287



Type-C MUX RTS5448



C O N N



USB2.0x1



C O N N



USB2.0 PORT



HALL Sensor



HD Audio



PWR BUTTON/Novo button PWR LED Finger printer diaplay LED



PCI-Express GPU(4X)



V14V15 IO BOARD



RPMC ROM (8MB)



PCI-Express



W25R64JVSSIQ_SO8



Touch Pad



2



Card Reader



HP&Mic Combo Conn.



3



S360 IO BOARD



CONNECTOR (24P for S360,36P for V14V15)



PCIe x1 PCIe x1 Gen2 USB2.0 x1 CNVi



NGFF



Camera



Intel MCP



1x Gen3



Tiger Lake UP3 15W 2



1



HDMI (DDI 1)



HDMI Conn.



SATA HDD



E



LAN RJ45 3



I2C



USB2.0 PORT



SPI ROM (16MB) W25Q128JVSIQ_SO8 I2C



HALL Sensor



Touch Screen SPI(Mirror Code)



PWR BUTTON/Novo button PWR LED Finger printer diaplay LED



ESPI



EC



GPIO



IT8227VG-128-CX_VFBGA128



Int.KBD Thermal Sensor



Option



F75303M



KB Backlight CONN 4



4



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: A



B



C



D



Document Number



Rev



Block Diagram_EE Tuesday, November 10, 2020 E



Sheet



2



of



0.1 110



5



4



3



2



1



+5VS



V20B+



Richtek +5VALW/8A



LV5083AGQUF



Adaptor 65W D



D



+1.05VGS/2.1A



Converter



+3VS



FOR SYSTEM



+1.0VALW/6A +3VALW/ 6A



EN



PGOOD



+1.8VALW/1A



C



TI BQ24780SRUYR Battery Charger Switch Mode



EN



Silergy LV5116AGQW SYS PMIC



+1.35V/8A



Richtek LV5095B Switch Mode



+2.5V/1A



C



FOR VRAM



+0.6VS/2A



UPI UP1666QQKF



SMBus EN



Switch Mode FOR GPU VDDC



Battery polymer 3S1P/2S2P EN



+1.2V/6A



PGOOD



+VGA_CORE/30A PGOOD



Richtek RT3602ACGQW Switch Mode FOR CPU Core



IA Core/42A VCCGT/18A VCCSA/4A



PGOOD



B



B



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



Block Diagram_PWR Tuesday, November 10, 2020 1



Sheet



3



of



110



A



B



Voltage Rails ( O --> Means ON



C



D



, X --> Means OFF ) SIGNAL



STATE



Power Plane



+3VALW +5VALW +3VALW_PCH +1.8VALW +1.05VALW



V20B+



1



+5VS



+1.2V



+3VS +VCCIO



+2.5V_DDR



+VCCSTG



+VALW



+V



+VS



Clock



Full ON



HIGH



HIGH



HIGH



ON



ON



ON



ON



S3 (Suspend to RAM)



LOW



HIGH



HIGH



ON



ON



OFF



OFF



S4 (Suspend to Disk)



LOW



LOW



LOW



ON



OFF



OFF



OFF



S5 (Soft OFF)



LOW



LOW



LOW



ON



OFF



OFF



OFF



1



+VCC_GT +CPU_CORE +0.6VS



HSIO PORT



USB3.0



S0



O



S3 Battery only



O



O



S5 S4 Battery only S5 S4 AC & Battery don't exist



O



O



O



O



S5 S4 AC Only



O



O



O



S3



X



O



O



X



USB2.0



X



X



O



X



X



X



X



X



X



X



PCIE



SMBUS Control Table



Function 1



USB3.0 Conn



2



USB3.0 Conn



3 4



NC NC



5



NC



6



NC



1



USB3.0 Conn



2 3



NC USB3.0 Conn



4



USB2.0 conn



5



Card reader



6



Touch Screen



7



Camera



8



NC



9



NC



10



Bluetooth



5~8 X4



DGPU



9



WLAN



10



NC



11



SATA HDD



12



NC



13~16 X4



3



SLP_S3# SLP_S4# SLP_S5#



+VCCSA



+VCCST



State



2



E



SOURCE



BATT



Charger



DGPU



EC_SMB_CK1



IT8586E



EC_SMB_DA1



+3VL_EC



V



V



X



EC_SMB_CK2



IT8586E



EC_SMB_DA2



+3VS



X



X



EC_SMB_CK3



IT8586E



EC_SMB_DA3



+3VL_EC



X



X



X



X



X



X



PCH_SMB_CLK



PCH



PCH_SMB_DATA +3VALW_PCH



V



+3VG_AON



IT8586E



Memory Down



V



X



V



X



V



X



X



X



+3VL_EC



+3VS



+3VL_EC



PMIC



SODIMM



Thermal Sensor



WLAN WiMAX



X



X



X



X



X



V



X



X



V



X



X



V



X



X



X



V



X



V



X



PCH



+3VALW_PCH



+3VALW_PCH



+3VS



2



PCIE/SATA SSD



3



V



+3VS



EC SMBus1 address



EC SMBus2 address



EC SMBus3 address



PCH SM Bus address



Device



Address



Device



Address



Device



Address



Device



Address



Smart Battery



need to update



Thermal Sensor(NCT7718W)



1001_100xb



PMIC



need to update



DDR4 SODIMM



need to update



Charger



0001 0010 b



PCH



need to update



Wlan



Reserved



DGPU



need to update



4



4



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: A



B



C



D



Document Number



Rev 0.1



PWR Map/SMBUS/HSIO Tuesday, November 10, 2020 E



Sheet



4



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



S360-TGL Document Number



Rev 0.1



Notes_For VGA Tuesday, November 10, 2020 1



Sheet



5



of



110



5



4



ZZZ1



ZZZ2



ZZZ3



ZZZ4



ZZZ5



15W PR1045



PCB 21M NM-D472 REV1 M/B PCB 21M NM-D472 REV1 M/B DA800018210 DA800018210 HS460_DIS@ HS560_DIS@



ZZZ30



PCB 21N NM-D473 REV1 M/B DA800018310 HS760_DIS@



ZZZ31



PCB 21R NM-D475 REV1 M/B DA800018510 HV460_DIS@



ZZZ32



ZZZ33



PCB 21R NM-D475 REV1 M/B DA800018510 HV560_DIS@



I3@



PCB 21M NM-D471 REV1 M/B DA800018110 HS760_UMA@



PR1045



24.3K_0402_1% SD000011300 15W@



12.1K_0402_1% SD03412128J 25W@



PR1039



11.8K_0201_1% SD000019S0T 15W@



PCB 21R NM-D474 REV1 M/B DA800018410 HV560_UMA@



PR1044 21.5K_0402_1% SD03421528J 25W@



PR1043



1/16W_42.2K_1%_0402 SD03442228J 15W@



UC1



PR1039



1/20W_14.3K_1%_0201 20K_0402_1% SD00001DR00 SD03420028J 25W@ 25W@



PR1021



PR1011



PR1008



PR1021



S IC FH8069004531502 QVBG B1 3G BGA 1449 S IC FH8069004530601 QVBD B1 2.4G BGA SA0000AY330 SA0000AY230



1/20W_200K_1%_0402 19.6K_0402_1% SD03420038T SD00000358J 15W@ 15W@



S IC FH8069004529905 QVBA B1 2.8G BGA SA0000AWZ30



178K_0402_1% SD03417838T 15W@



1/20W_93.1K_1%_0402 SD03493128J 25W@



22.6K_0402_1% SD000019W00 25W@



19.6K_0402_1% SD00000358J 25W@



I5NPU42@ PEN@



I3NPU22@ UC1



UC1



UC1



UC1



S IC FH8069004531901 QVBS B1 1.8G BGA 1449 S IC FH8069004531802 QVBK B1 2G BGA 1449 SA0000B4C20



SA0000B4920



OPT17@



Un-stuff



FHD@ HDR@ 14@ 15@



For FHD Panel Part



8M_ROM@



For 8G BIOS ROM part



AMP@ AMP_NS@ AMP_PWR@



For external Amplifier solution part



ANS@ USM@



For power ANS solution part



BL@ CD@ CHANNELA@ DDPA@ SDPA@ DDPB@ SDPB@



For Key Board Backlight part



NPI@ MP@



For NPI Phase part



PCIE4@



For PCIE Gen4 part



EMC@ EMC_15@ EMC_NS@ RF_NS@



For EMC part



AOAC@ CNVI@



For AOAC part



ME@



For ME part



OPT@ OPTN16@ OPTN17@



For NV GPU part



TS@ TP@ UMA@



For touch screen part



For HDR Panel Part For GYG41 part For GYG51 part



D



For external Amplifier solution un-stuff part For discrete Amplifier power solution part



PR1011



UC1



CEL@



Description



I7@ PR1008



CPU



1



ZZZ34



PCB 21R NM-D474 REV1 M/B DA800018410 HV460_UMA@



I5@



UC1



BOM Structure @



25W PR1044



16.9K_0402_1% SD03416928J 15W@



PR1043



PCB 21M NM-D471 REV1 M/B PCB 21M NM-D471 REV1 M/B DA800018110 DA800018110 HS460_UMA@ HS560_UMA@



D



2



BOM Structure



Virtual Symbol_Power



Virtual Symbol PCB



3



PR1024



S IC FH8069004531301 QVBE B1 2.4G BGA S IC FH8069004531602 QVBH B1 3G BGA 1449 SA0000AY240 SA0000AY340



PR1024



1/20W_8.45K_1%_0201 SD000013J8T 15W@



1/20W_14K_1%_0201 SD00001VD00 25W@



For power USM solution part



For C cost down For Memory Channel A part For Memory Channel A DDP part For Memory Channel A SDP part For Memory Channel B DDP part For Memory Channel B SDP part



OPT18@



UG1



PR6816



PR6816



UG1



GPU S IC N17S-G5-A1 BGA 595P GPU MP



S IC N18S-G5-A1 BGA 603P GPU MP SA0000AQJ40



SA0000AEQ20



@



1/16W 22.6K +-1% 0402 SD000019W00 OPT17@



@



1/16W 23.2K +-1% 0402 SD00001NZ00 OPT18@



PU2000



PU2000



RT8816CGQW WQFN 20P PWM



SA0000B3F00



@



DRAM MD



RT_OPT@



UPI_OPT@



UP1666QQKF WQFN 20P CONTROLLER



SA00008G000



GPU Power Solution D16Gb MIC 3200 MT40A1G16KD-062E:E SA0000ADK00 @



D8Gb MIC 3200 MT40A512M16TB-062E:J SA00009R510



For MP Phase Part



D8Gb SAM 3200 K4A8G165WC-BCWE SA0000AC810



For GYG51 EMC part For EMC un-stuff part For RF Un-Stuff part



@ @ C



D16Gb HYX 3200 H5ANAG6NCMR-XNC SA0000AC520 @



HDMI Royalty D8Gb HYX 3200 H5AN8G6NDJR-XNC SA0000AT510 D16Gb SAM 3200 K4AAG165WA-BCWE SA0000AC020



ZZZ38



S IC D4 512MX16/3200 SDQC8G8W16XCWE9N1T FBGA 96P SA0000BC900 @



HDMI@



HDMI PN



RO00000040J @



C



For CNVi WLAN part



For NV N16S-GTR GPU part For NV N17S-G1 GPU part



@



VRAM S IC D5 256M32/2000 K4G80325FC-HC2 SA00007Z720



S IC D5 256MX32 H5GC8H24AJR-R2C SA00009FV00



S IC D5 256MX32 MT51J256M32HF-80:B SA00007Z930 D8G_MIC_S@



D8G_SAM_S@



D8G_HYX_S@



ZZZ6



ZZZ7



ZZZ8



D8G_MIC_V@



X76



MIC D8G S360 X764BF1200P



SAM D8G S360 X764BF1200Q



HYX D8G S360 X764BF1200M



D4G_SAM_S@



D4G_MIC_S@



D4G_HYX_S@



ZZZ9



SAM D4G S360 X764BF1200K SSAMV2GN17@ ZZZ12



DRAM SODIM



SAM V2G N17 S360 X764BF1200J



B



SHYNV2GN18@



Re-Driver



UK1



ZZZ10



MIC D4G S360 X764BF1200N



MIC V2G N18 S360 X764BF1200G SHYNV2GN17@



ZZZ20



SMT D4G S360 X764BF1200L



SMICV2GN17@



ZZZ22



MIC D8G V14V15 X764BE1200K



SMT D4G V14V15 X764BE1200L



SAM D8G V14V15 X764BE1200M



HYX D8G V14V15 X764BE1200R



D4G_SAM_V@



D4G_MIC_V@



D4G_HYX_V@



For TOuch Pad Part



ZZZ19



ZZZ21



For UMA part



SAM D4G V14V15 X764BE1200Q



MIC D4G V14V15 X764BE1200N



ZZZ18



HYN D4G V14V15 X764BE1200P



VSAMV2GN17@



VMICV2GN17@



ZZZ24



ZZZ25



VHYXV2GN17@



ZZZ14 ZZZ26



MIC V2G N17 S360 X764BF1200E SSAMV2GN18@



ZZZ15



ZZZ16



ZZZ17



HYN V2G N18 S360 X764BF1200H



HYN V2G N17 S360 X764BF1200F



SAM V2G N18 S360 X764BF1200D



SAM V2G N17 V14V15 X764BE1200J



MIC V2G N17 V14V15 X764BE1200E



VMICV2GN18@



VSAMV2GN18@



ZZZ27



ZZZ28



ZZZ29



MIC V2G N18 V14V15 X764BE1200H



B



HYX V2G N17 V14V15 X764BE1200G



VHYXV2GN18@



HYX V2G N18 V14V15 X764BE1200F



S IC PI3EQX6741STZDEX TQFN SATA REDRIVER SA000060400 SATA_6741@



D8G_HYX_V@



ZZZ35



HYX D4G S360 X764BF1200R



ZZZ13



D8G_SAM_V@



ZZZ36



D4G_SMT_S@



ZZZ11



SMICV2GN18@



D4G_SMT_V@



ZZZ23



SAM V2G N18 V14V15 X764BE1200D



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Document Number



5



4



3



2



Rev 0.1



Notes_For BOM



Wednesday, November 18, 2020 Sheet



Date: 1



6



of



110



5



4



3



2



1



UC1A 1 OF 21



[47] [47]



CPU_EDP_AUX_P CPU_EDP_AUX_N



CPU_EDP_TX1_P CPU_EDP_TX1_N CPU_EDP_TX0_P CPU_EDP_TX0_N CPU_EDP_AUX_P CPU_EDP_AUX_N



AJ2 AJ1 DN4 DT6



D



eDP* Hot Plug Routing: Recommend 50Ω nominal trace impedance [47] with reasonable noise isolation



HDMI CLK HDMI D0 HDMI D1 HDMI D2



[50] [50] [50] [50] [50] [50] [50] [50]



CPU_EDP_HPD



DR5



CPU_EDP_HPD CPU_HDMI_CLK_P CPU_HDMI_CLK_N CPU_HDMI_TX0_P CPU_HDMI_TX0_N CPU_HDMI_TX1_P CPU_HDMI_TX1_N CPU_HDMI_TX2_P CPU_HDMI_TX2_N



CPU_HDMI_CLK_P CPU_HDMI_CLK_N CPU_HDMI_TX0_P CPU_HDMI_TX0_N CPU_HDMI_TX1_P CPU_HDMI_TX1_N CPU_HDMI_TX2_P CPU_HDMI_TX2_N



T12 T11 Y11 Y9 T9 P9 V11 V9 AB9 AD9



+3VS RPC11 1 2



4 CPU_HDMI_DDC_CLK 3 CPU_HDMI_DDC_DATA 2.2K_0404_4P2R_5%



[50] CPU_HDMI_DDC_CLK [50] CPU_HDMI_DDC_DATA



CPU_HDMI_DDC_CLK DM29 CPU_HDMI_DDC_DATA DK27 CPU_HDMI_HPD



[50] CPU_HDMI_HPD



DG43 DG47 DJ47



TBT_LSX0_RXD



DU8 DV8



TBT_LSX1_RXD



DF6 DD6



TBT_LSX2_RXD



DN23 DM23



TBT_LSX3_RXD



DK23 DN21 DF43 DF45 DF47



C



USB2.0 port Power Switch OC USB3.0 port Power Switch OC



[58] USB_OC1_N [57] USB_OC2_N [47] PCH_ENVDD [47,79] PCH_ENBKL [47] PCH_EDP_PWM



USB_OC1_N USB_OC2_N



DH52 DK45



PCH_ENVDD PCH_ENBKL PCH_EDP_PWM



DM8 DN8 DG10



B



TCP1_TXRX_P1 TCP1_TXRX_N1 TCP1_TXRX_P0 TCP1_TXRX_N0 TCP1_TX_P1 TCP1_TX_N1 TCP1_TX_P0 TCP1_TX_N0 TCP1_AUX_P TCP1_AUX



GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD GPP_E23/DDPA_CTRLDATA GPP_E14/DDSP_HPDA/DISP_MISCA DDIB_TXP_3 DDIB_TXN_3 DDIB_TXP_2 DDIB_TXN_2 DDIB_TXP_1 DDIB_TXN_1 DDIB_TXP_0 DDIB_TXN_0



TCP2_TXRX_P1 TCP2_TXRX_N1 TCP2_TXRX_P0 TCP2_TXRX_N0 TCP2_TX_P1 TCP2_TX_N1 TCP2_TX_P0 TCP2_TX_N0 TCP2_AUX_P TCP2_AUX



DDIB_AUX_P DDIB_AUX GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN GPP_H17/DDPB_CTRLDATA GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD



TCP3_TXRX_P1 TCP3_TXRX_N1 TCP3_TXRX_P0 TCP3_TXRX_N0 TCP3_TX_P1 TCP3_TX_N1 TCP3_TX_P0 TCP3_TX_N0 TCP3_AUX_P TCP3_AUX



GPP_A21/DDPC_CTRLCLK/I2S5_TXD GPP_A22/DDPC_CTRLDATA/I2S5_RXD GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK



GPP_D10 /TBT_LSX2_RXD: DDP3 I2C /TBT_LSX2 /BBSB_LS2 pins VCC configuration Rising edge of RSMRST# This strap has a 20 kohm ± 30% internal pull-down. TBT_LSX2_RXD RC14 1 0 = DDP3 I2C / TBT_LSX2 / BBSB_LS2 pins at 1.8V 1 = DDP3 I2C / TBT_LSX2 / BBSB_LS2 pins at 3.3V RC16 1 Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 2. This signal is in the primary well. 3. An external pull-up resistor is required if the pin is used as HDMI Display I2C, instead of TBT_LSX.



GPP_D12 /TBT_LSX3_RXD: DDP4 I2C /TBT_LSX3 /BBSB_LS3 pins VCC configuration Rising edge of RSMRST# This strap has a 20 kohm ± 30% internal pull-down. TBT_LSX3_RXD RC17 1 0 = DDP4 I2C / TBT_LSX3 / BBSB_LS3 pins at 1.8V 1 = DDP4 I2C / TBT_LSX3 / BBSB_LS3 pins at 3.3V RC18 1 Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 2. This signal is in the primary well. 3. An external pull-up resistor is required if the pin is used as HDMI Display I2C, instead of TBT_LSX.



TC_RCOMP_P TC_RCOMP



GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI



DSI_DE_TE_2



GPP_A17/DISP_MISCC/I2S4_TXD GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM



DDI_RCOMP DISP_UTILS/DSI_DE_TE_1



GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1 GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK



AT2 AT1 AU1 AU2 AD5 AD7 AH7 AH5 AF7 AF5



D



BF1 BF2 BE2 BE1 BD7 BD5 AY5 AY7 BB5 BB7 BK1 BK2 BJ2 BJ1 BM7 BM5 BH5 BH7 BK5 BK7 AN2 AN1



TCRCOMP_P TCRCOMP_N



M8



DSI_DE_TE_2 1



AB1



EDP_COMP



CE4



DISP_UTILS



RC2



1



2 1/20W_150_1%_0201



TP3 @



C



1



TP2 @



DISP_UTILS： Recommend 50 ohm nominal trace impedance with reasonable noise isolation. Requires level shifting on the platform.



EDP_VDDEN EDP_BKLTEN EDP_BKLTCTL



RC4 1/20W_150_1%_0201



@



+3VALW_PCH



+3VALW_PCH @



2 1/20W_4.7K_5%_0201



@



2 1/20W_20K_5%_0201



Primary Well Group A (Per-Pad 1.8 V) Primary Well Group B (Per-Pad 3.3 V) Primary Well Group C (Per-Pad 3.3 V) Primary Well Group D (Per-Pad 3.3 V) Primary Well Group E (Per-Pad 3.3 V) Primary Well Group F (Per-Pad 1.8 V) Primary Well Group H (Per-Pad 3.3 V) Primary Well Group R (Per-Family 1.8 V) Primary Well Group S (Per-Family 1.8 V) Primary Well Group T (Per-Pad 1.8 V or 3.3 V) - Applied to TGL PCH UP3 Only Primary Well Group U (Per-Pad 1.8 V or 3.3 V) - Applied to TGL PCH UP3 Only Deep Sleep Well Group (3.3 V Only)(GPD0~GPD11)



VCC_3P3_1P8_USB_OC



RC8 RC10



Confirmed with Intel Kaiyin follow TGP EDS 20200103



GPP_E21 /TBT_LSX1_RXD: DDP2 I2C /TBT_LSX1 /BBSB_LS1 pins VCC configuration Rising edge of RSMRST# This strap has a 20 kohm ± 30% internal pull-down. TBT_LSX1_RXD RC11 1 0 = DDP2 I2C / TBT_LSX1 / BBSB_LS1 pins at 1.8V 1 = DDP2 I2C / TBT_LSX1 / BBSB_LS1 pins at 3.3V RC12 1 Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 2. This signal is in the primary well. 3. An external pull-up resistor is required if the pin is used as HDMI Display I2C, instead of TBT_LSX.



A



DDIA_AUX_P DDIA_AUX



AY2 AY1 BB1 BB2 AM5 AM7 AT7 AT5 AP7 AP5



TGLLAKE-U_BGA1449



the diffrent with Base: 1.S540 no HDMI,S360&V14&V15 Ues HDMI; 2.S540 Use TCP for TBT,S360&V14&V15 no USE 3.S540 Use GPP_E22&E23,S360&V14&V15 no USE 4.S540 Stuff RC12,S360&V14&V15----- @ 5.S540 No TP3, S360&V14&V15 reserve GPP_E19 /TBT_LSX0_RXD: DDP1 I2C /TBT_LSX0 /BBSB_LS0 pins VCC configuration Rising edge of RSMRST# This strap has a 20 kohm ± 30% internal pull-down. TBT_LSX0_RXD RC5 1 0 = DDP1 I2C / TBT_LSX0 / BBSB_LS0 pins at 1.8V 1 = DDP1 I2C / TBT_LSX0 / BBSB_LS0 pins at 3.3V RC6 1 Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 2. This signal is in the primary well. 3. An external pull-up resistor is required if the pin is used as HDMI Display I2C, instead of TBT_LSX.



TCP0_TXRX_P1 TCP0_TXRX_N1 TCP0_TXRX_P0 TCP0_TXRX_N0 TCP0_TX_P1 TCP0_TX_N1 TCP0_TX_P0 TCP0_TX_N0 TCP0_AUX_P TCP0_AUX



1



CPU_EDP_TX1_P CPU_EDP_TX1_N CPU_EDP_TX0_P CPU_EDP_TX0_N



DDIA_TXP_3 DDIA_TXN_3 DDIA_TXP_2 DDIA_TXN_2 DDIA_TXP_1 DDIA_TXN_1 DDIA_TXP_0 DDIA_TXN_0



2



EDP



[47] [47] [47] [47]



AC2 AC1 AD2 AD1 AF1 AF2 AG2 AG1



1



@



2 0_0201_5%



1



@



2 0_0201_5%



+1.8VALW_PCH



RC7



2



110K_0201_5%



USB_OC1_N



RC9



2



110K_0201_5%



USB_OC2_N



+3VALW_PCH



@



2 1/20W_4.7K_1%_0201



@



2 1/20W_20K_5%_0201



For Glitch Free Cap or pull-down resistor is required depending on panel power sequencing spec or power delivery



PCH_ENVDD



@



2 1/20W_4.7K_1%_0201



@



2 1/20W_20K_5%_0201



2 100K_0402_5%



Change RC13,RC15 to 0402, reserve size for 330nF capacitor



Option 1:Cap Implementation 330 nF for 3.3v Ramp Rate from 5-50ms 33 nF for 3.3V Ramp Rate Less than 5ms



+3VALW_PCH



RC13 1



PCH_ENBKL



RC15 1



2 100K_0402_5%



1



2 100K_0201_5%



Option 2:Pull-down Resistor Implementation 100K for 3.3V Signaling Mode 75K for 1.8V Signaling Mode



PCH_EDP_PWM



RC863



+3VALW_PCH A



@



2 1/20W_4.7K_1%_0201



@



2 1/20W_20K_5%_0201



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



B



4



3



2



Document Number



Rev 0.1



DDI/EDP Tuesday, November 10, 2020 1



Sheet



7



of



110



5



4



3



2



1



SLOT DIMM



D



D



UC1B 2 OF 21 DDR4/LP4



DDR4 (NIL)/LP4



[25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25]



1



+3VALW



2



RC21 100K_0402_5% CPU_DRAMPG_CNTL



[93]



+1.2V 1



C



RC23 1 2 1K_0402_5%



DDR_VTT_CNTL_BASE 2 B



C QC1 MMBT3904WH_SOT323-3



3



E



2



DDR_VTT_CNTL



1



RC24 10K_0402_5% @



1



+1.2V



RC20 1/16W_470_1%_0402 RC22



2 CPU_DRAMRST_N



1



2 0_0201_5%



CPU_DRAMRST_N_R



@ 2 B



[25,26]



1 CC11 0.1U_6.3V_K_X5R_0201 @



DDRA_DQ7 DDRA_DQ6 DDRA_DQ5 DDRA_DQ4 DDRA_DQ3 DDRA_DQ2 DDRA_DQ1 DDRA_DQ0 DDRA_DQ15 DDRA_DQ14 DDRA_DQ13 DDRA_DQ12 DDRA_DQ11 DDRA_DQ10 DDRA_DQ9 DDRA_DQ8 DDRA_DQ23 DDRA_DQ22 DDRA_DQ21 DDRA_DQ20 DDRA_DQ19 DDRA_DQ18 DDRA_DQ17 DDRA_DQ16 DDRA_DQ31 DDRA_DQ30 DDRA_DQ29 DDRA_DQ28 DDRA_DQ27 DDRA_DQ26 DDRA_DQ25 DDRA_DQ24 DDRA_DQ39 DDRA_DQ38 DDRA_DQ37 DDRA_DQ36 DDRA_DQ35 DDRA_DQ34 DDRA_DQ33 DDRA_DQ32 DDRA_DQ47 DDRA_DQ46 DDRA_DQ45 DDRA_DQ44 DDRA_DQ43 DDRA_DQ42 DDRA_DQ41 DDRA_DQ40 DDRA_DQ55 DDRA_DQ54 DDRA_DQ53 DDRA_DQ52 DDRA_DQ51 DDRA_DQ50 DDRA_DQ49 DDRA_DQ48 DDRA_DQ63 DDRA_DQ62 DDRA_DQ61 DDRA_DQ60 DDRA_DQ59 DDRA_DQ58 DDRA_DQ57 DDRA_DQ56



DDRA_DQ7 DDRA_DQ6 DDRA_DQ5 DDRA_DQ4 DDRA_DQ3 DDRA_DQ2 DDRA_DQ1 DDRA_DQ0 DDRA_DQ15 DDRA_DQ14 DDRA_DQ13 DDRA_DQ12 DDRA_DQ11 DDRA_DQ10 DDRA_DQ9 DDRA_DQ8 DDRA_DQ23 DDRA_DQ22 DDRA_DQ21 DDRA_DQ20 DDRA_DQ19 DDRA_DQ18 DDRA_DQ17 DDRA_DQ16 DDRA_DQ31 DDRA_DQ30 DDRA_DQ29 DDRA_DQ28 DDRA_DQ27 DDRA_DQ26 DDRA_DQ25 DDRA_DQ24 DDRA_DQ39 DDRA_DQ38 DDRA_DQ37 DDRA_DQ36 DDRA_DQ35 DDRA_DQ34 DDRA_DQ33 DDRA_DQ32 DDRA_DQ47 DDRA_DQ46 DDRA_DQ45 DDRA_DQ44 DDRA_DQ43 DDRA_DQ42 DDRA_DQ41 DDRA_DQ40 DDRA_DQ55 DDRA_DQ54 DDRA_DQ53 DDRA_DQ52 DDRA_DQ51 DDRA_DQ50 DDRA_DQ49 DDRA_DQ48 DDRA_DQ63 DDRA_DQ62 DDRA_DQ61 DDRA_DQ60 DDRA_DQ59 DDRA_DQ58 DDRA_DQ57 DDRA_DQ56



CP53 CP52 CP50 CP49 CU53 CU52 CU50 CU49 CH53 CH52 CH50 CH49 CL53 CL52 CL50 CL49 CT47 CV47 CT45 CV45 CT42 CV42 CT41 CV41 CK47 CM47 CK45 CM45 CK42 CM42 CM41 CK41 BF53 BF52 BF50 BF49 BH53 BH52 BH50 BH49 AY53 AY52 AY50 AY49 BC53 BC52 BC50 BC49 BK47 BK45 BH47 BH45 BH42 BK42 BK41 BH41 BD47 BB47 BD45 BB45 BB42 BB41 BD42 BD41



DDR0_DQ0_7/DDR0_DQ0_7 DDR0_DQ0_6/DDR0_DQ0_6 DDR0_DQ0_5/DDR0_DQ0_5 DDR0_DQ0_4/DDR0_DQ0_4 DDR0_DQ0_3/DDR0_DQ0_3 DDR0_DQ0_2/DDR0_DQ0_2 DDR0_DQ0_1/DDR0_DQ0_1 DDR0_DQ0_0/DDR0_DQ0_0 DDR0_DQ1_7/DDR0_DQ1_7 DDR0_DQ1_6/DDR0_DQ1_6 DDR0_DQ1_5/DDR0_DQ1_5 DDR0_DQ1_4/DDR0_DQ1_4 DDR0_DQ1_3/DDR0_DQ1_3 DDR0_DQ1_2/DDR0_DQ1_2 DDR0_DQ1_1/DDR0_DQ1_1 DDR0_DQ1_0/DDR0_DQ1_0 DDR0_DQ2_7/DDR1_DQ0_7 DDR0_DQ2_6/DDR1_DQ0_6 DDR0_DQ2_5/DDR1_DQ0_5 DDR0_DQ2_4/DDR1_DQ0_4 DDR0_DQ2_3/DDR1_DQ0_3 DDR0_DQ2_2/DDR1_DQ0_2 DDR0_DQ2_1/DDR1_DQ0_1 DDR0_DQ2_0/DDR1_DQ0_0 DDR0_DQ3_7/DDR1_DQ1_7 DDR0_DQ3_6/DDR1_DQ1_6 DDR0_DQ3_5/DDR1_DQ1_5 DDR0_DQ3_4/DDR1_DQ1_4 DDR0_DQ3_3/DDR1_DQ1_3 DDR0_DQ3_2/DDR1_DQ1_2 DDR0_DQ3_1/DDR1_DQ1_1 DDR0_DQ3_0/DDR1_DQ1_0 DDR0_DQ4_7/DDR2_DQ0_7 DDR0_DQ4_6/DDR2_DQ0_6 DDR0_DQ4_5/DDR2_DQ0_5 DDR0_DQ4_4/DDR2_DQ0_4 DDR0_DQ4_3/DDR2_DQ0_3 DDR0_DQ4_2/DDR2_DQ0_2 DDR0_DQ4_1/DDR2_DQ0_1 DDR0_DQ4_0/DDR2_DQ0_0 DDR0_DQ5_7/DDR2_DQ1_7 DDR0_DQ5_6/DDR2_DQ1_6 DDR0_DQ5_5/DDR2_DQ1_5 DDR0_DQ5_4/DDR2_DQ1_4 DDR0_DQ5_3/DDR2_DQ1_3 DDR0_DQ5_2/DDR2_DQ1_2 DDR0_DQ5_1/DDR2_DQ1_1 DDR0_DQ5_0/DDR2_DQ1_0 DDR0_DQ6_7/DDR3_DQ0_7 DDR0_DQ6_6/DDR3_DQ0_6 DDR0_DQ6_5/DDR3_DQ0_5 DDR0_DQ6_4/DDR3_DQ0_4 DDR0_DQ6_3/DDR3_DQ0_3 DDR0_DQ6_2/DDR3_DQ0_2 DDR0_DQ6_1/DDR3_DQ0_1 DDR0_DQ6_0/DDR3_DQ0_0 DDR0_DQ7_7/DDR3_DQ1_7 DDR0_DQ7_6/DDR3_DQ1_6 DDR0_DQ7_5/DDR3_DQ1_5 DDR0_DQ7_4/DDR3_DQ1_4 DDR0_DQ7_3/DDR3_DQ1_3 DDR0_DQ7_2/DDR3_DQ1_2 DDR0_DQ7_1/DDR3_DQ1_1 DDR0_DQ7_0/DDR3_DQ1_0



DDR0_CLK_P1/DDR3_CLK_P DDR0_CLK_N1/DDR3_CLK NC/DDR2_CLK_P NC/DDR2_CLK NC/DDR1_CLK_P NC/DDR1_CLK DDR0_CLK_P0/DDR0_CLK_P DDR0_CLK_N0/DDR0_CLK DDR4/LP4



NC/DDR3_CKE0 NC/DDR3_CKE1 NC/DDR2_CKE0 NC/DDR2_CKE1 NC/DDR1_CKE0 NC/DDR1_CKE1 NC/DDR0_CKE0 NC/DDR0_CKE1 DDR4/LP4



DDR0_CKE1/DDR2_CA4 DDR0_CKE0/DDR2_CA5 DDR4/LP4



DDR0_CS1/DDR1_CA1 DDR0_CS0/NC DDR4/LP4



NC/DDR0_CA0 NC/DDR0_CA1 NC/DDR2_CS0 NC/DDR3_CA5 NC/DDR3_CA4 NC/DDR3_CA3 NC/DDR3_CA2 DDR4 (NIL)/LP4



DDR0_DQSP_7/DDR3_DQSP_1 DDR0_DQSN_7/DDR3_DQSN_1 DDR0_DQSP_6/DDR3_DQSP_0 DDR0_DQSN_6/DDR3_DQSN_0 DDR0_DQSP_5/DDR2_DQSP_1 DDR0_DQSN_5/DDR2_DQSN_1 DDR0_DQSP_4/DDR2_DQSP_0 DDR0_DQSN_4/DDR2_DQSN_0 DDR0_DQSP_3/DDR1_DQSP_1 DDR0_DQSN_3/DDR1_DQSN_1 DDR0_DQSP_2/DDR1_DQSP_0 DDR0_DQSN_2/DDR1_DQSN_0 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQSN_0/DDR0_DQSN_0 DDR4/LP4



DDR0_ODT1/DDR1_CA0 DDR0_ODT0/DDR1_CS0 DDR4/LP4



DDR0_MA16/DDR1_CA4 DDR0_MA15/DDR1_CA3 DDR0_MA14/DDR1_CA2 DDR0_MA13/DDR1_CS1 DDR0_MA12/DDR2_CA1 DDR0_MA11/NC DDR0_MA10/DDR3_CA1 DDR0_MA9/DDR2_CA0 DDR0_MA8/DDR0_CA2 DDR0_MA7/DDR0_CA4 DDR0_MA6/DDR0_CA3 DDR0_MA5/DDR0_CA5 DDR0_MA4/DDR0_CS0 DDR0_MA3/DDR0_CS1 DDR0_MA2/DDR3_CS0 DDR0_MA1/NC DDR0_MA0/NC DDR4/LP4



DDR0_BG1/DDR2_CA2 DDR0_BG0/DDR2_CA3 DDR4/LP4



DDR0_BA1/DDR1_CA5 DDR0_BA0/DDR3_CA0 DDR4/LP4



DDR0_ACT#/DDR2_CS1 DDR4/LP4



DDR0_PAR/DDR3_CS1 DDR4



DDR0_ALERT# DDR0_VREF_CA DDR_VTT_CTL DRAM_RESET# DDR_RCOMP



BT42 BT41 BP52 BP53 CD42 CD41 CC52 CC53



DDRA_CLK1_P DDRA_CLK1_N



DDRA_CLK0_P DDRA_CLK0_N



DDRA_CLK1_P DDRA_CLK1_N



[25] [25]



DDRA_CLK0_P DDRA_CLK0_N



[25] [25]



DDRA_CKE1 DDRA_CKE0



[25] [25]



DDRA_CS1_N DDRA_CS0_N



[25] [25]



BT45 BT47 BN51 BN53 CD45 CD47 CA51 CA53 BU52 BL50



DDRA_CKE1 DDRA_CKE0



CF42 CF47



DDRA_CS1_N DDRA_CS0_N



CE53 CE50 BL53 BP47 BP42 BP45 BP44



C



BB44 BD44 BK44 BH44 BA51 BA50 BG51 BG50 CK44 CM44 CT44 CV44 CK51 CK50 CR51 CR50



DDRA_DQS7_P DDRA_DQS7_N DDRA_DQS6_P DDRA_DQS6_N DDRA_DQS5_P DDRA_DQS5_N DDRA_DQS4_P DDRA_DQS4_N DDRA_DQS3_P DDRA_DQS3_N DDRA_DQS2_P DDRA_DQS2_N DDRA_DQS1_P DDRA_DQS1_N DDRA_DQS0_P DDRA_DQS0_N



CF44 CF45



DDRA_ODT1 DDRA_ODT0



CB47 CB44 CB45 CF41 BU53 BT51 BV42 BU50 BY53 CA50 BY52 BY50 CD51 CD53 BV47 CE52 BV41



DDRA_MA16_RAS_N DDRA_MA15_CAS_N DDRA_MA14_WE_N DDRA_MA13 DDRA_MA12 DDRA_MA11 DDRA_MA10 DDRA_MA9 DDRA_MA8 DDRA_MA7 DDRA_MA6 DDRA_MA5 DDRA_MA4 DDRA_MA3 DDRA_MA2 DDRA_MA1 DDRA_MA0



BN50 BL52



DDRA_BG1 DDRA_BG0



CB42 BV44



DDRA_BA1 DDRA_BA0



BT53



DDRA_ACT_N



BV45



DDRA_PAR



AU50 AU49



DDRA_ALERT_N DDR_SA_VREFCA



E52 DV47 C49



DDR_VTT_CNTL CPU_DRAMRST_N DDR_RCOMP0



DDRA_DQS7_P DDRA_DQS7_N DDRA_DQS6_P DDRA_DQS6_N DDRA_DQS5_P DDRA_DQS5_N DDRA_DQS4_P DDRA_DQS4_N DDRA_DQS3_P DDRA_DQS3_N DDRA_DQS2_P DDRA_DQS2_N DDRA_DQS1_P DDRA_DQS1_N DDRA_DQS0_P DDRA_DQS0_N



[25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25]



DDRA_ODT1 DDRA_ODT0



[25] [25]



DDRA_MA16_RAS_N DDRA_MA15_CAS_N DDRA_MA14_WE_N DDRA_MA13 DDRA_MA12 DDRA_MA11 DDRA_MA10 DDRA_MA9 DDRA_MA8 DDRA_MA7 DDRA_MA6 DDRA_MA5 DDRA_MA4 DDRA_MA3 DDRA_MA2 DDRA_MA1 DDRA_MA0



[25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25] [25]



DDRA_BG1 DDRA_BG0



[25] [25]



DDRA_BA1 DDRA_BA0



[25] [25]



DDRA_ACT_N



[25]



DDRA_PAR



[25]



DDRA_ALERT_N DDR_SA_VREFCA



[25] [25]



RC19 1



the diffrent with Base: 1.S540 BT42&BT41BU52&CF42*CF44---- NC, S360&V14V15 use For SO-DIMM



B



2 1/20W_100_1%_0201



TGLLAKE-U_BGA1449 @



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev



DDR4-Chanel-A Tuesday, November 10, 2020 1



Sheet



8



of



110



5



4



3



2



1



Memory Down



D



D



UC1C 3 OF 21 DDR4/LP4



DDR4 (NIL)/LP4



[26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26]



C



DDRB_DQ7 DDRB_DQ6 DDRB_DQ5 DDRB_DQ4 DDRB_DQ3 DDRB_DQ2 DDRB_DQ1 DDRB_DQ0 DDRB_DQ15 DDRB_DQ14 DDRB_DQ13 DDRB_DQ12 DDRB_DQ11 DDRB_DQ10 DDRB_DQ9 DDRB_DQ8 DDRB_DQ23 DDRB_DQ22 DDRB_DQ21 DDRB_DQ20 DDRB_DQ19 DDRB_DQ18 DDRB_DQ17 DDRB_DQ16 DDRB_DQ31 DDRB_DQ30 DDRB_DQ29 DDRB_DQ28 DDRB_DQ27 DDRB_DQ26 DDRB_DQ25 DDRB_DQ24 DDRB_DQ39 DDRB_DQ38 DDRB_DQ37 DDRB_DQ36 DDRB_DQ35 DDRB_DQ34 DDRB_DQ33 DDRB_DQ32 DDRB_DQ47 DDRB_DQ46 DDRB_DQ45 DDRB_DQ44 DDRB_DQ43 DDRB_DQ42 DDRB_DQ41 DDRB_DQ40 DDRB_DQ55 DDRB_DQ54 DDRB_DQ53 DDRB_DQ52 DDRB_DQ51 DDRB_DQ50 DDRB_DQ49 DDRB_DQ48 DDRB_DQ63 DDRB_DQ62 DDRB_DQ61 DDRB_DQ60 DDRB_DQ59 DDRB_DQ58 DDRB_DQ57 DDRB_DQ56



DDRB_DQ7 DDRB_DQ6 DDRB_DQ5 DDRB_DQ4 DDRB_DQ3 DDRB_DQ2 DDRB_DQ1 DDRB_DQ0 DDRB_DQ15 DDRB_DQ14 DDRB_DQ13 DDRB_DQ12 DDRB_DQ11 DDRB_DQ10 DDRB_DQ9 DDRB_DQ8 DDRB_DQ23 DDRB_DQ22 DDRB_DQ21 DDRB_DQ20 DDRB_DQ19 DDRB_DQ18 DDRB_DQ17 DDRB_DQ16 DDRB_DQ31 DDRB_DQ30 DDRB_DQ29 DDRB_DQ28 DDRB_DQ27 DDRB_DQ26 DDRB_DQ25 DDRB_DQ24 DDRB_DQ39 DDRB_DQ38 DDRB_DQ37 DDRB_DQ36 DDRB_DQ35 DDRB_DQ34 DDRB_DQ33 DDRB_DQ32 DDRB_DQ47 DDRB_DQ46 DDRB_DQ45 DDRB_DQ44 DDRB_DQ43 DDRB_DQ42 DDRB_DQ41 DDRB_DQ40 DDRB_DQ55 DDRB_DQ54 DDRB_DQ53 DDRB_DQ52 DDRB_DQ51 DDRB_DQ50 DDRB_DQ49 DDRB_DQ48 DDRB_DQ63 DDRB_DQ62 DDRB_DQ61 DDRB_DQ60 DDRB_DQ59 DDRB_DQ58 DDRB_DQ57 DDRB_DQ56



AL53 AL52 AL50 AL49 AP53 AP52 AP50 AP49 AF53 AF52 AF50 AF49 AH53 AH52 AH50 AH49 AR41 AV42 AR42 AV41 AR45 AV45 AR47 AV47 AJ41 AJ42 AL41 AL42 AJ45 AJ47 AL45 AL47 A43 B43 D43 E44 A46 B46 D46 E47 E38 D38 B38 A38 E41 D40 B40 A40 G42 G41 J41 J42 G45 J45 G47 J47 G38 G36 H36 H38 N36 L36 L38 N38



DDR1_DQ0_7/DDR4_DQ0_7 DDR1_DQ0_6/DDR4_DQ0_6 DDR1_DQ0_5/DDR4_DQ0_5 DDR1_DQ0_4/DDR4_DQ0_4 DDR1_DQ0_3/DDR4_DQ0_3 DDR1_DQ0_2/DDR4_DQ0_2 DDR1_DQ0_1/DDR4_DQ0_1 DDR1_DQ0_0/DDR4_DQ0_0 DDR1_DQ1_7/DDR4_DQ1_7 DDR1_DQ1_6/DDR4_DQ1_6 DDR1_DQ1_5/DDR4_DQ1_5 DDR1_DQ1_4/DDR4_DQ1_4 DDR1_DQ1_3/DDR4_DQ1_3 DDR1_DQ1_2/DDR4_DQ1_2 DDR1_DQ1_1/DDR4_DQ1_1 DDR1_DQ1_0/DDR4_DQ1_0 DDR1_DQ2_7/DDR5_DQ0_7 DDR1_DQ2_6/DDR5_DQ0_6 DDR1_DQ2_5/DDR5_DQ0_5 DDR1_DQ2_4/DDR5_DQ0_4 DDR1_DQ2_3/DDR5_DQ0_3 DDR1_DQ2_2/DDR5_DQ0_2 DDR1_DQ2_1/DDR5_DQ0_1 DDR1_DQ2_0/DDR5_DQ0_0 DDR1_DQ3_7/DDR5_DQ1_7 DDR1_DQ3_6/DDR5_DQ1_6 DDR1_DQ3_5/DDR5_DQ1_5 DDR1_DQ3_4/DDR5_DQ1_4 DDR1_DQ3_3/DDR5_DQ1_3 DDR1_DQ3_2/DDR5_DQ1_2 DDR1_DQ3_1/DDR5_DQ1_1 DDR1_DQ3_0/DDR5_DQ1_0 DDR1_DQ4_7/DDR6_DQ0_7 DDR1_DQ4_6/DDR6_DQ0_6 DDR1_DQ4_5/DDR6_DQ0_5 DDR1_DQ4_4/DDR6_DQ0_4 DDR1_DQ4_3/DDR6_DQ0_3 DDR1_DQ4_2/DDR6_DQ0_2 DDR1_DQ4_1/DDR6_DQ0_1 DDR1_DQ4_0/DDR6_DQ0_0 DDR1_DQ5_7/DDR6_DQ1_7 DDR1_DQ5_6/DDR6_DQ1_6 DDR1_DQ5_5/DDR6_DQ1_5 DDR1_DQ5_4/DDR6_DQ1_4 DDR1_DQ5_3/DDR6_DQ1_3 DDR1_DQ5_2/DDR6_DQ1_2 DDR1_DQ5_1/DDR6_DQ1_1 DDR1_DQ5_0/DDR6_DQ1_0 DDR1_DQ6_7/DDR7_DQ0_7 DDR1_DQ6_6/DDR7_DQ0_6 DDR1_DQ6_5/DDR7_DQ0_5 DDR1_DQ6_4/DDR7_DQ0_4 DDR1_DQ6_3/DDR7_DQ0_3 DDR1_DQ6_2/DDR7_DQ0_2 DDR1_DQ6_1/DDR7_DQ0_1 DDR1_DQ6_0/DDR7_DQ0_0 DDR1_DQ7_7/DDR7_DQ1_7 DDR1_DQ7_6/DDR7_DQ1_6 DDR1_DQ7_5/DDR7_DQ1_5 DDR1_DQ7_4/DDR7_DQ1_4 DDR1_DQ7_3/DDR7_DQ1_3 DDR1_DQ7_2/DDR7_DQ1_2 DDR1_DQ7_1/DDR7_DQ1_1 DDR1_DQ7_0/DDR7_DQ1_0



DDR1_CLK_P1/DDR7_CLK_P DDR1_CLK_N1/DDR7_CLK NC/DDR6_CLK_P NC/DDR6_CLK NC/DDR5_CLK_P NC/DDR5_CLK DDR1_CLK_P0/DDR4_CLK_P DDR1_CLK_N0/DDR4_CLK DDR4/LP4



NC/DDR7_CKE0 NC/DDR7_CKE1 NC/DDR6_CKE0 NC/DDR6_CKE1 NC/DDR5_CKE0 NC/DDR5_CKE1 NC/DDR4_CKE0 NC/DDR4_CKE1 DDR4/LP4



DDR1_CKE1/DDR6_CA4 DDR1_CKE0/DDR6_CA5 DDR4/LP4



DDR1_CS1/DDR5_CA1 DDR1_CS0/NC DDR4/LP4



NC/DDR7_CA5 NC/DDR7_CA4 NC/DDR7_CA3 NC/DDR7_CA2 NC/DDR6_CS0 NC/DDR4_CA1 NC/DDR4_CA0 DDR4 (NIL)/LP4



DDR1_DQSP_7/DDR7_DQSP_1 DDR1_DQSN_7/DDR7_DQSN_1 DDR1_DQSP_6/DDR7_DQSP_0 DDR1_DQSN_6/DDR7_DQSN_0 DDR1_DQSP_5/DDR6_DQSP_1 DDR1_DQSN_5/DDR6_DQSN_1 DDR1_DQSP_4/DDR6_DQSP_0 DDR1_DQSN_4/DDR6_DQSN_0 DDR1_DQSP_3/DDR5_DQSP_1 DDR1_DQSN_3/DDR5_DQSN_1 DDR1_DQSP_2/DDR5_DQSP_0 DDR1_DQSN_2/DDR5_DQSN_0 DDR1_DQSP_1/DDR4_DQSP_1 DDR1_DQSN_1/DDR4_DQSN_1 DDR1_DQSP_0/DDR4_DQSP_0 DDR1_DQSN_0/DDR4_DQSN_0 DDR4/LP4



DDR1_ODT1/DDR5_CA0 DDR1_ODT0/DDR5_CS0 DDR4/LP4



DDR1_MA16/DDR5_CA4 DDR1_MA15/DDR5_CA3 DDR1_MA14/DDR5_CA2 DDR1_MA13/DDR5_CS1 DDR1_MA12/DDR6_CA1 DDR1_MA11/NC DDR1_MA10/DDR7_CA1 DDR1_MA9/DDR6_CA0 DDR1_MA8/DDR4_CA2 DDR1_MA7/DDR4_CA4 DDR1_MA6/DDR4_CA3 DDR1_MA5/DDR4_CA5 DDR1_MA4/DDR4_CS0 DDR1_MA3/DDR4_CS1 DDR1_MA2/DDR7_CS0 DDR1_MA1/NC DDR1_MA0/NC



B



DDR4/LP4



DDR1_BG1/DDR6_CA2 DDR1_BG0/DDR6_CA3 DDR4/LP4



DDR1_BA1/DDR5_CA5 DDR1_BA0/DDR7_CA0 DDR1_ACT#/DDR6_CS1 DDR1_PAR/DDR7_CS1 DDR1_ALERT# DDR1_VREF_CA



R41 R42 M52 M53 AC42 AC41 Y52 Y53



DDRB_CLK0_P DDRB_CLK0_N



DDRB_CLK0_P DDRB_CLK0_N



[26] [26]



DDRB_CKE0



[26]



DDRB_CS0_N



[26]



DDRB_DQS7_P DDRB_DQS7_N DDRB_DQS6_P DDRB_DQS6_N DDRB_DQS5_P DDRB_DQS5_N DDRB_DQS4_P DDRB_DQS4_N DDRB_DQS3_P DDRB_DQS3_N DDRB_DQS2_P DDRB_DQS2_N DDRB_DQS1_P DDRB_DQS1_N DDRB_DQS0_P DDRB_DQS0_N



[26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26] [26]



DDRB_ODT0



[26]



R47 R45 K51 K53 AC47 AC45 W51 W53 P52 J50



DDRB_CKE0



AE42 AE47



DDRB_CS0_N



N42 N45 N44 N47 J53 AC50 AC53 C



K36 K38 G44 J44 D39 C39 C45 D45 AJ44 AL44 AV44 AR44 AG51 AG50 AN51 AN50



DDRB_DQS7_P DDRB_DQS7_N DDRB_DQS6_P DDRB_DQS6_N DDRB_DQS5_P DDRB_DQS5_N DDRB_DQS4_P DDRB_DQS4_N DDRB_DQS3_P DDRB_DQS3_N DDRB_DQS2_P DDRB_DQS2_N DDRB_DQS1_P DDRB_DQS1_N DDRB_DQS0_P DDRB_DQS0_N



AE44 AE45



DDRB_ODT0



AA47 AA44 AA45 AE41 P53 N51 U42 P50 U53 W50 U52 U50 AA51 AA53 U47 AC52 U41



DDRB_MA16_RAS_N DDRB_MA15_CAS_N DDRB_MA14_WE_N DDRB_MA13 DDRB_MA12 DDRB_MA11 DDRB_MA10 DDRB_MA9 DDRB_MA8 DDRB_MA7 DDRB_MA6 DDRB_MA5 DDRB_MA4 DDRB_MA3 DDRB_MA2 DDRB_MA1 DDRB_MA0



K50 J52



DDRB_BG1 DDRB_BG0



AA42 U44



DDRB_BA1 DDRB_BA0



N53



DDRB_ACT_N



U45



DDRB_PAR



AU53 AU52



DDRB_ALERT_N DDR_SB_VREFCA



DDRB_MA16_RAS_N [26] DDRB_MA15_CAS_N [26] DDRB_MA14_WE_N [26] DDRB_MA13 [26] DDRB_MA12 [26] DDRB_MA11 [26] DDRB_MA10 [26] DDRB_MA9 [26] DDRB_MA8 [26] DDRB_MA7 [26] DDRB_MA6 [26] DDRB_MA5 [26] DDRB_MA4 [26] DDRB_MA3 [26] DDRB_MA2 [26] DDRB_MA1 [26] DDRB_MA0 [26] DDRB_BG1 DDRB_BG0



[26] [26]



DDRB_BA1 DDRB_BA0



[26] [26]



DDRB_ACT_N



[26]



DDRB_PAR



[26]



DDRB_ALERT_N DDR_SB_VREFCA



[26] [26]



B



TGLLAKE-U_BGA1449 @



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev



DDR4-Chanel-B Tuesday, November 10, 2020 1



Sheet



9



of



110



5



4



3



2



1



+VCCSTG_TERM +VCC1.05_OUT_FET RC25 1 RC26 1



D



RC38 1 @ @



DBG_PMODE



2 1K_0201_5%



RC40 1



2 1K_0201_5%



RC41 1



@ @



RC36 1



DBG_PMODE(Reserved): Rising edge of RSMRST# This strap has a 20 kohm ± 30% internal pull-up. This strap should sample high. There should NOT be any on-board device driving it to opposite direction during strap sampling. Notes: 1. The internal pull-up is disabled after RSMRST# deasserts. 2. This signal is in the primary well. Confirmed with Intel Kaiyin, follow PDG 20200103



PCH_JTAG_TDO



2 51_0402_5%



CPU_JTAG_TCK



2@ RC48 1 0_0201_5% CPU_JTAG_TRST_N RC233 1 2@ 0_0201_5% CPU_JTAG_TMS 2@ RC234 1 0_0201_5%



PCH_JTAG_JTAGX



PCH_JTAG_TDO



2 51_0402_5%



CPU_JTAG_TDI



2 51_0402_5%



CPU_JTAG_TMS



2 51_0402_5%



CPU_JTAG_TCK



CPU_JTAG_TDO CPU_JTAG_TDI



RC35 1



@



2 51_0402_5%



CPU_JTAG_TRST_N



RC37 1



@



2 51_0402_5%



PCH_JTAG_TCK



PCH_JTAG_TRST_N PCH_JTAG_TMS



2@ RC235 1 0_0201_5% 2@ RC236 1



D



PCH_JTAG_TDI



0_0201_5%



UC1U 21 OF 21



[79] [20,79] +VCCSTG_TERM RC44



PCH_PECI H_PROCHOT_N



Follow CRB,Page35 1



RC39 1 RC42 1 RC43 1



2 1K_0201_5%



H_PROCHOT_N



PCH_CATERR_N M7 PCH_PECI BK9 2 1/20W_499_1%_0201 H_PROCHOT_N_R E2 PCH_H_THRMTRIP_N M5 2 1/20W_49.9_1%_0201 PROC_OPI_RCOMPCT39 2 1/20W_49.9_1%_0201 PCH_OPI_RCOMP CB9 CW12 CM39 DBG_PMODE



+VCCST_CPU C



RC45



1



2 1K_0201_5%



PCH_H_THRMTRIP_N



DB42 DB41 DF8 DU5



+3VS RC47



1



2 10K_0201_5%



EC_PCH_SCI_N



[79]



EC_PCH_SCI_N



EC_PCH_SCI_N



DF4



GPP_H2 GPP_H1 GPP_H0



DF31 DV32 DW32 DJ27



CATERR# PECI PROCHOT# THRMTRIP#



PROC_TRST# PROC_TMS PROC_TDO PROC_TDI PROC_TCK



PROC_POPIRCOMP PCH_OPIRCOMP TP_1 TP_2 DBG_PMODE GPP_B4/CPU_GP3 GPP_B3/CPU_GP2 GPP_E7/CPU_GP1 GPP_E3/CPU_GP0



CPU_JTAG_TRST_N CPU_JTAG_TMS CPU_JTAG_TDO CPU_JTAG_TDI CPU_JTAG_TCK



D8 A9 E12 B12 A7 H4



PCH_JTAG_JTAGX PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TCK PCH_JTAG_TRST_N



C11 D11



PROC_PREQ_N PROC_PRDY_N



G1



CPU_EAR



DT15 DR15 DT14



GPP_F7



UC1D



PCH_JTAGX PCH_TMS PCH_TDO PCH_TDI PCH_TCK PCH_TRST# PROC_PREQ# PROC_PRDY#



EAR_N/EAR_N_TEST_NCTF GPP_H2 GPP_H1 GPP_H0



K4 B9 D12 A12 B6



GPP_F7 GPP_F9 GPP_F10



4 OF 21



DV24 DW47 DW49 A48 1 1



TP11 TP12



RSVD_2 RSVD_3 RSVD_4 RSVD_5



@ @



C



TGLLAKE-U_BGA1449 @



GPP_F10



GPP_H19/TIME_SYNC0 TGLLAKE-U_BGA1449 @



+VCCST_CPU



1 2 RC34 1K_0201_5%



2



@



RC46 1K_0201_5%



@



GPP_F7



RC50 1 @



2 1/20W_20K_5%_0201



GPP_F10



RC49 1 @



2 1/20W_20K_5%_0201



PCH_CATERR_N



0000 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is enabled 0010 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is disabled 0100 = BIOS on eSPI Peripheral Channel; CSME on master attached SPI 1000 = Slave Attached Flash Configuration (BIOS / CSME on eSPI attached device). 1100 = BIOS on eSPI peripheral Channel; CSME on slave attached SPI.



Place at C/S side for Debug easy



Issued Date



GPP_F7 and GPP_F10: Reserved, Rising edge of RSMRST# This strap has a 20 kohm ± 30% internal pull-down. This strap should sample LOW. There should NOT be any onboard device driving it to opposite direction during strap sampling. Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 2. This signal is in the primary well.



EC can not support, Delete --20200227



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



B



1



PDG Page116，CRB,Page35



RC30 1K_0201_5%



1



GPP_H0 GPP_H1 GPP_H2



GPP_H0: Boot Strap 1 GPP_H1: Boot Strap 2 GPP_H2: Boot Strap 3 Boot Strap, Rising edge of RSMRST# These straps has a 20 kohm ± 30% internal pull-down. They are bit [3:1] of a total of 4-bit encoded pin straps for boot configuration. Refer to Boot Strap 0 (on GPP_C5) for the encoding. Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 2. This signal is in the primary well.



EAR Stall CPU reset sequence until de-asserted: - 1 = (Default) Normal Operation; No stall. CPU_EAR - 0 = Stall; Follow PDG Page118



2



RC29 1/20W_4.7K_5%_0201



1 2 1



@



RC33 1/20W_20K_5%_0201



@



2



RC28 1/20W_4.7K_5%_0201



1 2 1



@



RC32 1/20W_20K_5%_0201



@



2



RC27 1/20W_4.7K_5%_0201



2 1 2 A



@



RC31 1/20W_20K_5%_0201



1



+3VALW_PCH



B



+VCCSTG_CPU



the diffrent with Base: 1.S540 CM39 PIN---- NC,S360&V14V15 Reserve TP9; 2.S540 DB42 PIN For TBT_FORCE_PWR,S360&V14V15 --NC



4



3



2



Document Number



MISC/JTAG



Tuesday, November 10, 2020



Sheet 1



10



Rev



of



110



A



5



4



3



+3VALW_PCH



1



UC1E 1 RC74



PCH_SPI0_CS0_N



1/20W_150K_5%_0201 2



1 RC68



PCH_SPI0_CS1_N



1/20W_4.7K_5%_0201 1



2 RC70



PCH_SPI0_SI



100K_0201_5%



2



1



RC71



PCH_SPI0_IO2



100K_0201_5%



2



1



RC72



PCH_SPI0_IO3



5 OF 21



Internal 20K PD @PCH VIH=0.7VCC @SPI ROM



BIOS SPI operates at 3.3V [27] [27] [27] [27] [27] [27] [27]



PCH_SPI0_CLK PCH_SPI0_IO3 PCH_SPI0_IO2 PCH_SPI0_SO PCH_SPI0_SI PCH_SPI0_CS1_N PCH_SPI0_CS0_N



PCH_SPI0_CLK PCH_SPI0_IO3 PCH_SPI0_IO2 PCH_SPI0_SO PCH_SPI0_SI PCH_SPI0_CS1_N PCH_SPI0_CS0_N



SPI0_MOSI(PCH_SPI_SI ): Rising edge of RSMRST# External pull-up is required. Recommend 4.7 kohm pull up. This strap should sample HIGH. There should NOT be any onboard device driving it to opposite direction during strap sampling. SPI0_IO2 and SPI0_IO3: Rising edge of RSMRST# External pull-up is required. Recommend 100K if pulled up to 3.3V or 75K if pulled up to 1.8V. This strap should sample HIGH. There should NOT be any onboard device driving it to opposite direction during strap sampling.



ID4 ID2 ID1 ID5 ID6 ID3



+3VALW_PCH



RC53



1



ID8 ID12 ID11 ID10 ID9 ID13 ID15 ID14



DN15 DK13 DM13 DN13 DJ15 DK15 DN10 DV14 DH3 DH4 DF2



GPP_E6



2 100K_0201_5%



1



ID7 GPP_E6



DJ6 DN5 DR9 DM6 DK6 DK8 DV11 DW9 DT8



2 1/20W_4.7K_5%_0201



@



SPI0_CLK SPI0_IO3 SPI0_IO2 SPI0_MISO SPI0_MOSI SPI0_CS1# SPI0_CS0# SPI0_CS2#



GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C2/SMBALERT# GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_C5/SML0ALERT# GPP_C6/SML1CLK GPP_C7/SML1DATA GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1#



GPP_E11/THC0_SPI1_CLK GPP_E2/THC0_SPI1_IO3 GPP_E1/THC0_SPI1_IO2 GPP_E12/THC0_SPI1_IO1 GPP_E13/THC0_SPI1_IO0 GPP_E10/THC0_SPI1_CS# GPP_E8/SATA_LED# GPP_E17/THC0_SPI1_INT# GPP_E6/THC0_SPI1_RST#



GPP_A5/ESPI_CLK GPP_A3/ESPI_IO3/SUSACK# GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK GPP_A1/ESPI_IO1 GPP_A0/ESPI_IO0 GPP_A4/ESPI_CS# GPP_A6/ESPI_RESET#



PCH_SML1_CLK PCH_SML1_DATA PCH_SML1_ALERT_N



DN53 DJ53 DH50 DP50 DP52 DK52 DL50



ESPI_CLK_R RC55 2 1 1/20W_49.9_1%_0201 ESPI_IO3_R RC56 1 2 1/20W_15_5%_0201 ESPI_IO2_R RC57 1 2 1/20W_15_5%_0201 ESPI_IO1_R RC59 1 2 1/20W_15_5%_0201 ESPI_IO0_R RC61 1 2 1/20W_15_5%_0201 ESPI_CS_N_R RC63 1 2@ LPC_ESPI_RST_N 0_0201_5%



D



LPC_ESPI_CLK [79] LPC_ESPI_IO3 [79] LPC_ESPI_IO2 [79] LPC_ESPI_IO1 [79] LPC_ESPI_IO0 [79] LPC_ESPI_CS_N[79] LPC_ESPI_RST_N [79] +3VALW_PCH RPC1



PCH_SML0_CLK PCH_SML0_DATA



1 2



PCH_SML0_ALERT_N



4 2.2K_0404_4P2R_5% 3



RC67 2



1



@



1/20W_4.7K_5%_0201



GPP_C5(PCH_SML0_ALERT#): Rising edge of RSMRST# This signal has a 20K+/-30% internal pull-down. 0 = Enable eSPI. (Default) 1 = Disable eSPI. Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 2. This signal is in the primary well



@



+3VALW_PCH



+3VS



+3VS PCH_SMB_ALERT_N



100K_0201_5% 4 3



2 5P_50V_B_NPO_0402 RPC2 2.2K_0404_4P2R_5%



QC4A 2N7002KDWH_SOT363-6



PCH_SMB_CLK



6



1



SMB_CLK_S1 G



5



[25]



QC4B 4



SMB_DATA_S1 [25]



D



3



S



PCH_SMB_DATA



1 1/20W_4.7K_5%_0201 C



RPC9 2.2K_0404_4P2R_5%



D



100K for 3.3V Signaling Mode 75K for 1.8V Signaling Mode



2



RC73



GPP_C2(PCH_SMB_ALERT#): This signal is used to wake the system or generate SMI#. External Pull-up resistor is required.Rising edge of RSMRST# This signal has a 20K+/-30% internal pull-down. 0 = Disable Intel ME Crypto Transport Layer Security (TLS) cipher suite (no confidentiality). (Default) 1 = Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality). Must be pulled up to support Intel AMT with TLS. Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 2. This signal is in the primary well.



1 2



1 2



EMC_NS@ Follow PDG P191 Glitch Free Requirements: Cap or pull-down resistor is required



2



2 1



DK17 DJ17 CY50



DIMM



eSPI operates at 1.8V only



G



1



PCH_SML0_CLK PCH_SML0_DATA PCH_SML0_ALERT_N



CL_CLK CL_DATA CL_RST#



C



CC1



DK19 DM17 DN17



GPP_F11/THC1_SPI2_CLK GPP_F15/GSXSRESET#/THC1_SPI2_IO3 GPP_F14/GSXDIN/THC1_SPI2_IO2 GPP_F13/GSXSLOAD/THC1_SPI2_IO1 GPP_F12/GSXDOUT/THC1_SPI2_IO0 GPP_F16/GSXCLK/THC1_SPI2_CS# GPP_F18/THC1_SPI2_INT# GPP_F17/THC1_SPI2_RST#



+3VALW_PCH RC65



PCH_SMB_CLK PCH_SMB_DATA PCH_SMB_ALERT_N



TGLLAKE-U_BGA1449



GPP_E6: JTAG ODT Disable Rising edge of RSMRST# This strap does not have an internal pull-up or pull-down. External pull-up is recommended 0=> JTAG ODT is disabled 1=> JTAG ODT is enabled



PCH_SPI0_CLK



DK21 DM19 DN19



4 3



RC54



DJ37 DG35 DJ39 DJ33 DJ35 DF35 DG37 DF39



S



1/20W_4.7K_5%_0201 2



D



2



2N7002KDWH_SOT363-6



+3VALW_PCH



2.2K change to 1k 0624



the diffrent with Base: 1.S540 PCH_SPI0_CS1_N RC74 ---4.7K;PCH_SPI0_CS0_N RC68 ---150K; S360&V14V15----Opposite 2.S540 SMBUS---NC S360&V14V15----To SO-DIMM; 3.S540 SML1---To TBT S360&V14V15----NC



+1.8VALW_PCH



RC51 1



@



2 1K_0201_5%



RC52 1



@



2 1/20W_75K_5%_0201



Glitch Free Requirements P163 B



LPC_ESPI_RST_N



LPC_ESPI_CS_N



RC62 RC75



1 1



PCH_SML1_ALERT_N



RC76



2



RC77



2



2 1K_0201_5% 2 1K_0201_5% @



1 1/20W_150K_5%_0201 1 1/20W_20K_5%_0201



GPP_B23 /SML1_ALERT# /PCHHOT#: CPUNSSC Clock Frequency Rising edge of RSMRST# This strap has a 20 kohm ± 30% internal pull-down. 0 = 38.4 MHz clock (direct from crystal) (default) 1 = 19.2 MHz clock (derived from 38.4 MHz crystal) Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 2. When used as PCHHOT# and strap low, a 150K pull-up is needed to ensure it does not override the internal pull-down strap sampling. 3. This signal is in the primary well.



Site for cap or pull-down resistor only.



RC64 1



PCH_SML1_CLK PCH_SML1_DATA



2 1/20W_75K_5%_0201



B



Board ID Table 1: 1.8V Level



BOARD ID



Board ID8



Board ID Table 1: 3.3V Level



+3VALW_PCH



@ RC251 100K_0201_5% 2 1



Board ID2



Board ID3 ID8 ID9 ID10 ID11 ID12 ID13 ID14 ID15



Board ID4



Board ID5



@ RC252 100K_0201_5% 2 1



@ RC249 100K_0201_5% 2 1 @ RC250 100K_0201_5% 2 1



OPT18@ RC247 100K_0201_5% 2 1 UMAorN17@ RC248 100K_0201_5% 2 1



OPT17@ RC245 100K_0201_5% 2 1 UMAorN18@ RC246 100K_0201_5% 2 1



@ RC243 100K_0201_5% 2 1 @ RC244 100K_0201_5% 2 1



@ RC241 100K_0201_5% 2 1



Board ID1



@ RC242 100K_0201_5% 2 1



@ RC239 100K_0201_5% 2 1 @ RC240 100K_0201_5% 2 1



@ RC237 100K_0201_5% 2 1



ID1 ID2 ID3 ID4 ID5 ID6 ID7



@ RC238 100K_0201_5% 2 1



RC260 100K_0201_5% 2 1 FP@ RC268 100K_0201_5% 2 1 NFP@



RC259 100K_0201_5% 2 1 @ RC267 100K_0201_5% 2 1 @



RC258 100K_0201_5% 2 1 @ RC266 100K_0201_5% 2 1 @



RC257 100K_0201_5% 2 1 @ RC265 100K_0201_5% 2 1 @



RC256 100K_0201_5% 2 1 @ RC264 100K_0201_5% 2 1 @



RC255 100K_0201_5% 2 1 TS@ RC263 100K_0201_5% 2 1 NTS@



A



RC262 100K_0201_5% 2 1 S360@



RC254 100K_0201_5% 2 1 V14V15@



+1.8VALW_PCH



Board ID6



Board ID7



GPP_E1



GPP_E2



GPP_E10 H GPP_E11 L



0



S360



1



V14V15



0



Non-TS



1



TS



00



FHD



***



01



UHD



No Use



10



FHD HDR



***



11



Reserved



No Use



No Use



Board ID10



No Use



Board ID11



00



13"



No Use



01



14"



***



GPP_E13 L



10



15"



***



11



17"



No Use



0



Non-FPR



Board ID12



FPR



Samsung



***



01



Micro



***



10



Hynix



***



4G



No Use



11



GPP_F13 H GPP_F14 L GPP_F15 H



No Use



01



8G



***



10



12G



***



11



16G



***



00



UMA



01



DIS



No Use Reserved for dGPU



10 Board ID13



1



GPP_F12 L



00



00



GPP_E12 H



GPP_E17



Board ID9



GPP_F11 H



Board ID14



GPP_F16 L GPP_F17



11 00



No Use



01 Reserved for Project



10 No Use



Board ID15



GPP_F18



11



GPU ID00UMA0 (RC248)0 (RC246) 01N17S0 (RC248)1 (RC425) 10N18S1 (RC247)0 (RC246) 11reserver1 (RC247)1 (RC425)



No need distinguish 14‘15’17 as PM viewpoint



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



A



4



3



2



Document Number



Rev 0.1



SPI/ESPI/SMB/CL Tuesday, November 10, 2020 1



Sheet



11



of



111



5



4



3



2



1



+3VALW_PCH



D



TP



UC1F 6 OF 21



PCH_WLAN_PERST_N PCH_BEEP PCH_WLAN_OFF_N



[47] [47] [47] [47]



PCH_TS_INT_N PCH_TS_STOP PCH_TS_RST VCC_TS_ON



PCH_WLAN_PERST_N PCH_BEEP PCH_WLAN_OFF_N



2 0_0201_5% PCH_TS_INT_N_RCY49 2 0_0201_5% PCH_TS_STOP_RCY53 2 0_0201_5% PCH_TS_RST_R CY52 DA50



RC849 1 @ RC848 1 @ RC851 1 @ VCC_TS_ON



DV21 DT21 DR21 DW21 [13,71] [79,81] [79,81] [79,81]



RC69 RC856 RC66 RC855



PCH_BT_OFF_N CAPS_LED_N Fnlk_LED_N NUM_LED_N



1 1 1 1



@ @ @ @



2 2 2 2



0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5%



@ TP14 @ TP15



TS TP



[71]



PCH_PCIE_WAKE_N_WLAN



[47] [47]



PCH_I2C0_SCL PCH_I2C0_SDA



[83] [83]



PCH_C13_BT_OFF_N DV19 PCH_CAPS_LED_N DT19 PCH_Fnlk_LED_N DR18 PCH_NUM_LED_N DU19



1 UART2_TXD DJ21 1 UART2_RXD DG23 PCH_PCIE_WAKE_N_WLANDJ19 DF21



PCH_I2C0_SCL PCH_I2C0_SDA



DV18 DW18



PCH_I2C1_SCL PCH_I2C1_SDA



PCH_I2C1_SCL PCH_I2C1_SDA



DJ23 DT18 DJ29 DJ31



C



DF29 DG29 DF25 DF27



GPP_B16/GSPI0_CLK GPP_B18/GSPI0_MOSI GPP_B17/GSPI0_MISO GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1# GPP_B15/GSPI0_CS0#



PCH_TP_INT_N GPP_D14/ISH_UART0_TXD GPP_D13/ISH_UART0_RXD GPP_D16/ISH_UART0_CTS# GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IMGCLKOUT5 GPP_B6/ISH_I2C0_SCL GPP_B5/ISH_I2C0_SDA



GPP_B20/GSPI1_CLK GPP_B22/GSPI1_MOSI GPP_B21/GSPI1_MISO GPP_B19/GSPI1_CS0#



GPP_B8/ISH_I2C1_SCL GPP_B7/ISH_I2C1_SDA



GPP_C9/UART0_TXD GPP_C8/UART0_RXD GPP_C11/UART0_CTS# GPP_C10/UART0_RTS#



GPP_B10/I2C5_SCL/ISH_I2C2_SCL GPP_B9/I2C5_SDA/ISH_I2C2_SDA GPP_E16/ISH_GP7 GPP_E15/ISH_GP6 GPP_D18/ISH_GP5 GPP_D17/ISH_GP4 GPP_D3/ISH_GP3/BK3/SBK3 GPP_D2/ISH_GP2/BK2/SBK2 GPP_D1/ISH_GP1/BK1/SBK1 GPP_D0/ISH_GP0/BK0/SBK0



GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C21/UART2_TXD GPP_C20/UART2_RXD GPP_C23/UART2_CTS# GPP_C22/UART2_RTS#



GPP_RCOMP GPP_T3 GPP_T2



GPP_C17/I2C0_SCL GPP_C16/I2C0_SDA



GPP_U5 GPP_U4



GPP_C19/I2C1_SCL GPP_C18/I2C1_SDA



RC99



1



@



2



100K_0201_5%



PCH_ECLPM_BREAK



2



100K_0201_5%



PCH_WLAN_PERST_N



@



PCH_ECLPM_BREAK FB_GC6_EN_R GPU_EVENT_N



2 0_0201_5%



+3VS



[79] [32,35] [32]



UART2_TXD UART2_RXD



RC87 1 RC89 1



2 1/20W_49.9K_1%_0201 2 1/20W_49.9K_1%_0201



DB45 DB44 +3VS CY39 DB47



PXS_PWREN_R PXS_RST_N_R



RC8041 RC8051



@ @



2 0_0402_5% 2 0_0402_5%



DD47 DD44



DGPU_PWROK_R RC8061 1.0VGS_1.35VGSPG_R RC8141



@ @



2 0_0402_5% 2 0_0201_5%



DJ8 DR7 DR24 DU25 DV31 DU31 DT27 DV27



FPR_RESET FPR_DELINK



@ @



2 0_0201_5% 2 0_0201_5%



DR51



RC88 1 RC2931



PXS_PWREN PXS_RST_N



[35] [32]



DGPU_PWROK 1.0VGS_1.35VGSPG



[35,102] [103]



FP_RESETN_R FPR_DELINK_R



TS



RPC5



PCH_I2C0_SDA PCH_I2C0_SCL PCH_TS_INT_N



1 2 RC850



1



4 3 2.2K_0404_4P2R_5% 2 10K_0201_5%



[65] [65,79] +3VS FPR_DELINK



RC83 1



@



2 2.2K_0402_5%



FPR_RESET



RC8641



@



2 10K_0201_5%



GPP_RCOMP



DN33 DT35 DG17 DG19



RC97 1/20W_200_1%_0201



+3VS PCH_CAPS_LED_N RC862



1



2 10K_0201_5%



PCH_NUM_LED_N



RC853



1



2 10K_0201_5%



PCH_Fnlk_LED_N



RC811



1



2 10K_0201_5%



PXS_PWREN_R



RC807



1 OPT@



2 10K_0201_5%



RC808



1 OPT_NS@ 2 10K_0201_5%



RC809



1 OPT_NS@ 2 10K_0201_5%



RC810



1 OPT@



FB_GC6_EN_R



RC812



1 OPT_NS@ 2 10K_0201_5%



GPU_EVENT_N



RC813



1 OPT@



RC817



1 OPT_NS@ 2 10K_0201_5%



PXS_RST_N



CC801



1



DGPU_PWROK_R



RC8201 UMA@ 2 10K_0201_5%



C



+3VS



the diffrent with Base: 1.S540 NO Touch scrren &I2C for touch, S360&V14V15 use 2.S540 has Tof& &I2C for TOF;S360&V14V15 no use 3.S540 NO Fingerprinter, S360&V14V15 use; 4.S540 NO num&fnlink LED, S360&V14V15 use 5.S540 DD44 PIN----1.0VGS_1.25VGSPG, S360&V14V15 DD44 PIN----1.0VGS_1.35VGSPG 6.S540 DV31 PIN----PCH_LID_0D_SW_N,S360&V14V15---NC 7.S540 DJ8 PIN----ISH_GP7_ITS_R,S360&V14V15---FPR_RESET 8.S540 DR7 PIN----NC,S360&V14V15---FPR_DELINK



+3VS PXS_RST_N_R



2 10K_0201_5%



+3VS RC1011



@



2 1/20W_4.7K_5%_0201



PCH_BEEP



GPP_B14(PCH_BEEP): Rising edge of PCH_PWROK The strap has a 20 kohm ± 30% internal pull-down. 0 = Disable Top Swap mode. (Default) 1 = Enable Top Swap mode. This inverts an address on access to SPI and firmware hub, so the processor believes it fetches the alternate boot block instead of the original boot-block. PCH will invert A16 (default) for cycles going to the upper two 64-KB blocks in the FWH or the appropriate address lines (A16, A17, or A18) as selected in Top Swap Block size soft strap. Notes: 1. The internal pull-down is disabled after PCH_PWROK is high. 2. Software will not be able to clear the Top Swap bit until the system is rebooted. 3. The status of this strap is readable using the Top Swap bit (Bus0, Device31, Function0, offset DCh, bit4). 4. This signal is in the primary well.



B



1



GPP_H9/I2C4_SCL/CNV_MFUART2_TXD GPP_H8/I2C4_SDA/CNV_MFUART2_RXD



+3VS 1



D



2.2K_0404_4P2R_5% 2 10K_0201_5% RC82 1



GPP_H7/I2C3_SCL GPP_H6/I2C3_SDA



TGLLAKE-U_BGA1449



RC98



4 3



Need support wake by touch pad



GPP_H5/I2C2_SCL GPP_H4/I2C2_SDA



@



+3VALW_PCH



DR27 DW27 PCH_ECLPM_BREAK DV25 PCH_FB_GC6_EN_R RC854 DT25 GPU_EVENT_N



1 2



1



TS IO



GPP_B18



[71] [66] [71]



DC53 DA51 DC49 DC50 DC52



2



PCH_TP_INT_N



[79,83] PCH_TP_INT_N



RPC4



PCH_I2C1_SCL PCH_I2C1_SDA



RC102



1



@



2 1/20W_4.7K_5%_0201



RC103



1



@



2 1/20W_20K_5%_0201



GPP_B18 +3VS



GPP_B18:Rising edge of PCH_PWROK The signal has a weak internal pull-down. 0 = Disable No Reboot mode. (Default) 1 = Enable No Reboot mode (PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP. Notes: 1. The internal pull-down is disabled after PCH_PWROK is high. 2. This signal is in the primary well.



2 10K_0201_5%



B



2 0.01U_6.3V_K_X7R_0201 OPT@



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



I2C/ISH/UART/GPIO Tuesday, November 10, 2020 1



Sheet



12



of



110



5



4



3



2



1



UC1G 7 OF 21



D



[66] [66] [66] [66]



RC111 1 RC109 1 RC110 1



HDA_BITCLK_AUDIO HDA_SYNC_AUDIO HDA_SDOUT_AUDIO HDA_SDIN0



PCH_HDA_BCLK PCH_HDA_SYNC PCH_HDA_SDO HDA_SDIN0



2 1/20W_33_5%_0201 2 1/20W_33_5%_0201 2 1/20W_33_5%_0201 @ TP109



[71]



RC113 1



CNVI_RF_RESET_N



RC861 1



PCH_BT_OFF_N



RC117



HDA_RST_N



1



DV41 DL53 PCH_CNVI_RF_RESET_NDG51 DG50



2 1/20W_33_5%_0201 PCH_CNVI_MODEM_CLKREQ DL49 DL52



RC116 1



[71] CNVI_MODEM_CLKREQ [12,71]



2 1/20W_33_5%_0201



DR38 DU37 DT37 DV37



@



1



PCH_A13_BT_OFF_N



2 0_0201_5%



2 1/20W_200_1%_0201



SNDW_RCOMP



DH49 DF33



GPP_R0/HDA_BCLK/I2S0_SCLK GPP_R1/HDA_SYNC/I2S0_SFRM GPP_R2/HDA_SDO/I2S0_TXD GPP_R3/HDA_SDI0/I2S0_RXD



DW15 DW24



GPP_F8/I2S_MCLK2_INOUT GPP_D19/I2S_MCLK1



DG41 DT38 DV38 DW38



GPP_A23/I2S1_SCLK GPP_R7/I2S1_SFRM GPP_R6/I2S1_TXD GPP_R5/HDA_SDI1/I2S1_RXD



GPP_R4/HDA_RST# GPP_A7/I2S2_SCLK/DMIC_CLK_A0 GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0 GPP_A10/I2S2_RXD/DMIC_DATA1



DN31 DM31



GPP_S6/SNDW3_CLK/DMIC_CLK_A0 GPP_S7/SNDW3_DATA/DMIC_DATA0



GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1 GPP_A11/PMC_I2C_SDA/I2S3_SCLK



PCH_DMIC_CLK0 PCH_DMIC_DAT0



[47] [47]



DK33 DK31



GPP_S4/SNDW2_CLK/DMIC_CLK_A1 GPP_S5/SNDW2_DATA/DMIC_DATA1



GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0



DW35 DV35



GPP_S2/SNDW1_CLK/DMIC_CLK_B0 GPP_S3/SNDW1_DATA/DMIC_CLK_B1



SNDW_RCOMP



D



DT32 DR35



GPP_S0/SNDW0_CLK GPP_S1/SNDW0_DATA +1.8VALW_PCH 1



TGLLAKE-U_BGA1449 @ RC107 1/20W_4.7K_5%_0201 PCH_HDA_SDO



RC108 1



C



2



C



2



ME_FLASH



@



[79]



the diffrent with Base: 0_0402_5% GPP_R2(HDA_SDO_R): 1.S540 PCH_DMIC_CLK0 This signal has a 20K ±30% internal pull-down. 0 = Enable security measures defined in the Flash Descriptor. (Default) 2.S540 PCH_HDA_SDI no 1 = Disable Flash Descriptor Security (override). This strap should only be asserted high using external Pull-up in manufacturing/debug environments ONLY. Notes: 1. The internal pull-down is disabled after PCH_PWROK is high. 2. This signal is in the primary well.



EMC PCH_HDA_BCLK



PCH_HDA_SDO



HDA_SDIN0



CC13 Stuff,S360&V14V15---NC: EMC reserve,S360&V14V15 reserve CC8



PCH_HDA_SYNC



1



2



CC2 0.1U_6.3V_K_X5R_0201 EMC_NS@



PCH_DMIC_CLK0 1



2



1



2



CC15 2P_25V_C_NPO_0201 EMC_NS@



PCH_DMIC_DAT0



CC13 100P 25V J NPO 0201 EMC_NS@



1



2



2



CC8 27P_0402_50V8J EMC_NS@



1



2



2



RC104



2



@



1 100K_0201_5%



PCH_HDA_BCLK



RC105



2



@



1 100K_0201_5%



HDA_SDIN0



Glitch Free Requirements: Pull-down resistor to ensure the stability of the signal during platform bootup



B



1



1 1/20W_75K_5%_0201 PCH_CNVI_RF_RESET_N



RC106



B



Option 1:Cap Implementation NA for 3.3v Ramp Rate from 5-50ms NA for 3.3V Ramp Rate Less than 5ms CC3 0.1U_6.3V_K_X5R_0201 EMC_NS@



Option 2:Pull-down Resistor Implementation NA for 3.3V Signaling Mode 75K for 1.8V Signaling Mode



PCH_CNVI_MODEM_CLKREQ 1



CC14 33P_50V_J_NPO_0201 EMC_NS@



2



CC16 33P_50V_J_NPO_0201 EMC_NS@



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



AUDIO



Tuesday, November 10, 2020



Sheet 1



Rev 0.1 13



of



110



5



4



3



D



2



1



D



UC1I 9 OF 21



BT7 BT8 CE2 CE1



HDD



LAN



[78] [78]



[60] [60] [60] [60]



PCIE_PTX_C_DRX10_P PCIE_PTX_C_DRX10_N [78] [78]



WLAN



SSD C



[71] [71] [71] [71]



SATA_PTX_DRX0_P SATA_PTX_DRX0_N SATA_PRX_DTX0_P SATA_PRX_DTX0_N V14V15@CC9111 V14V15@CC9121 PCIE_PRX_DTX10_P PCIE_PRX_DTX10_N PCIE_PTX_DRX9_P PCIE_PTX_DRX9_N PCIE_PRX_DTX9_P PCIE_PRX_DTX9_N



[63] [63] [63] [63]



PCIE_PTX_DRX8_P PCIE_PTX_DRX8_N PCIE_PRX_DTX8_P PCIE_PRX_DTX8_N



[63] [63] [63] [63]



PCIE_PTX_DRX7_P PCIE_PTX_DRX7_N PCIE_PRX_DTX7_P PCIE_PRX_DTX7_N



[63] [63] [63] [63]



PCIE_PTX_DRX6_P PCIE_PTX_DRX6_N PCIE_PRX_DTX6_P PCIE_PRX_DTX6_N



[63] [63] [63] [63]



PCIE_PTX_DRX5_P PCIE_PTX_DRX5_N PCIE_PRX_DTX5_P PCIE_PRX_DTX5_N



SATA_PTX_DRX0_P SATA_PTX_DRX0_N SATA_PRX_DTX0_P SATA_PRX_DTX0_N



BT9 BV9 CF4 CF3



2 0.1u_0201_10V6KPCIE_PTX_DRX10_PBV7 2 0.1u_0201_10V6KPCIE_PTX_DRX10_N BV8 PCIE_PRX_DTX10_P CG2 PCIE_PRX_DTX10_N CG1 PCIE_PTX_DRX9_P PCIE_PTX_DRX9_N PCIE_PRX_DTX9_P PCIE_PRX_DTX9_N



BY7 BY8 CG5 CG4



PCIE_PTX_DRX8_P PCIE_PTX_DRX8_N PCIE_PRX_DTX8_P PCIE_PRX_DTX8_N



CB8 CB7 CK5 CK4



PCIE_PTX_DRX7_P PCIE_PTX_DRX7_N PCIE_PRX_DTX7_P PCIE_PRX_DTX7_N



CD9 CD8 CK1 CK2



PCIE_PTX_DRX6_P PCIE_PTX_DRX6_N PCIE_PRX_DTX6_P PCIE_PRX_DTX6_N



CG8 CG7 CL4 CL3



PCIE_PTX_DRX5_P PCIE_PTX_DRX5_N PCIE_PRX_DTX5_P PCIE_PRX_DTX5_N



CJ8 CJ7 CN2 CN1 CR8 CR7 CN5 CN4



TYPE-C USB3.0



USB3.0 MB PORTB



[53] [53] [53] [53]



USB30_TX3_P USB30_TX3_N USB30_RX3_P USB30_RX3_N



[53] [53] [53] [53]



USB30_TX2_P USB30_TX2_N USB30_RX2_P USB30_RX2_N



[57] [57] [57] [57]



USB30_TX1_P USB30_TX1_N USB30_RX1_P USB30_RX1_N



USB30_TX3_P USB30_TX3_N USB30_RX3_P USB30_RX3_N



CU8 CU7 CT2 CT1



USB30_TX2_P USB30_TX2_N USB30_RX2_P USB30_RX2_N



CW8 CW7 CU3 CT4



USB30_TX1_P USB30_TX1_N USB30_RX1_P USB30_RX1_N



DA8 DA7 CV2 CV1



PCIE12_TXP/SATA1_TXP PCIE12_TXN/SATA1_TXN PCIE12_RXP/SATA1_RXP PCIE12_RXN/SATA1_RXN



USB2P_10 USB2N_10 USB2P_9 USB2N_9



PCIE11_TXP/SATA0_TXP PCIE11_TXN/SATA0_TXN PCIE11_RXP/SATA0_RXP PCIE11_RXN/SATA0_RXN



USB2P_8 USB2N_8 USB2P_7 USB2N_7



PCIE10_TXP PCIE10_TXN PCIE10_RXP PCIE10_RXN



USB2P_6 USB2N_6



PCIE9_TXP PCIE9_TXN PCIE9_RXP PCIE9_RXN



USB2P_5 USB2N_5 USB2P_4 USB2N_4



PCIE8_TXP PCIE8_TXN PCIE8_RXP PCIE8_RXN



USB2P_3 USB2N_3 USB2P_2 USB2N_2



PCIE7_TXP PCIE7_TXN PCIE7_RXP PCIE7_RXN



USB2P_1 USB2N_1



PCIE6_TXP PCIE6_TXN PCIE6_RXP PCIE6_RXN



GPP_E0/SATAXPCIE0/SATAGP0 GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM GPP_E9/USB_OC0# GPP_A16/USB_OC3#/I2S4_SFRM



PCIE5_TXP PCIE5_TXN PCIE5_RXP PCIE5_RXN



GPP_E5/DEVSLP1 GPP_E4/DEVSLP0 GPP_H15/M2_SKT2_CFG3 GPP_H14/M2_SKT2_CFG2 GPP_H13/M2_SKT2_CFG1 GPP_H12/M2_SKT2_CFG0



PCIE4_TXP/USB31_4_TXP PCIE4_TXN/USB31_4_TXN PCIE4_RXP/USB31_4_RXP PCIE4_RXN/USB31_4_RXN



PCIE_RCOMP_P PCIE_RCOMP



PCIE3_TXP/USB31_3_TXP PCIE3_TXN/USB31_3_TXN PCIE3_RXP/USB31_3_RXP PCIE3_RXN/USB31_3_RXN



USB_VBUSSENSE USB_ID USB2_COMP



PCIE2_TXP/USB31_2_TXP PCIE2_TXN/USB31_2_TXN PCIE2_RXP/USB31_2_RXP PCIE2_RXN/USB31_2_RXN



RSVD_BSCAN



CV4 CY3



USB20_10_P USB20_10_N



BT



USB20_10_P [71] USB20_10_N [71]



DD5 DD4 CW9 DA9 DD1 DD2



USB20_7_P USB20_7_N



DA1 CPU_USB20_6_P DA2 CPU_USB20_6_N DA12 DA11



USB20_5_P USB20_5_N



DC8 DC7



USB20_4_P USB20_4_N



USB20_7_P [65] USB20_7_N [65]



Finger Print



1 S360@ 2 0_0201_5% RC2817 1 S360@ 2 0_0201_5% RC2818 USB20_5_P [47] USB20_5_N [47] USB20_4_P [57] USB20_4_N [57]



DB4 DB3



USB20_6_P [78] USB20_6_N [78]



Card reader



Camera USB3.0 MB PORTB



USB3.0 Normal



Touch Screen Use I2C



DA5 DA4



USB20_2_P USB20_2_N



DC11 DC9



USB20_1_P USB20_1_N



USB20_2_P USB20_2_N



[53] [53]



USB20_1_P USB20_1_N



[78] [78]



TYPE-C USB2.0 USB2.0



DP4 DF41SSD_SATA_PCIE_DET1_N DD8 DJ45



USB_OC0_N USB_OC3_N



DN6 DG8



PCH_SATA_DEVSLP1



SSD_SATA_PCIE_DET1_N 1



RC60



@



2 0_0201_5%



TYPEC_OCP_N



[53]



PCH_SATA_DEVSLP1



[63] C



Type-c Power Switch OC PIN [63]



Native OD output



DN29 DK29 DT31 DR32 DV9 DT9



PCIE_RCOMPP PCIE_RCOMPN



RC1181



2 1/20W_100_1%_0201



DC12 DF1 DE1



USB2_VBUSSENSE USB2_ID USB2_COMP



RC1192 RC1202 RC1211



1 10K_0201_5% 1 10K_0201_5% 2 1/20W_113_1%_0201



E3



RSVD_BSCAN



1



TP85 @



the diffrent with Base: 1.S540 NO Fingerprinter&HDD&LAN, S360&V14V15 use; 4.S540 Has TBT,S360 TYPE-C USB3.0 Only 8.S540 DD8&DJ45 PIN----For TYPE-C OCP,S360&V14V15 DD8----For TYPE-C,DJ45-pull up



PCIE1_TXP/USB31_1_TXP PCIE1_TXN/USB31_1_TXN PCIE1_RXP/USB31_1_RXP PCIE1_RXN/USB31_1_RXN TGLLAKE-U_BGA1449 @



UC1H



B



B 8 OF 21



DGPU



[28] [28] [28] [28]



PCIE4_CTX_C_GRX3_P PCIE4_CTX_C_GRX3_N PCIE4_CRX_GTX3_P PCIE4_CRX_GTX3_N



[28] [28] [28] [28]



PCIE4_CTX_C_GRX2_P PCIE4_CTX_C_GRX2_N PCIE4_CRX_GTX2_P PCIE4_CRX_GTX2_N



PCIE4_CTX_C_GRX3_P CC9041 PCIE4_CTX_C_GRX3_N CC9031 PCIE4_CRX_GTX3_P PCIE4_CRX_GTX3_N



2 OPT@ 0.22U_6.3V_K_X5R_0201PCIE4_CTX_GRX3_P P5 2 OPT@ 0.22U_6.3V_K_X5R_0201PCIE4_CTX_GRX3_N P7 N1 N2



PCIE4_CTX_C_GRX2_P CC9021 PCIE4_CTX_C_GRX2_N CC9011 PCIE4_CRX_GTX2_P PCIE4_CRX_GTX2_N



2 OPT@ 0.22U_6.3V_K_X5R_0201PCIE4_CTX_GRX2_P T5 2 OPT@ 0.22U_6.3V_K_X5R_0201PCIE4_CTX_GRX2_N T7 R1 R2



PCIE4_TX_P_3 PCIE4_TX_N_3 PCIE4_RX_P_3 PCIE4_RX_N_3



PCIE4_TX_P_1 PCIE4_TX_N_1 PCIE4_RX_P_1 PCIE4_RX_N_1



PCIE4_TX_P_2 PCIE4_TX_N_2 PCIE4_RX_P_2 PCIE4_RX_N_2



PCIE4_TX_P_0 PCIE4_TX_N_0 PCIE4_RX_P_0 PCIE4_RX_N_0 PCIE4_RCOMP_P PCIE4_RCOMP



V5 V7 T1 T2



PCIE4_CTX_GRX1_P CC9101 PCIE4_CTX_GRX1_N CC9091



2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CTX_C_GRX1_P 2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CTX_C_GRX1_N PCIE4_CRX_GTX1_P PCIE4_CRX_GTX1_N



Y5 Y7 V1 V2



PCIE4_CTX_GRX0_P CC9081 PCIE4_CTX_GRX0_N CC9071



2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CTX_C_GRX0_P 2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CTX_C_GRX0_N PCIE4_CRX_GTX0_P PCIE4_CRX_GTX0_N



Y12 PCIE4_RCOMP_P V12 PCIE4_RCOMP_N RC126



2



PCIE4_CTX_C_GRX1_P PCIE4_CTX_C_GRX1_N PCIE4_CRX_GTX1_P PCIE4_CRX_GTX1_N



[28] [28] [28] [28]



PCIE4_CTX_C_GRX0_P PCIE4_CTX_C_GRX0_N PCIE4_CRX_GTX0_P PCIE4_CRX_GTX0_N



[28] [28] [28] [28]



1 1/20W_2.2K_5%_0201



V12



This RCOMP should be connected even if the CPU PCIe interface is not used TGLLAKE-U_BGA1449 @ +3VALW_PCH PCH_SATA_DEVSLP1



RC127



1



RC122



1



@



2 10K_0201_5%



+3VALW_PCH @ USB_OC0_N



2 10K_0201_5%



VCC_3P3_1P8_USB_OC



A



USB_OC3_N



RC125



1



2 10K_0201_5%



SSD_SATA_PCIE_DET1_N



RC271



1



2 10K_0201_5%



A



+1.8VALW_PCH



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



PCIE/USB/SATA Tuesday, November 10, 2020 1



Sheet



14



of



110



5



4



3



2



1



+1.8VALW_PCH UC1J



D



10 OF 21



D22 B22 E22 D20 A20 B20 B18 A18 D18 E18 C16 D16 D15 E15 A15 B15 L18 N18 L20 N20 G20 H20



C



H16 G16 G18 H18 L16 N16 G14 H14 L14 N14 2 RC139 1 1/20W_150_1%_0201



CSI_COMPK14 DK25 DM25 DN25 DJ25 DR30



B



CSI_F_DP_1 CSI_F_DN_1 CSI_F_DP_0 CSI_F_DN_0 CSI_F_CLK_P CSI_F_CLK



CNVI_WT_D1P CNVI_WT_D1N CNVI_WT_D0P CNVI_WT_D0N CNVI_WT_CLKP CNVI_WT_CLKN



CSI_E_DP_1/CSI_F_DP_2 CSI_E_DN_1/CSI_F_DN_2 CSI_E_DP_0/CSI_F_DP_3 CSI_E_DN_0/CSI_F_DN_3 CSI_E_CLK_P CSI_E_CLK



CNVI_WR_D1P CNVI_WR_D1N CNVI_WR_D0P CNVI_WR_D0N CNVI_WR_CLKP CNVI_WR_CLKN



CSI_C_DP_2 CSI_C_DN_2 CSI_C_DP_3 CSI_C_DN_3 CSI_C_DP_1 CSI_C_DN_1 CSI_C_DP_0 CSI_C_DN_0 CSI_C_CLK_P CSI_C_CLK



CNVI_WT_RCOMP GPP_F3/CNV_RGI_RSP/UART0_CTS# GPP_F2/CNV_RGI_DT/UART0_TXD GPP_F1/CNV_BRI_RSP/UART0_RXD GPP_F0/CNV_BRI_DT/UART0_RTS# GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ GPP_F6/CNV_PA_BLANKING GPP_F4/CNV_RF_RESET#



DK47 DM47 DN49 DR49 DN45 DN47



CNV_WT_D1_P CNV_WT_D1_N CNV_WT_D0_P CNV_WT_D0_N CNV_WT_CLK_P CNV_WT_CLK_N



DU43 DV43 DR44 DT43 DV44 DW44



CNV_WR_D1_P CNV_WR_D1_N CNV_WR_D0_P CNV_WR_D0_N CNV_WR_CLK_P CNV_WR_CLK_N



DN51



CNV_WT_RCOMP



RC134 1 CNVI@ 2 1/20W_150_1%_0201



DJ13 DG13 DF15 DF17



CNVI_RGI_RSP CNVI_RGI_DT_R CNVI_BRI_RSP CNVI_BRI_DT_R



RC135 1



@



2 0_0201_5%



RC136 1



@



2 0_0201_5%



CNV_WT_D1_P CNV_WT_D1_N CNV_WT_D0_P CNV_WT_D0_N CNV_WT_CLK_P CNV_WT_CLK_N



[71] [71] [71] [71] [71] [71]



CNV_WR_D1_P CNV_WR_D1_N CNV_WR_D0_P CNV_WR_D0_N CNV_WR_CLK_P CNV_WR_CLK_N



[71] [71] [71] [71] [71] [71]



CNVI_RGI_RSP



RC130



1



@



2 1/20W_20K_5%_0201



CNVI_BRI_RSP



RC131



1



@



2 1/20W_20K_5%_0201



D



+1.8VALW_PCH



CNVI_BRI_DT_R



CNVI_RGI_RSP CNVI_RGI_DT CNVI_BRI_RSP CNVI_BRI_DT



[71] [71] [71] [71]



DJ10 DV15 DK10



CSI_B_DP_1 CSI_B_DN_1 CSI_B_DP_0 CSI_B_DN_0 CSI_B_CLK_P CSI_B_CLK



RC58



1



@



2



RC138



1



@



2 1/20W_20K_5%_0201



100K_0201_5%



GPP_F0 /CNV_BRI_DT /UART0_RTS# XTAL Frequency Selection, Rising edge of RSMRST# This strap has a 20 kohm ± 30% internal pull-down. This strap should not be pulled high since 24 MHz crystal is not supported on the PCH. 0 = 38.4 MHz (default) 1 = 24 MHz Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts. 2. This signal is in the primary well.



PU at M.2 side Follow CNVI Design Guide Confirm with Intel CNVI_RGI_DT_R



CSI_B_DP_2 CSI_B_DN_2 CSI_B_DP_3 CSI_B_DN_3



C



+1.8VALW_PCH



RC132



1



@



2 100K_0201_5%



RC133



1



@



2 1/20W_4.7K_5%_0201



GPP_F2 /CNV_RGI_DT /UART0_TXD: M.2 CNVI MODES, Rising edge of RSMRST# A weak external pull-up is required. 0 = Integrated CNVi enabled. 1 = Integrated CNVi disabled. Note: When a RF companion chip is connected to the PCH CNVi interface, the device internal pulldown resistor will pull the strap low to enable CNVi interface.



CSI_RCOMP GPP_H23/IMGCLKOUT4 GPP_H22/IMGCLKOUT3 GPP_H21/IMGCLKOUT2 GPP_H20/IMGCLKOUT1 GPP_D4/IMGCLKOUT_0/BK4/SBK4 TGLLAKE-U_BGA1449



B



@



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



CSI-2/CNVI



Tuesday, November 10, 2020



Sheet 1



15



Rev 0.1 of



110



5



4



3



2



1



+3VALW_PCH



CLKOUT_PCIE_P /N [6,5,4, 2,1] = Support up to PCIe Gen3 CLKOUT_PCIE_P /N [3, 0] = Support up to PCIe Gen4 UC1K



WLAN_CLKREQ_N



RC140



1



@



2 10K_0201_5%



SSD_CLKREQ1_N



RC141



1



@



2 10K_0201_5%



11 OF 21



D



BW1 BW2



CLKOUT_PCIE_P6 CLKOUT_PCIE_N6



CB2 CB1



CLKOUT_PCIE_P5 CLKOUT_PCIE_N5



BW4 BW5 [78] [78]



C



CLK_PCIE_LAN_P CLK_PCIE_LAN_N



CLK_PCIE_LAN_P CLK_PCIE_LAN_N



[71] [71]



CLK_PCIE_WLAN_P CLK_PCIE_WLAN_N



[63] [63]



CLK_PCIE_SSD_P CLK_PCIE_SSD_N



[28] [28]



CLK_PCIE_GPU_P CLK_PCIE_GPU_N



1/20W_60.4_1%_0201



2



CLKOUT_PCIE_P4 CLKOUT_PCIE_N4



CL7 CL8



CLK_PCIE_WLAN_P CLK_PCIE_WLAN_N



CB4 CB5



CLK_PCIE_SSD_P CLK_PCIE_SSD_N



BY4 BY3



CLK_PCIE_GPU_P CLK_PCIE_GPU_N



CN7 CN8



GPP_F19/SRCCLKREQ6# GPP_H11/SRCCLKREQ5# GPP_H10/SRCCLKREQ4# GPP_D8/SRCCLKREQ3# GPP_D7/SRCCLKREQ2# GPP_D6/SRCCLKREQ1# GPP_D5/SRCCLKREQ0# XTAL_OUT XTAL_IN



CLKOUT_PCIE_P3 CLKOUT_PCIE_N3



GPD8/SUSCLK



CLKOUT_PCIE_P2 CLKOUT_PCIE_N2



RTCX2 RTCX1



CLKOUT_PCIE_P1 CLKOUT_PCIE_N1



RTCRST# SRTCRST#



DU14 DF23 DG25 DT24 DT30 DV30 DW30



LAN_CLKREQ_N WLAN_CLKREQ_N SSD_CLKREQ1_N GPU_CLKREQ_N



DM1 DL1



XTAL_PCH_38P4M_OUT XTAL_PCH_38P4M_IN



DW41



SUSCLK



DT47 DR47



RTC_X2 RTC_X1



DN37 DK37



RTC_RST_N SRTC_RST_N



+3VS LAN_CLKREQ_N WLAN_CLKREQ_N SSD_CLKREQ1_N GPU_CLKREQ_N



[78] [71] [63] [28]



SUSCLK



[71]



LAN_CLKREQ_N



RC865



1



2 10K_0201_5%



GPU_CLKREQ_N



RC270



1



2 10K_0201_5%



RC142 1



SUSCLK



RTC_X2 RC145 1



2



@ 1



XTAL_PCH_38P4M_OUT



RC146



4



3



1 LC1



2



1



1 CC19 9P_50V_B_NPO_0402



2



CC20 9P_50V_B_NPO_0402



XTAL_PCH_38P4M_IN_R



2 0_0402_5%



EXC24CH500U_4P



1



C



1



TGLLAKE-U_BGA1449



4



2



32.768KHZ 9PF 202934-PG14



@



RC144



2 10M_0402_5%



YC1 1



XCLK_BIASREF



XTAL_PCH_38P4M_IN



2 1K_0201_5%



@



RTC_X1



CLKOUT_PCIE_P0 CLKOUT_PCIE_N0



1 RC143 XCLK_BIASREFDJ5



D



VCCRTC 3



1



2



EMC_NS@ @ 2 0_0402_5%



CC21 1U_6.3V_K_X5R_0201



RC148 1



2 1/20W_20K_1%_0201 2



RTC_RST_N



RC150 1



2 1/20W_20K_1%_0201



SRTC_RST_N



XTAL_PCH_38P4M_OUT_R



1



RC149 1



@



2 0_0201_5%



EC_RTC_RST_N [79]



CC24 1U_6.3V_K_X5R_0201



2 XTAL_PCH_38P4M_IN_R



B



RC147 1



XTAL_PCH_38P4M_OUT_R



2 200K_0402_1%



RTC_RST_N



CC4 1



EMC_NS@ 2 0.01U_6.3V_K_X7R_0201



B



YC2 4 1 CC22 10P_0402_50V8J



NC1 OSC1



OSC2 NC2



CMOS RESET SAVE CMOS = PU (Default) CLEAR CMOS = PD



3 2



1



ME RESET SAVE ME = PU (Default) CLEAR ME = PD



1 38.4MHZ_10PF_7R38400001



2



2



CC23 10P_0402_50V8J



the diffrent with Base: 1.S540 NO LAN, S360&V14V15 use LAN CLK&CLKREQ; 2.S540 GPU_CLKREQ_N Pull 3VS, SSD&WLAN_CLKREQ_N Pull +3VALW_PCH; S360&V14V15GPU_CLKREQ_N Pull 3VS, SSD&WLAN&LAN_CLKREQ_N Pull +3VALW_PCH A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



S360-TGL Document Number



CLOCK SIGNALS



Tuesday, November 10, 2020



Sheet 1



16



Rev 0.1 of



110



5



4



3



2



1



UC1L 12 OF 21



[79]



PCH_PM_SLP_SUS_N



PCH_PM_SLP_SUS_N



[79.84] [79]



PCH_PM_SLP_S4_N PCH_PM_SLP_S3_N



D



[79,84]



[32,63,71,78,79] [79] [79]



DV49



1PCH_PM_SLP_S5_N @ TP17 DM43 PCH_PM_SLP_S4_N DJ41 PCH_PM_SLP_S3_N DJ43 1PCH_PM_SLP_A_N @ TP18 DR41 1PCH_PM_SLP_WLAN_N DT44 @ TP108 RC1521



PM_SLP_S0_N



PLT_RST_N EC_SYS_PWROK EC_PCH_PWROK



@



2 0_0201_5% PCH_PM_SLP_S0_N PCH_PM_SLP_LAN_N



DD42 DN39 DM35 DD10 DD41 DK35 DF10 DN35



RC1541



@



PCH_RSMRST_N PCH_SYS_RESET_N 2 0_0201_5% PCH_PLT_RST_N



RC1551 RC1571



@ @



PCH_DPWROK 2 0_0201_5% SYS_PWROK 2 0_0201_5% PCH_PWROK INTRUDER_N SPI VCCIOSEL



DM37 DT49



SLP_SUS#



PROCPWRGD GPD3/PWRBTN# GPD0/BATLOW# GPD1/ACPRESENT



GPD10/SLP_S5# GPD5/SLP_S4# GPD4/SLP_S3# GPD6/SLP_A# GPD9/SPL_WLAN#



GPP_B11/PMCALERT# GPP_H18/CPU_C10_GATE# GPP_H3/SX_EXIT_HOLDOFF#



GPP_B12/SLP_S0# SLP_LAN# RSMRST# SYS_RESET# GPP_B13/PLTRST#



WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC/DSWLDO_MON GPD7



DSW_PWROK SYS_PWROK PCH_PWROK



VCCSTPWRGOOD_TCSS VCCST_PWRGD VCCST_OVERRIDE



INTRUDER# SPIVCCIOSEL



GPP_F20/EXT_PWR_GATE# GPP_F21/EXT_PWR_GATE2#



BM9 DK41 DN41 DK43



CPU_PROCPWRGD 1 PBTN_OUT_N BATLOW_N AC_PRESENT



CW40 DN27 DG31



PCH_PMC_ALERT_N CPU_C10_GATE_N SX_EXIT_HOLDOFF_N PCIE_WAKE_N_R



DK39



TP16 @ PBTN_OUT_N BATLOW_N AC_PRESENT



[79] [79] [79]



CPU_C10_GATE_N SX_EXIT_HOLDOFF_N



[84] [79]



1 V14V15@2 0_0201_5% RC2819



D



Sx Exit Holdoff Delay: Delay exit from Sx state after SLP_A# is de-asserted



PCIE_WAKE_N



[71,78,79]



DM41 PCH_LAN_WAKE_N DT41 DN43



BB_TBT_PERST_N



CE5 BP8 BP9



VCCSTPWRGOOD_TCSS VCCST_PWRGD VCCST_OVERRIDE_R



RC1561 RC1581 RC1591



@ @



2 0_0201_5% 2 1/20W_60.4_1%_0201 2 0_0201_5%



VCCST_OVERRIDE [84] EC_VCCST_PWRGD [79] VCCST_OVERRIDE [84]



DR12 DW12



TGLLAKE-U_BGA1449 @



the diffrent with Base: 1.S540 DM41 no LAN, S360&V14V15 Lan to page78; 2.1.S540 PCH_PM_SLP_WLAN_N no reserve,S360&V14V15 reserve RC186 +VCCST_CPU



Glitch Free Requirements: Pull-up resistor is required if a device is monitoring SLP_S0# before RSMRST# de-assertion 100K for 3.3V Signaling Mode 75K for 1.8V Signaling Mode



DSW_PWROK and RSMRST# are always separate power good signals [79]



EC_PCH_DPWROK_R



EC_PCH_DPWROK_R



RC1611



@



RC1601



2 0_0201_5%



PCH_DPWROK



2 10K_0201_5%



EC_VCCST_PWRGD



RC164



1



2 1K_0201_5%



PCH_SYS_RESET_N



RC167



1



2 10K_0201_5%



+3VS



+3VALW_PCH



+3VALW_PCH



RC169 10K----1K 0624



C



C



[79]



EC_RSMRST_N_R



EC_RSMRST_N_R



RC1621 RC1631



@



2 0_0201_5%



PCH_RSMRST_N



PCH_PM_SLP_S0_N



RC168



1



2



BB_TBT_PERST_N



RC184



1



2 1/20W_20K_5%_0201



PCH_PMC_ALERT_N



RC169



1



2 1K_0201_5%



PCIE_WAKE_N_R



RC170



1



2 1K_0201_5%



PCH_LAN_WAKE_N



RC171



1



PBTN_OUT_N



RC173



1



2



100K_0201_5%



BATLOW_N



RC175



1



2



100K_0201_5%



AC_PRESENT



RC176



1



2



100K_0201_5%



100K_0201_5%



2 10K_0201_5%



+VCCPDSW_3P3 +VCCPDSW_3P3 RC165



2



RC166



2



@



1 1/20W_4.7K_5%_0201



SPI VCCIOSEL



1 1/20W_4.7K_5%_0201



The VCCSPI voltage (3.3V or 1.8V) is selected via a strap on SPIVCCIOSEL； This strap sets the SPI interface signaling voltage at the rising edge of DSW_PWROK. Designers should strap this pin to match the expected interface operational voltage for CAD NOTE: their target SPI device as follows. INPUT3VSEL: 3V SELECT STRAP 0 = SPI voltage is 3.3V (4.7K ohm pull-down to GND)； LOW-> 3.3V +/-5% 1 = SPI voltage is 1.8V (4.7K ohm pull-up to VCCDSW_3P3) HIGH->3.0V +/-5%



VCCRTC RC1721 RC174



2 1/20W_1M_5%_0201



1



@ 2



PCH_PM_SLP_S5_N



RC188



1



PCH_PM_SLP_S3_N



RC181



PCH_PM_SLP_S4_N PCH_PM_SLP_A_N



2



100K_0201_5%



1



2



100K_0201_5%



RC182



1



2



100K_0201_5%



RC185



1



2



100K_0201_5%



@



2 10K_0201_5% @



+3VALW_PCH CPU_C10_GATE_N



RC31



@



PCH_PWROK



RC177



1



2 10K_0201_5%



SYS_PWROK



RC179



1



2 10K_0201_5%



VCCST_OVERRIDE



RC180



1



2 100K_0201_5%



2



100K_0201_5%



INTRUDER_N



2 1/20W_1M_5%_0201



B



CC25



GPD7(BB_TBT_PERST#): Rising edge of DSW_PWROK This signal has a 20K+-30% internal pull-down. This strap should sample LOW. There should NOT be any on-board device driving it to opposite direction during strap sampling Notes: 1. The internal pull-down is disabled after DSW_PWROK is high. 2. This signal is in the DSW well



@



1 0.1U_6.3V_K_X5R_0201



INTRUDER# RTC-Well Input Strap Requirements should have a weak external pull-up to VccRTC



PCH_PM_SLP_WLAN_NRC186



1



@



2



100K_0201_5%



PCH_PM_SLP_LAN_N RC187



1



@



2



100K_0201_5%



PCH_PM_SLP_SUS_N RC178



1



2



100K_0201_5%



PLT_RST_N



1



2



100K_0201_5%



RC189



B



Glitch Free Requirements: Cap or pull-down resistor is required



FOR EMC



Option 1:Cap Implementation 330 nF for 3.3v Ramp Rate from 5-50ms 33 nF for 3.3V Ramp Rate Less than 5ms 0.1U_6.3V_K_X5R_0201 1



2 CC5



EMC_NS@



PCH_PLT_RST_N



0.1U_6.3V_K_X5R_0201 1



2 CC6



EMC_NS@



PCH_PWROK



0.1U_6.3V_K_X5R_0201 1



2 CC7



EMC_NS@



SYS_PWROK



1000P 25V K X7R 0201 1



2 CC33



EMC_NS@



PCH_RSMRST_N



1000P 25V K X7R 0201 1



2 CC34



EMC_NS@



PCH_DPWROK



0.01U_25V_K_X5R_0201 1



2 CC55



EMC_NS@



VCCST_PWRGD



Option 2:Pull-down Resistor Implementation 100K for 3.3V Signaling Mode 75K for 1.8V Signaling Mode



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



SYSTEM PM Tuesday, November 10, 2020 1



Sheet



17



of



110



5



4



3



2



1



UC1M 13 OF 21



2



1 100_0402_1%



VR_SVID_DATA



RC191



2



1 56_0402_5%



VR_SVID_ALERT_N



RC192



2



1 1/16W_45.3_1%_0402 VR_SVID_CLK



@



CAD NOTE: Alert signal must be routed between Clk and Data signals to minimize Cross-Talk.



D



+VCCSTG_OUT_LGC



+VCCSTG_TERM @ 1



RC193



2 0_0402_5%



+1.2V



+1.2V



+VCCSTG_OUT



+VCCSTG_FUSE @ 1



RC197



2 0_0402_5%



+VCCSTG_OUT



+VCCFPGM @



C



1



RC198



2 0_0402_5%



VCCIN_66 VCCIN_67 VCCIN_68 VCCIN_69 VCCIN_70 VCCIN_71 VCCIN_72 VCCIN_73 VCCIN_74 VCCIN_75 VCCIN_76 VCCIN_77 VCCIN_78 VCCIN_79 VCCIN_80 VCCIN_81 VCCIN_82 VCCIN_83 VCCIN_84 VCCIN_85 VCCIN_86 VCCIN_87 VCCIN_88 VCCIN_89 VCCIN_90 VCCIN_91 VCCIN_92 VCCIN_93 VCCIN_94 VCCIN_95 VCCIN_96 VCCIN_97 VCCIN_98 VCCIN_99 VCCIN_100 VCCIN_101 VCCIN_102 VCCIN_103 VCCIN_104 VCCIN_105 VCCIN_106 VCCIN_107 VCCIN_108 VCCIN_109 VCCIN_110 VCCIN_111 VCCIN_SENSE VSSIN_SENSE VIDSOUT VIDSCK VIDALERT#



D



+VCCIN 1



RC190



VCCIN_1 VCCIN_2 VCCIN_3 VCCIN_4 VCCIN_5 VCCIN_6 VCCIN_7 VCCIN_8 VCCIN_9 VCCIN_10 VCCIN_11 VCCIN_12 VCCIN_13 VCCIN_14 VCCIN_15 VCCIN_16 VCCIN_17 VCCIN_18 VCCIN_19 VCCIN_20 VCCIN_21 VCCIN_22 VCCIN_23 VCCIN_24 VCCIN_25 VCCIN_26 VCCIN_27 VCCIN_28 VCCIN_29 VCCIN_30 VCCIN_31 VCCIN_32 VCCIN_33 VCCIN_34 VCCIN_35 VCCIN_36 VCCIN_37 VCCIN_38 VCCIN_39 VCCIN_40 VCCIN_41 VCCIN_42 VCCIN_43 VCCIN_44 VCCIN_45 VCCIN_46 VCCIN_47 VCCIN_48 VCCIN_49 VCCIN_50 VCCIN_51 VCCIN_52 VCCIN_53 VCCIN_54 VCCIN_55 VCCIN_56 VCCIN_57 VCCIN_58 VCCIN_59 VCCIN_60 VCCIN_61 VCCIN_62 VCCIN_63 VCCIN_64 VCCIN_65



RC194 100_0402_1% 2



+VCCST_CPU



+VCCIN G32 H24 H26 H30 H32 J1 J2 K1 K2 K24 K26 K30 K32 L24 L26 L30 L32 N24 N26 N30 N32 P24 P26 P28 P30 P32 T21 T23 T25 T27 T31 U23 U27 U29 U31 U33 V23 V25 V27 V29 V31 V33 W22 W24 W28 W32 VCCIN_SENSE VSSIN_SENSE



R38 R37



VCCIN_SENSE VSSIN_SENSE



M12 VR_SVID_DATA M11 VR_SVID_CLK P12 VR_SVID_ALERT_N



VR_SVID_DATA [95] VR_SVID_CLK [95] VR_SVID_ALERT_N [95]



[95] [95] C



1



A24 A26 A29 A30 A33 A35 AY39 B24 B26 B29 B30 B33 B35 BA10 BA40 BB39 BB9 BC10 BC40 BD39 BD9 BE10 BE40 BF9 BG10 BG40 BH12 BH39 BH9 BJ10 BJ40 BK39 BL10 BL40 BM39 BN40 BP12 BP39 BR10 BR40 BT12 BT39 BU10 BU40 BV12 BY12 CA10 CB12 D24 D26 D29 D30 D33 D35 E24 E26 E27 E29 E30 E32 E33 G2 G24 G26 G30



RC196 100_0402_1% 2



+VCCIN



TGLLAKE-U_BGA1449 @



PDG: VCCST 1u_0402 * 2



PDG: VCCSTG 1u_0402 * 2



+VCCST_CPU



+VCCSTG_CPU



2



2



15 OF 21



1 @



2



AA39 AB40 AC39 AD40 AD51 AD52 AE39 AF40 AG39 AH40 AJ39 AK40 AK51 AK52 AL39 AM40 AN39 AP40 AR39 AT52 AU40 AW40 AW51 AW52 BD51 BD52 BK51 BK52 BV51 BV52 CA40 CC40 CC49 CC50 CE40 CG40 CH39 CJ40 CL40 CN40 CP47 CR40 D50 E51 F49 T51 T52



1U_6.3V_M_X5R_0201 CC38



@



1



1U_6.3V_M_X5R_0201 CC37



B



1



1U_6.3V_M_X5R_0201 CC36



2



1U_6.3V_M_X5R_0201 CC35



1



UC1O +1.2V



+VCCIN



2



1



2



CC91 EMC@ 0.1U_6.3V_K_X5R_0201



1



12P_50V_F_COG_0402 CC90 EMC@



2



100P_0402_50V8J CC89 EMC@



1



Place as close as possible to the package (less than 5mm).



A



VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8 VDD2_9 VDD2_10 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20 VDD2_21 VDD2_22 VDD2_23 VDD2_24 VDD2_25 VDD2_26 VDD2_27 VDD2_28 VDD2_29 VDD2_30 VDD2_31 VDD2_32 VDD2_33 VDD2_34 VDD2_35 VDD2_36 VDD2_37 VDD2_38 VDD2_39 VDD2_40 VDD2_41 VDD2_42 VDD2_43 VDD2_44 VDD2_45 VDD2_46 VDD2_47



VCCSTG_OUT_1 VCCSTG_1 VCCSTG_2 VCCSTG_OUT_2 VCCSTG_OUT_3 VCCSTG_OUT_4 VCCIO_OUT VCCSTG_OUT_LGC VCCST_1 VCCST_2 VCCST_3 VCCSTG_3 VCCSTG_4 VCCSTG_5



AF9 AF12 AD12



+VCCSTG_OUT



AN10 AM9 AG10



+VCCFPGM



V15



+VCCSTG_FUSE



INTERNAL RAIL.



+VCCIO_OUT



M9



+VCCSTG_OUT_LGC



BT2 BT1 BT4



+VCCST_CPU



BP2 BP1 BP4



+VCCSTG_CPU



B



A



TGLLAKE-U_BGA1449 @



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



CPU Power(1/2) Tuesday, November 10, 2020 1



Sheet



18



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



CPU Power(2/2) Tuesday, November 10, 2020 1



Sheet



19



of



110



5



4



3



+VCCIN_AUX



+1.8VALW_PCH



+1.8VALW



1



UC1N 14 OF 21



RC857



1



2 0_5%_0603



@



AB12 AC10 AE10 AK2 AR10 AT12 AU10 AW10 BV1 BV39 BW40 BY39 CC1 CD12 CF10 CG12 CH10 CJ1 CJ12 CK10 CL12 CM10 CP1 CP10 CR12 CT10 CU12 CY1 AK1



D



+VCCPDSW_3P3



+3VALW



0.003A @ RC232



1



RC199



1



2 0_0402_5%



+3VALW_PCH



1



1U_6.3V_M_X5R_0201 CC39



2 0_0402_5%



@



PDG: VCCDSW_3P3 Placeholder 1* 0402 capacitor on primary side 2 as close as possible to the vias.



@



VCCIN_AUX_VSSSENSE VCCIN_AUX_VCCSENSE +VNN_BYPASS



+3VALW_PCH



+V1.05A_BYPASS



+VCCPRIM_3P3



AV9 AT9



1.05V / 0.76V 0.2ADD17 DD18 1.05V



0.2ADA15 DA17



@ RC858



1



2 0_0402_5% 0.202A 1



2



1 @



2



@



1 1



@ TP20 @ TP21



CC41 0.1U_6.3V_K_X5R_0201



PDG: VCCPRIM_3P3 Placeholder up to 2 capacitor If capacitor is on primary side place it near to package pins right after signal breakout. If capacitor is on secondary side, make sure the capacitor pads have power(VCC) and ground (GND) vias next to each other, connected to main plane



1U_6.3V_M_X5R_0201 CC40



C



2



[84,93] [84,93]



GPPC_B2_VRALERT_N DB39 GPPC_F22_VNN_CTRL DV12 GPPC_F23_V1P05_CTRL DT12 VCCIN_AUX_VID0 VCCIN_AUX_VID1



VCCIN_AUX_VID0 VCCIN_AUX_VID1



DB37 DB38



VCCPRIM_1P8_1 VCCPRIM_1P8_2 VCCPRIM_1P8_3 VCCPRIM_1P8_4 VCCPRIM_1P8_5 VCCPRIM_1P8_6 VCCPRIM_1P8_7 VCCPRIM_1P8_8 VCCPRIM_1P8_9 VCCPRIM_1P8_10 VCCPRIM_1P8_11 VCCPRIM_1P8_12 VCCPRIM_1P8_13 VCCPRIM_1P8_14 VCCPRIM_1P8_15 VCCPRIM_1P8_16 VCCPRIM_1P8_17



DV46



VCCLDOSTD_0P85



VCCDPHY_1P24 VCCDSW_1P05



VCC_V1P05EXT_1P05_1 VCC_V1P05EXT_1P05_2 GPP_B2/VRALERT# GPP_F22/VNN_CTRL GPP_F23/V1P05_CTRL



0.165A



VCCRTC VCCDSW_3P3 VCCPGPPR VCCPRIM_3P3_5 VCCPRIM_3P3_6 VCCPRIM_1P8_18



This rail is generated internally and needs to be routed out to the motherboard for decoupling purposes.



+VCCA_CLKLDO_1P8



INTERNAL RAIL.



+VCCDPHY_1P24



DD38



INTERNAL RAIL.



+VCCDSW_1P05



DA31 DC33 DC31



VCCPRIM1P05_OUT_PCH_1 VCCPRIM1P05_OUT_PCH_2 VCCPRIM1P05_OUT_PCH_3



+VCCLDOSTD_OUT_0P85



DV28



BR3 BR4 BT5



VCC1P05_OUT_FET_1 VCC1P05_OUT_FET_2 VCC1P05_OUT_FET_3



GPP_B0/CORE_VID0 GPP_B1/CORE_VID1



+VCCRTCEXT INTERNAL RAIL.



DV16 DC15



VCCA_CLKLDO_1P8_1 VCCA_CLKLDO_1P8_2



VCC_VNNEXT_1P05_1 VCC_VNNEXT_1P05_2



+VCCPRIM_3P3



DV34



DCPRTC



VCCIN_AUX_VSSSENSE VCCIN_AUX_VCCSENSE



D



DA35 DC28 DC30 DD30



VCCPRIM_3P3_1 VCCPRIM_3P3_2 VCCPRIM_3P3_3 VCCPRIM_3P3_4



Note: Don't forget to check PU level



This rail is generated internally with a LDO and needs to be routed out to the motherboard for decoupling purposes.



+VCC1.05_OUT_FET INTERNAL RAIL. +VCC1.05_OUT_PCH



DC35 DD37 DA28



VCCRTC +VCCPDSW_3P3 +VCCPGPPR_3P3_1P8



CY31 CY33 CV39



+VCCPRIM_3P3



This is internally generated rail, do not connect to external supply. C



+VCCPRIM_1P8



AP12



RSVD_1 TGLLAKE-U_BGA1449 @



+VCCPGPPR_3P3_1P8



+1.8VALW_PCH



VCCIN_AUX_1 VCCIN_AUX_2 VCCIN_AUX_3 VCCIN_AUX_4 VCCIN_AUX_5 VCCIN_AUX_6 VCCIN_AUX_7 VCCIN_AUX_8 VCCIN_AUX_9 VCCIN_AUX_10 VCCIN_AUX_11 VCCIN_AUX_12 VCCIN_AUX_13 VCCIN_AUX_14 VCCIN_AUX_15 VCCIN_AUX_16 VCCIN_AUX_17 VCCIN_AUX_18 VCCIN_AUX_19 VCCIN_AUX_20 VCCIN_AUX_21 VCCIN_AUX_22 VCCIN_AUX_23 VCCIN_AUX_24 VCCIN_AUX_25 VCCIN_AUX_26 VCCIN_AUX_27 VCCIN_AUX_28 VCCIN_AUX_29



+VCCPRIM_1P8 CY18 CY20 CY24 CY26 DA18 DA20 DA22 DA24 DA26 DC18 DC20 DC22 DC24 DC26 DD20 DD22 DV22



+VCCIN_AUX @



+1.8VALW_PCH



[93] [93]



VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE



+3VALW_PCH



VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE



1



2



@



RC205 100_0402_1%



RC206 100_0402_1%



RC203 1/20W_20K_5%_0201



+VCCPRIM_1P8



[10,79]



H_PROCHOT_N



2



DC4



2



@



2



1



CC43 0.1U_6.3V_K_X5R_0201



2



1U_6.3V_M_X5R_0201 CC42



1



1



2 0_0402_5%



1



1



2



RC859



1



GPPC_B2_VRALERT_N



RB521CM-30T2R_VMN2M-2 1



1.3A 1



B



PDG: VCCPRIM_1P8 Placeholder ?u_0402 * 1 Place the 0402 capacitor on the primary side, as close as possible to the vias.



2



1



2



@



@



1



2



1U_6.3V_M_X5R_0201 CC48



2 0_5%_0603



1U_6.3V_M_X5R_0201 CC47



@



1U_6.3V_M_X5R_0201 CC46



RC815



the diffrent with Base: 1.S540 +1.8VALW_PCH To +VCCPRIM_1P8 directly , S360&V14V15 use RC815;



RC204



1



@



2 0_0402_5%



Follow CRB Page35 B



@



VCCRTC +VCCLDOSTD_OUT_0P85 +VCCA_CLKLDO_1P8 @ 2 0_0402_5%



0.165A



2



2



0 ohm_0603 100 mohm_0603



1



Option 1: stuff with 0 ohm if the inductor is not stuffed. Option 2: stuff 100 mohm if the inductor stuffed



1



Place the cap near to package pin DR15 and DR12 right after signal breakout



+VCCDSW_1P05



1



2



Place as close as possible to the package (less than 5mm).



1U_6.3V_M_X5R_0201 CC50



Inductor by default is a placeholder. If stuffed, the inductor needs to meet following requirement: Rated at least 150mA; DCR = 0.036Ohm +/- 20%



1



+V1.05A_BYPASS +VCCDPHY_1P24



RC209 100K_0201_5%



1



PDG: VCCDSW_1P05 1u_0402/0201 *1 Place on Primary/Secondary Side as close as possible to the package edge (less than 3mm).



2



CC52 4.7U_0402_6.3V6M



LCFC Highly Confidential Information 2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



Date: 4



3



@



A



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 5



RC210 1K_0402_5% @



PDG: VCCDPHY_1P24 4.7u_0402 *1 Place on Primary/Secondary Side as close as possible to the package edge (less than 3mm).



Security Classification Issued Date



+VNN_BYPASS



1



2



1



2



2@



1



CC94 EMC@ 0.1U_6.3V_K_X5R_0201



2



1



12P_50V_F_COG_0402 CC93 EMC@



1



100P_0402_50V8J CC92 EMC@



1



680nF (Placeholder)



47u_0603



2



PDG: VCCRTC 1u_0402 *1 + 0.1u_0402 *1 If capacitor is on primary side place it near to package pins right after signal breakout. If capacitor is on secondary side, make sure the capacitor pads have power(VCC) and ground (GND) vias next to each other, connected to main plane



VCCA_CLKLDO_R



PDG: VCCA_CLKLDO_1P8



A



2



PDG: VCCRTCEXT 0.1u_0402 *1 Place on Primary/Secondary Side as close as possible to the package edge (less than 3mm).



+VCCIN_AUX



1U_6.3V_M_X5R_0201 CC54



CC53 47U_6.3V_M_X5R_0805_H1.25



CC51 0.1u_0201_10V6K



1



1



1



RC208 0_0402_5% @



2



1



2



1



2



RC860



1



0.1U_6.3V_K_X5R_0201 CC45



PDG: VCCLDOSTD_0P85 2.2u_0402 *1 CC49 Place on Primary/Secondary Side 2.2U_0402_6.3V6M as close as possible to the package 2 edge (less than 3mm). Do not use bigger capacitance value than 2.2uF. Use 10% tolerance capacitance. 1



1U_6.3V_M_X5R_0201 CC44



+1.8VALW_PCH



+VCCRTCEXT



2



Document Number



Rev 0.1



PCH Power Tuesday, November 10, 2020 1



Sheet



20



of



110



5



4



3



2



1



UC1R UC1P



UC1Q 16 OF 21



D



C



B



A27 A32 A45 A49 AA41 AA48 AB5 AB7 AB8 AC44 AC49 AD4 AD48 AD8 AF4 AF8 AG41 AG42 AG44 AG45 AG47 AG48 AG53 AH4 AH8 AK12 AK4 AK48 AK5 AK7 AK8 AM1 AM2 AM4 AM8 AN41 AN42 AN44 AN45 AN47 AN48 AN53 AP4 AP8 AT4 AT48 AT51 AT8 AV12 AV39 AV4 AV5 AV7 AV8 AW1 AW2 AW48 AY4 AY41 AY42 AY44 AY45 AY47 AY8 AY9 B13



VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288



18 OF 21 17 OF 21



VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353



B19 B2 B23 B27 B32 B36 B39 B42 B48 B52 B8 BA48 BA53 BB4 BB8 BC1 BC2 BD12 BD4 BD48 BD8 BF39 BF4 BF41 BF42 BF44 BF45 BF47 BF5 BF7 BF8 BG48 BG53 BH1 BH2 BH4 BH8 BK12 BK4 BK48 BK8 BL49 BM1 BM4 BM41 BM42 BM44 BM45 BM47 BM8 BN48 BP41 BP49 BP5 BP50 BP7 BT44 BT48 BU49 BV3 BV48 BV5 BW10 BY41 BY42



BY44 BY45 BY47 BY49 BY9 C13 C19 C23 CA48 CB41 CC10 CC3 CC5 CD44 CD48 CD7 CE49 CG48 CG51 CG52 CG9 CH41 CH42 CH44 CH45 CH47 CJ3 CJ5 CJ9 CK39 CK48 CK53 CL9 CN12 CN48 CN51 CN52 CN9 CP3 CP41 CP42 CP44 CP45 CP5 CR48 CR53 CR9 CT5 CU4 CU9 CV10 CV48 CV5 CV51 CV52 CY17 CY22 CY35 CY41 CY42



VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168



VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222



DP53 DR11 DR16 DR22 DR28 DR34 DR40 DR46 DT4 DT50 DU11 DU16 DU22 DU28 DU34 DU40 DU46 DV1 DV40 DV52 DW51 E13 E19 E35 E48 G22 G28 G34 G39 G48 G51 G52 H12 H22 H28 H34 H8 J39 J49 K16 K18 K20 K22 K28



CY44 CY45 CY47 CY5 D27 D32 D36 D42 D49 D5 DA30 DA33 DA53 DC17 DD15 DD24 DD26 DD28 DD31 DD33 DD35 DD39 DD45 DD51 DD52 DE3 DE5 DF19 DF37 DG15 DG21 DG27 DG33 DG39 DG45 DG5 DG53 DG6 DJ1 DJ2 DJ4 DK51 DL3 DL5 DM10 DM15 DM21 DM27 DM33 DM39 DM4 DM45 DN1 DN2



VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45



VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108



K34 K48 K5 L22 L28 L34 L39 L41 L42 L44 L45 L47 L49 M1 M2 M50 N22 N28 N34 N39 N41 N48 P11 P14 P16 P18 P20 P22 P33 P35 P4 P49 P8 R39 R44 T19 T29 T33 T4 T48 T8 U19 U25 U39 U49 V19 V4 V8 W1 W16 W26 W30 W39 W41 W42 W44 W45 W47 W48 Y4 Y49 Y50 Y8



D



C



B



TGLLAKE-U_BGA1449 @



TGLLAKE-U_BGA1449 @



TGLLAKE-U_BGA1449 @



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



PCH Power



Tuesday, November 10, 2020



Sheet 1



21



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



PCH PWR_Reserved



Tuesday, November 10, 2020



Sheet 1



22



of



110



5



4



3



2



1



+VCCIO_OUT UC1T



SKTOCC#



2 RC212 1 1K_0201_5%



2 RC219



2 RC218



2 RC215



2 RC222



VSS_1 TP_3 TP_4 RSVD_17 RSVD_18



RSVD_8 RSVD_9 RSVD_10 RSVD_11



@



@



@ 1 1K_0201_5%



RSVD_TP_23 RSVD_TP_24



2 RC213



BN10 BM12 DD13 DF13



TCP0_MBIAS_RCOMP RSVD_TP_2 RSVD_TP_3 RSVD_TP_4 RSVD_TP_5 RSVD_TP_6



1 1K_0201_5%



AR2 AL10 AM12 AH12 AJ10 AR1



2 RC223



2 2.2K_0402_1% 1 TP75 1 TP76 1 TP78 1 TP80 1 TP81



1 1K_0201_5%



@ @ @ @ @



RSVD_16 RSVD_TP_21 RSVD_TP_22



2 RC214



1



RSVD_6 RSVD_7



1 1K_0201_5%



RC231



RSVD_TP_19 RSVD_TP_20



2 RC224



A3 B3 TCP0_MBIAS RSVD_TP_2 RSVD_TP_3 RSVD_TP_4 RSVD_TP_5 RSVD_TP_6



RSVD_TP_17 RSVD_TP_18



BPM#_3 BPM#_2 BPM#_1 BPM#_0



1 1K_0201_5%



Y1 M4 AB4 Y2



RSVD_TP_13 RSVD_TP_14



1 1



TP42 @ TP43 @



1 1K_0201_5%



BPM3_N BPM2_N BPM1_N BPM0_N



DV4 DW3 DU1 DT2



RSVD_TP_15 RSVD_TP_16



1 1



TP44 @ TP48 @



DW2 DV2



RSVD_TP_17 RSVD_TP_18



1 1



TP53 @ TP57 @



E1 F1



RSVD_TP_19 RSVD_TP_20



1 1



TP63 @ TP66 @



2 RC229



1 1 1 1



@



AH9



DR1 DR2



RSVD_TP_21 RSVD_TP_22



1 1



TP71 @ TP73 @



@



@



@



@



@



DR53 DW5



RSVD_TP_23 RSVD_TP_24



1 1



TP77 @ TP79 @



1 1



TP82 @ TP83 @



1



TP84 @



DW6 DV6



CPU_CFG14 CPU_CFG11 CPU_CFG10 CPU_CFG9 CPU_CFG7 CPU_CFG4 CPU_CFG3 CPU_CFG2 CPU_CFG1



AB2



DV51 DW52 TP_3 DV53 TP_4 W34 V35 D52



SKTOCC_N



1 1K_0201_5%



@ @ @ @



RSVD_TP_15 RSVD_TP_16



CFG_17 CFG_16



TP36 @



1 1K_0201_5%



U17 H11



1



2 RC228



CPU_CFG17 CPU_CFG16



RSVD_TP_12



1 1K_0201_5%



1 1



CP39 CU40 AK9



1 1K_0201_5%



CFG_RCOMP



@ TP47 @ TP51 TP56 TP59 TP62 TP65



RSVD_TP_13 RSVD_TP_14



TP33 @ TP34 @



2 RC225



B5



1 1



2 RC216



CFG_RCOMP



RSVD_TP_9 RSVD_TP_10



1 1K_0201_5%



1



1 49.9_0402_1%



C1 D2



1 1K_0201_5%



2



RSVD_14 RSVD_15



TP23 @ TP32 @



2 RC226



@ TP41 RC221



RSVD_13



1 1



1 1K_0201_5%



D



RSVD_TP_11 RSVD_TP_12 RSVD_12



RSVD_TP_7 RSVD_TP_8



2 RC217



1 1



RSVD_TP_9 RSVD_TP_10



A51 B51



1 1K_0201_5%



@ TP31 @ TP37



RSVD_TP_7 RSVD_TP_8



2 RC227



1



CFG_15 CFG_14 CFG_13 CFG_12 CFG_11 CFG_10 CFG_9 CFG_8 CFG_7 CFG_6 CFG_5 CFG_4 CFG_3 CFG_2 CFG_1 CFG_0



1 1K_0201_5%



@ TP29



T15 V17 U15 K11 K12 K9 T17 K7 H7 K8 H9 E6 H5 E9 D9 E7



1 1K_0201_5%



1 1



2 RC230



1



@ TP25 @ TP26



1 1K_0201_5%



@ TP22



2 RC220



20 OF 21



CPU_CFG15 CPU_CFG14 CPU_CFG13 CPU_CFG12 CPU_CFG11 CPU_CFG10 CPU_CFG9 CPU_CFG8 CPU_CFG7 CPU_CFG6 CPU_CFG5 CPU_CFG4 CPU_CFG3 CPU_CFG2 CPU_CFG1 CPU_CFG0



D



TGLLAKE-U_BGA1449 @ UC1S C



C



19 OF 21



DF53 DF52 @ TP38 @ TP40



1 1



PCH_IST_TP_1 PCH_IST_TP_0



DT52 DU53 DF50 DF49



@ TP45 @ TP49



1 1



CPU_CFG25 CPU_CFG26



CY30 CY15



@ TP54



1



CPU_CFG27



D4



@ TP60 @ TP64



1 1



IST_TP_1 IST_TP_0



A6 A4



RSVD_19 RSVD_20 PCH_IST_TP_1 PCH_IST_TP_0 RSVD_21 RSVD_22 RSVD_TP_25 RSVD_TP_26 RSVD_TP_27 IST_TP_1 IST_TP_0



RSVD_23 RSVD_24 RSVD_25 RSVD_26 RSVD_27 RSVD_28 RSVD_29 RSVD_30 RSVD_31 RSVD_TP_28 RSVD_TP_29 RSVD_TP_30 RSVD_TP_31 RSVD_TP_32 RSVD_TP_33 RSVD_32 RSVD_TP_34 RSVD_TP_35 RSVD_TP_36 RSVD_TP_37 RSVD_TP_38 RSVD_TP_39



TGLLAKE-U_BGA1449 @



B



the diffrent with Base: 1.S540 Remove All TP, S360&V14V15 use



C53 T35 E53 CF39 U35 F53 B53 AP9 A52 BF12 V21 W20 U37 CD39 U21 CB39 BB12 W37 AY12 W38 U38 CY28



CPU_CFG28 CPU_CFG29 CPU_CFG30 CPU_CFG31



1 1 1 1



TP46 TP50 TP52 TP55



CPU_CFG33



1



TP61 @



CPU_CFG35 CPU_CFG36 CPU_CFG37 CPU_CFG38 CPU_CFG39



1 1 1 1 1



TP68 TP69 TP70 TP72 TP74



@ @ @ @



@ @ @ @ @



Pin Name



Strap Description



Configuration



CFG[0]



RSVD



None



CFG[3:1]



RSVD



Pull-up to VCCIO



1Kohm



CFG[4]



eDP enable strap 1 = Disabled 0 = Enabled



Pull-up to VCCIO / Pull-down Platform design dependent



1Kohm



CFG[6:5]



RSVD



None



PEG deferred link training 1 = (default) PEG Trainimmediately following RESET# de-assertion. 0 = PEG Wait for BIOS for training.



Pull-up to VCCIO / Pull-down Platform design dependent



CFG[8]



RSVD



None



CFG[11:9]



RSVD



Pull-up to VCCIO



CFG[13:12]



RSVD



None



CFG[14]



PEG60 Lane Reversal 1 = Normal(Default) 0 = Reversed



Pull-up to VCCIO / Pull-down Platform design dependent



RSVD



None



CFG[7]



CFG[17:15]



Default Value



1Kohm



1Kohm



1Kohm B



CPU PCIe Gen4 Bifurcation and Lane Reversal Mapping CFG Signals



Bifurcation



CFG [14] 1x4 1x4(Reversed)



Lanes 0



1



2



3



1



0



1



2



3



0



3



2



1



0



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



PCH PWR_Reserved



Tuesday, November 10, 2020 1



Sheet



23



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



XDP



Tuesday, November 10, 2020



Sheet 1



24



of



110



5



4



3



2



DDRA_DQ[0..63]



DDRA_DQ[0..63]



1



[8]



+1.2V



1



+1.2V +1.2V JDDR1B



D



DDRA_MA3 DDRA_MA1



DDRA_MA3 DDRA_MA1



[8] [8]



DDRA_CLK0_P DDRA_CLK0_N



[8]



DDRA_PAR



[8]



DDRA_BA1



131 133 135 137 139 141 143



DDRA_CLK0_P DDRA_CLK0_N DDRA_PAR



A3 A1 VDD_9 CK0_t CK0_c VDD_11 Parity



A2 EVENT_n VDD_10 CK1_t CK1_c VDD_12 A0



132 134 136 138 140 142 144



DDRA_MA2 DDRA_EVENT_N



146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260



DDRA_MA10



DDRA_MA2



DDRA_CLK1_P DDRA_CLK1_N DDRA_MA0



[8]



+1.2V



2



[8] [8]



RD133 240_0402_1% @



1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129



DDRA_DQ59 DDRA_DQ60



DDRA_CLK1_P DDRA_CLK1_N



[8] [8]



DDRA_MA0



[8]



DDRA_MA10



[8]



DDRA_DQ63



DDRA_BA0 DDRA_MA16_RAS_N



[8] [8]



DDRA_DQ47



DDRA_MA15_CAS_N DDRA_MA13



[8] [8]



[8] [8]



DDRA_DQS7_N DDRA_DQS7_P



DDRA_DQS7_N DDRA_DQS7_P



DDRA_DQ61



DDRA_ODT0 DDRA_CS1_N



[8]



DDRA_ODT1



DDRA_ODT0 DDRA_CS1_N DDRA_ODT1



[8] [8]



DDRA_DQS2_N DDRA_DQS2_P



DDRA_DQS2_N DDRA_DQS2_P



DDRA_DQ22 DDRA_DQ18 DDRA_DQ14 DDRA_DQ15



DDRA_DQ8 C



DDRA_DQ9 DDRA_DQ5 DDRA_DQ4 [8] [8]



DDRA_DQS0_N DDRA_DQS0_P



DDRA_DQS0_N DDRA_DQS0_P



DDRA_DQ3 DDRA_DQ0 DDRA_DQ27 DDRA_DQ24



DDRA_DQ28 DDRA_DQ30 [11] +3VS



SMB_CLK_S1 +VDD_SPD



SMB_CLK_S1 1 2 RD77 @



1



2



+2.5V_DDR



1



RD127



B



@



2



CD73



1



2



0.1u_0201_10V6K



CD72



2.2U_0402_6.3V6M



0_5%_0603



261



GND_1



GND_2



DDRA_DQ40 DDRA_DQ43



DDRA_DQ21 CD74



1



DDRA_DQ23 2 DDRA_DQ20



CD75 @



1



2



2.2U_0402_6.3V6M



DDRA_DQ17



DDRA_DQ46



+VREF_CA_DIMM DDRA_SA2 0.1u_0201_10V6K



DDRA_DQ19



DDRA_MA15_CAS_N DDRA_MA13



DDRA_DQ38 DDRA_DQ37 [8] [8]



DDRA_DQS4_N DDRA_DQS4_P



DDRA_DQS4_N DDRA_DQS4_P



DDRA_DQ16



DDRA_DQ35



DDRA_DQ12



DDRA_DQ32



DDRA_DQ13



DDRA_DQ51



DDRA_DQS1_N DDRA_DQS1_P



DDRA_DQS1_N DDRA_DQS1_P



DDRA_DQ48



[8] [8]



+1.2V



DDRA_DQ10 DDRA_DQ54 DDRA_DQ11 DDRA_DQ7



DDRA_DQ55



1



[8] [8]



DDRA_BA0 DDRA_MA16_RAS_N



RD129 240_0402_1%



DDRA_DQ6



RD128 240_0402_1% 2



DDRA_CS0_N DDRA_MA14_WE_N



DDRA_CS0_N DDRA_MA14_WE_N



BA1 A10/AP VDD_13 VDD_14 CS0_n BA0 WE_n/A14 RAS_n/A16 VDD_15 VDD_16 ODT0 CAS_n/A15 CS1_n A13 VDD_17 VDD_18 ODT1 C0/CS2_n/NC VDD_19 VREFCA C1/CS3_n/NC SA2 VSS_53 VSS_54 DQ37 DQ36 VSS_55 VSS_56 DQ33 DQ32 VSS_57 VSS_58 DQS4_c DM4_n/DBl4_n/NC DQS4_t VSS_59 VSS_60 DQ39 DQ38 VSS_61 VSS_62 DQ35 DQ34 VSS_63 VSS_64 DQ45 DQ44 VSS_65 VSS_66 DQ41 DQ40 VSS_67 VSS_68 DQS5_c DM5_n/DBl5_n/NC DQS5_t VSS_69 VSS_70 DQ46 DQ47 VSS_71 VSS_72 DQ42 DQ43 VSS_73 VSS_74 DQ52 DQ53 VSS_75 VSS_76 DQ49 DQ48 VSS_77 VSS_78 DQS6_c DM6_n/DBl6_n/NC DQS6_t VSS_79 VSS_80 DQ54 DQ55 VSS_81 VSS_82 DQ50 DQ51 VSS_83 VSS_84 DQ60 DQ61 VSS_85 VSS_86 DQ57 DQ56 VSS_87 VSS_88 DQS7_c DM7_n/DBl7_n/NC DQS7_t VSS_89 VSS_90 DQ62 DQ63 VSS_91 VSS_92 DQ58 DQ59 VSS_93 VSS_94 SCL SDA VDDSPD SA0 VPP_1 VTT VPP_2 SA1



1



[8] [8]



145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259



2



DDRA_BA1



DDRA_DQS8_N DDRA_DQS8_P



DDRA_DQ1 DDRA_DQ2 DDRA_DQ29 DDRA_DQ31 DDRA_DQS3_N DDRA_DQS3_P



DDRA_DQS3_N DDRA_DQS3_P



[8] [8]



DDRA_DQ26



DDRA_SA1



DDRA_CKE0



[8] [8]



DDRA_BG1 DDRA_BG0



[8] [8]



DDRA_DQ25 SMB_DATA_S1 DDRA_SA0



[8]



SMB_DATA_S1



[8] [8]



[11]



DDRA_CKE0 DDRA_BG1 DDRA_BG0 DDRA_MA12 DDRA_MA9



DDRA_MA12 DDRA_MA9



DDRA_MA8 DDRA_MA6



DDRA_MA8 DDRA_MA6



JDDR1A



+VPP



2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130



DDRA_DQ58



D



DDRA_DQ62



DDRA_DQ57 DDRA_DQ56 DDRA_DQ45 DDRA_DQ44 DDRA_DQS5_N DDRA_DQS5_P



DDRA_DQS5_N DDRA_DQS5_P



[8] [8]



DDRA_DQ42 DDRA_DQ41 DDRA_DQ36 DDRA_DQ39



DDRA_DQ34 DDRA_DQ33 DDRA_DQ52 DDRA_DQ53 DDRA_DQS6_N DDRA_DQS6_P



DDRA_DQS6_N DDRA_DQS6_P



[8] [8]



DDRA_DQ50



C



DDRA_DQ49



CPU_DRAMRST_N_R [8,26]



DDRA_CKE1



DDRA_CKE1



DDRA_ACT_N DDRA_ALERT_N



[8]



1



DDRA_ACT_N [8] DDRA_ALERT_N [8]



DDRA_MA11 DDRA_MA7 DDRA_MA5 DDRA_MA4



DDRA_MA11 DDRA_MA7



[8] [8]



DDRA_MA5 DDRA_MA4



[8] [8]



CD1806 0.1u_0201_10V6K 2@



ARGOS_D4AR0-26001-1P40 ME@



ARGOS_D4AR0-26001-1P40 ME@



VDDSPD: 1x2.2uF 1x0.1uF



0_5%_0603



VSS_1 VSS_2 DQ5 DQ4 VSS_3 VSS_4 DQ1 DQ0 VSS_5 VSS_6 DQS0_C DM0_n/DBIO_n/NC DQS0_t VSS_7 VSS_8 DQ6 DQ7 VSS_9 VSS_10 DQ2 DQ3 VSS_11 VSS_12 DQ12 DQ13 VSS_13 VSS_14 DQ8 DQ9 VSS_15 VSS_16 DQS1_c DM1_n/DBl1_n/NC DQS1_t VSS_17 VSS_18 DQ15 DQ14 VSS_19 VSS_20 DQ10 DQ11 VSS_21 VSS_22 DQ21 DQ20 VSS_23 VSS_24 DQ17 DQ16 VSS_25 VSS_26 DQS2_c DM2_n/DBl2_n/NC DQS2_t VSS_27 VSS_28 DQ22 DQ23 VSS_29 VSS_30 DQ18 DQ19 VSS_31 VSS_32 DQ28 DQ29 VSS_33 VSS_34 DQ24 DQ25 VSS_35 VSS_36 DQS3_c DM3_n/DBl3_n/NC DQS3_t VSS_37 VSS_38 DQ30 DQ31 VSS_39 VSS_40 DQ26 DQ27 VSS_41 VSS_42 CB5/NC CB4/NC VSS_43 VSS_44 CB1/NC CB0/NC VSS_45 VSS_46 DQS8_c DM8_n/DBI8_n/NC DQS8_t VSS_47 VSS_48 CB6/NC CB2/NC VSS_49 VSS_50 CB7/NC CB3/NC VSS_51 VSS_52 RESET_n CKE0 CKE1 VDD_1 VDD_2 BG1 ACT_n BG0 ALERT_n VDD_3 VDD_4 A12 A11 A9 A7 VDD_5 VDD_6 A8 A5 A6 A4 VDD_7 VDD_8



+0.6VS



262



+1.2V



the diffrent with Base: 1.S540 channeL A use MD S360&V14V15 use DIMM



B



+1.2V



+3VS



1 2



DDRA_SA1



RD68 0_0402_5%



RD130 0_0402_5%



RD131 0_0402_5% DDRA_SA2



RD132 0_0402_5% 1



CD70 RD74 0.1u_0201_10V6K 1K_0402_1% 2



@



2



2 2



DDRA_SA0



RD71 0_0402_5%



1



1 2 DDR_SA_VREFCA_C RD134 24.9_0402_1%



@



@



@



SPD Address = A0



2



A



1



2



1



CD68 0.022U_16V_K_X7R_0402



+VREF_CA_DIMM



2 2_0402_5%



@



1



1 1



RD67 0_0402_5%



2



2



@



RD70 [8] DDR_SA_VREFCA



+3VS



+3VS 1



RD73 1K_0402_1%



2



CD151 0.1u_0201_10V6K



SPD address setting Need confirm with BIOS



1



2



Note: VREF trace width:20 mils at least Spacing:20mils to other signal/planes Place near DIMM scoket



1



1



LCFC Highly Confidential Information



Security Classification Issued Date



A



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



Memory_CHA



Tuesday, November 10, 2020 1



Sheet



25



of



110



5



4



3



2



1



Apply X76 BOM to control SDP Memory Down stuff components!



RD75 1 RD78 1 DDRB_BA0 DDRB_BA1



[9] [9] [9]



DDRB_ACT_N DDRB_CS0_N DDRB_ALERT_N



[9]



DDRB_BG0



[9]



DDRB_ODT0



[9]



DDRB_PAR



DDRB_DM1 DDRB_DM0



E2 E7



DDRB_BA0 DDRB_BA1



N2 N8



DDRB_ACT_N DDRB_CS0_N DDRB_ALERT_N



L3 L7 P9



DDRB_BG0



M2



DDRB_ODT0



K3



DDRB_PAR



T3



VPP1 VPP2



PAR



VREFCA



TEN



VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS8



RESET_N



VSS7 VSS9 VSS10 ZQ



F3 G3 A7 B7



DDRB_DM3 DDRB_DM2



E2 E7



DDRB_BA0 DDRB_BA1



N2 N8



DDRB_ACT_N DDRB_CS0_N DDRB_ALERT_N



L3 L7 P9



+2.5V_DDR



B1 R9 +VREF_CA_SB



M1 E1 K1 N1 T1 B2 G8 K9



CD38



1



2



T7



DDP_VSS_5 1 DDPB@ 2 RD107 0_0201_5%



M9



DDRB_BG1_R



E9 F9



UD5_DDRB_UZQ ZQ5



1



CD36 @



CD37



1



2



2



CD39



1



2



RD98 1



DDRB_BG0



M2



DDRB_ODT0



K3



DDRB_PAR



T3



2 10K_0201_5% TEN_UD6



DQSL_C DQSL_T DQSU_C DQSU_T NF/UDM_N/UDBI_N NF/LDM_N/LDBI_N BA0 BA1 ACT_N CS_N ALERT_N



P1



2



ODT



VPP1 VPP2



PAR



VREFCA



TEN



VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS8



RESET_N



F1 H1 A2 D2 E3 A8 D8 E8 C9 H9



1



VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10



BG0



N9



CPU_DRAMRST_N_R



CD45 0.1U_6.3V_K_X5R_0201 @



CKE



VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10



VSS7 VSS9 VSS10 ZQ



1



VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10



2 0_0201_5% 2 0_0201_5%



DDRB_DQS4_N DDRB_DQS4_P DDRB_DQS6_N DDRB_DQS6_P



VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10



RD111 1/20W_240_1%_0201



D1 J1 L1 R1 B3 G7 B9 J9 L9 T9



CD60 0.1U_6.3V_K_X5R_0201



B1 R9



1



2



M1



+VREF_CA_SB



E1 K1 N1 T1 B2 G8 K9



1



2



T7



DDP_VSS_6 1 DDPB@ 2 RD108 0_0201_5%



M9



DDRB_BG1_R



E9 F9



UD6_DDRB_UZQ ZQ6



CD40 @



1



CD42 CD41



2



1



2



CD43



1



2



[9]



DDR_SB_VREFCA



RD1241



RD123 1/20W_1.8K_1%_0201



2 1/20W_2.7_1%_0201



1



CD65 0.022U_6.3V_K_X5R_0201 2 DDR_SB_VREFCA_C



2 0_0201_5% 2 0_0201_5%



K8 K7



DDRB_CKE0



K2



DDRB_DQS1_N DDRB_DQS1_P DDRB_DQS3_N DDRB_DQS3_P



F3 G3 A7 B7



DDRB_DM5 DDRB_DM4



E2 E7



DDRB_BA0 DDRB_BA1



N2 N8



B



DDRB_ACT_N DDRB_CS0_N DDRB_ALERT_N



L3 L7 P9



DDRB_BG0



M2



DDRB_ODT0 DDRB_PAR



RD126 24.9_0201_1%



1



BG0



VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS8



RESET_N



VSS7 VSS9 VSS10 ZQ



B1 R9 M1



+VREF_CA_SB



E1 K1 N1 T1 B2 G8 K9



1



T7



2



1DDP_VSS_7 2 RD119 DDPB@ 0_0201_5%



M9



DDRB_BG1_R



E9 F9



UD7_DDRB_UZQ ZQ7



CD49 @



1



2



CD48 CD50



1



2



CD51



1



2



F3 G3 A7 B7



DDRB_DM7 DDRB_DM6



E2 E7



DDRB_BA0 DDRB_BA1



N2 N8



DDRB_ACT_N DDRB_CS0_N DDRB_ALERT_N



L3 L7 P9



DDRB_BG0



M2



DDRB_ODT0



K3



DDRB_PAR RD1181



2 10K_0201_5% TEN_UD8 CPU_DRAMRST_N_R



CD57 0.1U_6.3V_K_X5R_0201 @



1



VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10



+2.5V_DDR



K2



DDRB_DQS5_N DDRB_DQS5_P DDRB_DQS7_N DDRB_DQS7_P



1



2



T3 N9 P1 F1 H1 A2 D2 E3 A8 D8 E8 C9 H9



CKE DQSL_C DQSL_T DQSU_C DQSU_T NF/UDM_N/UDBI_N NF/LDM_N/LDBI_N BA0 BA1 ACT_N CS_N ALERT_N



VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10



ODT



VPP1 VPP2



PAR



VREFCA



TEN



VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS8



VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10



VSS7 VSS9 VSS10 ZQ



RD121 1/20W_240_1%_0201



RPD9



1 2



4 1/16W_36_5%_4P2R_0404 3



2



DDRB_ACT_N DDRB_BG0



RPD20



1 2



4 1/16W_36_5%_4P2R_0404 3



DDRB_MA0 DDRB_BA0



RPD21



1 2



4 1/16W_36_5%_4P2R_0404 3



DDRB_MA14_WE_N RPD22 DDRB_MA10



1 2



4 1/16W_36_5%_4P2R_0404 3



DDRB_MA11 DDRB_MA3



RPD23



1 2



4 1/16W_36_5%_4P2R_0404 3



DDRB_MA8 DDRB_PAR



RPD24



1 2



4 1/16W_36_5%_4P2R_0404 3



DDRB_MA2 DDRB_MA1



RPD25



1 2



4 1/16W_36_5%_4P2R_0404 3



DDRB_MA9 DDRB_MA12



RD69



1 DDPB@ 2 0_0201_5%



RPD26



1 2



4 1/16W_36_5%_4P2R_0404 3



DDRB_MA7 DDRB_MA13



RPD27



1 2



RD72



1 SDPB@ 2 0_0201_5%



RD82



1 SDPB@ 2 0_0201_5%



DDRB_BG1



[9]



4 1/16W_36_5%_4P2R_0404 3



4 1/16W_36_5%_4P2R_0404 3



Byte 5 UD5_DDRB_UZQ



Byte 7 UD6_DDRB_UZQ



D1 J1 L1 R1 B3 G7 B9 J9 L9 T9



UD7_DDRB_UZQ



RD85



1 DDPB@ 2 1/20W_240_1%_0201



RD88



1 SDPB@ 2 0_0201_5%



RD91



1 DDPB@ 2 1/20W_240_1%_0201



RD94



1 SDPB@ 2 0_0201_5%



RD99



1 DDPB@ 2 1/20W_240_1%_0201



RD102



1 SDPB@ 2 0_0201_5%



RD104



1 DDPB@ 2 1/20W_240_1%_0201



DDRB_CS0_N RPD14 DDRB_MA16_RAS_N



1 2



DDRB_BG1_R



RD103



2 DDPB@ 1 1/20W_36_5%_0201



DDRB_BA1



RD106



2



1



A1 C1 G1 F2 J2 F8 J8 A9 D9 G9



1 1/20W_36_5%_0201



+1.2V



RF & EMC UD8_DDRB_UZQ



2



1



2



B



+2.5V_DDR



B1 R9 +VREF_CA_SB



M1 E1 K1 N1 T1 B2 G8 K9



1



2



T7



DDP_VSS_8 1 2 RD120 DDPB@ 0_0201_5%



M9



DDRB_BG1_R



E9 F9



UD8_DDRB_UZQ ZQ8



CD52



CD54 @



1



2



CD55



1



2



CD53



1



2



+0.6VS



1



2



1



2



RD122 1/20W_240_1%_0201



K4AAG165WA-BCWE_FBGA96 @



+2.5V_DDR



2



2



K4AAG165WA-BCWE_FBGA96 @



DDRB_BG1_R



+1.2V



VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10



BG0



RESET_N



DDRB_CKE0 DDRB_ODT0



CD59 22P_0201_258J



VREFCA



TEN



2 0_0201_5% 2 0_0201_5%



DDRB_CKE0



CK_C CK_T



4 1/16W_36_5%_4P2R_0404 3



CD58 22P_0201_258J



PAR



@ @



K8 K7



1 2



1U_6.3V_M_X5R_0201



VPP1 VPP2



RD1151 RD1161



DDRB_CLK0_N DDRB_CLK0_P



WE_N/A14 CAS_N/A15 RAS_N/A16



DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7



DDRB_DQ47 DDRB_DQ43 DDRB_DQ45 DDRB_DQ41 DDRB_DQ46 DDRB_DQ40 DDRB_DQ44 DDRB_DQ42 DDRB_DQ59 DDRB_DQ63 DDRB_DQ61 DDRB_DQ60 DDRB_DQ58 DDRB_DQ57 DDRB_DQ62 DDRB_DQ56



G2 F7 H3 H7 H2 H8 J3 J7 A3 B8 C3 C7 C2 C8 D3 D7



1U_6.3V_M_X5R_0201



ODT



DDRB_DQS5_N DDRB_DQS5_P DDRB_DQS7_N DDRB_DQS7_P



L2 M8 L8



RPD19



C



0.1U_25V_K_X5R_0201



F1 H1 A2 D2 E3 A8 D8 E8 C9 H9



ACT_N CS_N ALERT_N



+1.2V



A1 C1 G1 F2 J2 F8 J8 A9 D9 G9



[9] [9] [9] [9]



DDRB_MA14_WE_N DDRB_MA15_CAS_N DDRB_MA16_RAS_N



A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC_N A13



DDRB_MA4 DDRB_MA6



CD66



RD112 1/20W_240_1%_0201



0.047U_0402_25V_X7R_0402



2



0.1U_25V_K_X5R_0201



@



CD56



P1



BA0 BA1



VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10



0.1U_25V_K_X5R_0201



1



T3 N9



NF/UDM_N/UDBI_N NF/LDM_N/LDBI_N



D1 J1 L1 R1 B3 G7 B9 J9 L9 T9



1U_6.3V_M_X5R_0201



CPU_DRAMRST_N_R



DQSL_C DQSL_T DQSU_C DQSU_T



VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10



1U_6.3V_M_X5R_0201



2 10K_0201_5% TEN_UD7



CKE



+1.2V



0.047U_0402_25V_X7R_0402



RD1171



K3



CK_C CK_T



Byte 3



P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8



4 1/16W_36_5%_4P2R_0404 3



CD47 RF_NS@ 22P_0201_258J



@ @



DDRB_CLK0_N DDRB_CLK0_P



WE_N/A14 CAS_N/A15 RAS_N/A16



Byte 1



DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13



1 2



+VREF_CA_SB



RD125 1/20W_1.8K_1%_0201 @



UD8



DDRB_DQ12 DDRB_DQ8 DDRB_DQ14 DDRB_DQ10 DDRB_DQ13 DDRB_DQ9 DDRB_DQ15 DDRB_DQ11 DDRB_DQ31 DDRB_DQ29 DDRB_DQ27 DDRB_DQ25 DDRB_DQ30 DDRB_DQ28 DDRB_DQ26 DDRB_DQ24



G2 F7 H3 H7 H2 H8 J3 J7 A3 B8 C3 C7 C2 C8 D3 D7



DDRB_MA5 RPD18 DDRB_MA15_CAS_N



CD46 RF_NS@ 22P_0201_258J



RD1131 RD1141



L2 M8 L8



DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7



1



2 A



Issued Date



1



2



1



2



1



2



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



A



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Document Number



4



3



2



1



Rev 0.1



Memory_CHB



Wednesday, November 11, 2020 Sheet



Date: 5



D



1



DDRB_DQS1_N DDRB_DQS1_P DDRB_DQS3_N DDRB_DQS3_P



DDRB_MA14_WE_N DDRB_MA15_CAS_N DDRB_MA16_RAS_N



A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC_N A13



2 1/20W_49.9_1%_0201



+1.2V +2.5V_DDR



K4AAG165WA-BCWE_FBGA96 @



2 +1.2V



[9] [9] [9] [9]



P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8



RD66 1



Terminal signal SWAP 0624



UD7 DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13



CD35 0.01U_25V_K_X5R_0201 1 DDRB_CLK0_R



+0.6VS



A1 C1 G1 F2 J2 F8 J8 A9 D9 G9



2



K4AAG165WA-BCWE_FBGA96 @



C



1 1/20W_36_5%_0201 1 1/20W_36_5%_0201



the diffrent with Base: 1.S360&V14V15 UD5&UD6&UD7&UD8 DQ SWAP; Rtt Resister Packs Rtt need change(manual) 36ohm SD300005100 3.S540 CD73~CD78 1.2v cap emc_ns@ for RF&EMC, S360&V14V15 No add



+1.2V



CK_C CK_T



2 2



+1.2V



0.1U_25V_K_X5R_0201



ODT



@ @



K2



RD64 RD65



DDRB_ALERT_N



1U_6.3V_M_X5R_0201



2



BG0



RD76 1 RD79 1



K8 K7



DDRB_CKE0



2



DDRB_CLK0_N DDRB_CLK0_P CD34 3.3P_50V_C_NPO_0201



Byte 6



1U_6.3V_M_X5R_0201



1



ACT_N CS_N ALERT_N



A1 C1 G1 F2 J2 F8 J8 A9 D9 G9



0.1U_25V_K_X5R_0201



F1 H1 A2 D2 E3 A8 D8 E8 C9 H9



BA0 BA1



VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10



DDRB_DQS4_N DDRB_DQS4_P DDRB_DQS6_N DDRB_DQS6_P



DDRB_CLK0_N DDRB_CLK0_P



WE_N/A14 CAS_N/A15 RAS_N/A16



1



@



0.1U_25V_K_X5R_0201



P1



NF/UDM_N/UDBI_N NF/LDM_N/LDBI_N



[9] [9] [9] [9]



+1.2V



0.047U_0402_25V_X7R_0402



CD44 0.1U_6.3V_K_X5R_0201 @



N9



DQSL_C DQSL_T DQSU_C DQSU_T



1U_6.3V_M_X5R_0201



CPU_DRAMRST_N_R



CPU_DRAMRST_N_R



CKE



D1 J1 L1 R1 B3 G7 B9 J9 L9 T9



1U_6.3V_M_X5R_0201



2 10K_0201_5% TEN_UD5



RD97 1 [8,25]



2 0_0201_5% 2 0_0201_5%



F3 G3 A7 B7



VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10



L2 M8 L8



2



Byte 4



0.047U_0402_25V_X7R_0402



[9] [9]



@ @



DDRB_DQS0_N DDRB_DQS0_P DDRB_DQS2_N DDRB_DQS2_P



CK_C CK_T



DDRB_MA14_WE_N DDRB_MA15_CAS_N DDRB_MA16_RAS_N



DDRB_DQ39 DDRB_DQ35 DDRB_DQ37 DDRB_DQ33 DDRB_DQ38 DDRB_DQ32 DDRB_DQ36 DDRB_DQ34 DDRB_DQ54 DDRB_DQ48 DDRB_DQ51 DDRB_DQ50 DDRB_DQ55 DDRB_DQ52 DDRB_DQ49 DDRB_DQ53



G2 F7 H3 H7 H2 H8 J3 J7 A3 B8 C3 C7 C2 C8 D3 D7



EMC_NS@ CD64 0.1u_0201_10V6K



DDRB_DQS0_N DDRB_DQS0_P DDRB_DQS2_N DDRB_DQS2_P



K2



+1.2V



DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7



EMC_NS@ CD63 0.1u_0201_10V6K



+1.2V



DDRB_CKE0



K8 K7



DDRB_CKE0



Byte 2



A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC_N A13



EMC_NS@ CD62 0.1u_0201_10V6K



[9] [9] [9] [9] [9]



DDRB_CLK0_N DDRB_CLK0_P



WE_N/A14 CAS_N/A15 RAS_N/A16



Byte 0



P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8



EMC_NS@ CD61 0.1u_0201_10V6K



DDRB_CLK0_N DDRB_CLK0_P



L2 M8 L8



+1.2V



UD6 DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13



1



[9] [9]



DDRB_MA14_WE_N DDRB_MA15_CAS_N DDRB_MA16_RAS_N



[9]



2



DDRB_DQ[0..63]



1



DDRB_MA14_WE_N DDRB_MA15_CAS_N DDRB_MA16_RAS_N



DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7



2



[9] [9] [9]



A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC_N A13



1



DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13



DDRB_DQ4 DDRB_DQ1 DDRB_DQ6 DDRB_DQ0 DDRB_DQ5 DDRB_DQ2 DDRB_DQ7 DDRB_DQ3 DDRB_DQ21 DDRB_DQ16 DDRB_DQ19 DDRB_DQ22 DDRB_DQ23 DDRB_DQ18 DDRB_DQ17 DDRB_DQ20



G2 F7 H3 H7 H2 H8 J3 J7 A3 B8 C3 C7 C2 C8 D3 D7



1



D



[9] [9] [9] [9] [9] [9] [9] [9] [9] [9] [9] [9] [9] [9]



P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8



2



DDRB_DQ[0..63] UD5 DDRB_MA0 DDRB_MA1 DDRB_MA2 DDRB_MA3 DDRB_MA4 DDRB_MA5 DDRB_MA6 DDRB_MA7 DDRB_MA8 DDRB_MA9 DDRB_MA10 DDRB_MA11 DDRB_MA12 DDRB_MA13



26



of



110



5



[11]



D



4



PCH_SPI0_CS0_N



[11]



PCH_SPI0_CLK



[11]



PCH_SPI0_SI



[11]



PCH_SPI0_SO



[11]



PCH_SPI0_IO2



[11]



PCH_SPI0_IO3



EC_SPI_CLK



[79]



EC_SPI_SI



[79]



EC_SPI_SO



RB1



1



PCH_SPI0_CLK



2 0_0201_5%



SPI_CS0_N



RB8



1



2 1/20W_10_1%_0201



SPI_CLK



PCH_SPI0_SI



RB3



1



2 1/20W_10_1%_0201



SPI_SI



PCH_SPI0_SO



RB6



1



2 1/20W_10_1%_0201



SPI_SO



PCH_SPI0_IO2



RB4



1



2 1/20W_10_1%_0201



SPI_IO2



PCH_SPI0_IO3



RB5



1



2 1/20W_10_1%_0201



SPI_IO3



@



2



+3VSUS



+3V_SPI



2



2 0_0402_5%



1



D



DB1



RB521CM-30T2R_VMN2M-2 @



EC_SPI_CS0_N



RB13 1



SPI_CS0_N



EC_SPI_CLK



RB10 1



2 1/20W_100_1%_0201 SPI_CLK



EC_SPI_SI



RB11 1



2 1/20W_100_1%_0201 SPI_SI



EC_SPI_SO



RB12 1



2 1/20W_100_1%_0201 SPI_SO



2 0_0201_5%



@



[27,79] [11]



C



1



@ RB2 1



[27,79] EC_SPI_CS0_N [79]



PCH_SPI0_CS0_N



3



SPI_SO



1



RB7



EC_SPI_CS0_N PCH_SPI0_CS1_N



RB26 1



@



2 0_0201_5%



RB9 1



@



2 0_0201_5%



SPI_CS1_N C



2 100K_0201_5%



@



+3V_SPI



1



UB2 SPI_CS0_N SPI_SO SPI_IO2



RB14 1 RB15 1 RB16 1



SPI_8M_CS0_N 2 0_0201_5% 2 1/20W_15_5%_0201 SPI_8M_SO 2 1/20W_15_5%_0201 SPI_8M_IO2



@



1 2 3 4



2



/CS VCC IO1 IO3 IO2 CLK GND IO0



8 7 6 5



SPI_8M_IO3 SPI_8M_CLK SPI_8M_SI



RB17 1 RB18 1 RB19 1



CB1 0.1U_6.3V_K_X5R_0201



2 1/20W_15_5%_0201 2 1/20W_15_5%_0201 2 1/20W_15_5%_0201



SPI_IO3 SPI_CLK SPI_SI



+3V_SPI



W25R64JVSSIQ_SO8 1 B



2



UB3 UB1 1 2 3 4



/CS DO (IO1) IO2 GND



VCC IO3 CLK DI (IO0)



SPI_CS1_N



RB20 1



SPI_SO



RB21 1



2 1/20W_15_5%_0201 SPI_16M_SO



2



SPI_IO2



RB23 1



2 1/20W_15_5%_0201 SPI_16M_IO2



3



2 0_0201_5%



@



SPI_16M_CS1_N



1



8 7 6 4 5



/CS DO(IO1)



VCC /HOLD(IO3)



/WP(IO2)



CLK



GND



DI(IO0)



CB3 0.1U_6.3V_K_X5R_0201



B



8 7



SPI_16M_IO3



RB22 1



2 1/20W_15_5%_0201



SPI_IO3



6



SPI_16M_CLK



RB24 1



2 1/20W_15_5%_0201



SPI_CLK



5



SPI_16M_SI



RB25 1



2 1/20W_15_5%_0201



SPI_SI



W25Q128JVSIQ_SO8 W25Q64JVSSIQ_SO8 @



UB1 ,UB2 co-lay



A



A



the diffrent with Base: Security Classification 1.UB1&UB2 ROM CO-LAYOUT Issued Date 2.RB13,RB26 Stuff different as co-layout diffrent



Title



LCFC Highly Confidential Information 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



SPI ROM/TPM



Tuesday, November 10, 2020



Sheet 1



27



of



110



5



4



+1.8VGS



RG2602 10K_0402_5% OPT@



2 RG2603 10K_0402_5% OPT_NS@



2 GP107S



TU117S



[32]



PLT_RST_VGA_N



PCIE4_CRX_GTX0_P PCIE4_CRX_GTX0_N



[14] [14]



PCIE4_CRX_GTX1_P PCIE4_CRX_GTX1_N



PCIE4_CRX_GTX2_P PCIE4_CRX_GTX2_N



[14] [14] [14] [14]



PCIE4_CRX_GTX3_P PCIE4_CRX_GTX3_N



[14] [14]



AC9 AB9 AG6 AG7



PCIE4_CTX_C_GRX1_P PCIE4_CTX_C_GRX1_N



AF7 AE7



2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CRX_C_GTX2_P AD11 2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CRX_C_GTX2_N AC11



PCIE4_CTX_C_GRX2_P PCIE4_CTX_C_GRX2_N



PCIE4_CRX_GTX3_PCG2607 1 PCIE4_CRX_GTX3_NCG2608 1



PCIE4_CTX_C_GRX0_P PCIE4_CTX_C_GRX0_N



AE8 AD8



2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CRX_C_GTX1_P AB10 2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CRX_C_GTX1_N AC10



PCIE4_CTX_C_GRX1_P PCIE4_CTX_C_GRX1_N



PCIE4_CRX_GTX2_PCG2605 1 PCIE4_CRX_GTX2_NCG2606 1



CLK_PCIE_GPU_P CLK_PCIE_GPU_N



2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CRX_C_GTX0_P 2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CRX_C_GTX0_N



PCIE4_CTX_C_GRX0_P PCIE4_CTX_C_GRX0_N



PCIE4_CRX_GTX1_PCG2603 1 PCIE4_CRX_GTX1_NCG2604 1 [14] [14]



[14] [14]



CLK_PCIE_GPU_P CLK_PCIE_GPU_N



PCIE4_CRX_GTX0_PCG2601 1 PCIE4_CRX_GTX0_NCG2602 1 [14] [14]



AC7 AC6



[16] [16] [14] [14]



PLT_RST_VGA_N



CLK_REQ_GPU_N



3



PCIE4_CTX_C_GRX2_P PCIE4_CTX_C_GRX2_N



AE9 AF9



2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CRX_C_GTX3_P AC12 2 OPT@ 0.22U_6.3V_K_X5R_0201 PCIE4_CRX_C_GTX3_N AB12



PCIE4_CTX_C_GRX3_P PCIE4_CTX_C_GRX3_N



PCIE4_CTX_C_GRX3_P AG9 PCIE4_CTX_C_GRX3_N AG10 AB13 AC13 AF10 AE10 AD14 AC14



C



AE12 AF12 AC15 AB15 AG12 AG13 AB16 AC16 AF13 AE13 AD17 AC17 AE15 AF15 AC18 AB18 AG15 AG16 AB19 AC19 AF16 AE16 AD20 AC20 B



AE18 AF18 AC21 AB21 AG18 AG19 AD23 AE23 AF19 AE19 AF24 AE24 AE21 AF21 AG24 AG25 AG21 AG22



TU117S



GP107S



NC



PEX_WAKE_N PEX_RST_N



PEX_DVDD



PEX_CVDD PEX_DVDD_2 PEX_DVDD_3 PEX_DVDD_4 PEX_DVDD_5 PEX_DVDD_6



PEX_CLKREQ_N PEX_REFCLK PEX_REFCLK_N



1



1



AA22 AB23 AC24 AD25 AE26 AE27



D



PEX_HVDD



PEX_TX0 PEX_TX0_N



+1.8VGS @ RG2607 1 2 0_5%_0603



PEX_RX0 PEX_RX0_N



PEX_HVDD_1 PEX_HVDD_2 PEX_HVDD_3 PEX_HVDD_4 PEX_HVDD_5 PEX_HVDD_6 PEX_HVDD_7 PEX_HVDD_8 PEX_HVDD_9 PEX_HVDD_10 PEX_HVDD_11 PEX_HVDD_12 PEX_HVDD_13 PEX_HVDD_14



PEX_TX1 PEX_TX1_N PEX_RX1 PEX_RX1_N PEX_TX2 PEX_TX2_N PEX_RX2 PEX_RX2_N



AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27



1 @



2 0_5%_0603 RG2608



PEX_TX3 PEX_TX3_N PEX_RX3 PEX_RX3_N PEX_TX4 PEX_TX4_N PEX_RX4 PEX_RX4_N



+1.8VGS RG2604



PEX_TX5 PEX_TX5_N



PEX_PLL_HVDD_1 PEX_PLL_HVDD_2



PEX_PLL_HVDD



AA8 AA9



PEX_RX5 PEX_RX5_N



OPT@ CG2610



AA14



2



JUMP_43X79 @



PEX_TX6 PEX_TX6_N PEX_RX6 PEX_RX6_N



1



2



1 @



2 0_5%_0603



C



the PEX PLLs require 1.8V for the N17/GB2D-64/GB2C-64 GPUs and the N18/GB2E-64 GPUs and those supply pins must be switched to the VDD_MAIN supply



Under GPU (below 150mils)



PEX_TX7 PEX_TX7_N PEX_RX7 PEX_RX7_N PEX_TX8 PEX_TX8_N PEX_RX8 PEX_RX8_N PEX_TX9 PEX_TX9_N



PEX LANES 15 - 4 ARE DEFEATURED



QG2601 OPT@ LSI1012XT1G_SC-89-3



1



OPT_NS@ 2



1



GPU_CLKREQ_N



PJ6812



UG1A



0.1U_6.3V_K_X5R_0201



1



AA14:PEX_WAKE#:N18&N17,Leave unconnected and folating



GPU_CLKREQ_PUPWR



1/14 PCI_EXPRESS



D



[16]



+1.0VGS



PEX_DVDD



1



2



0.1U_6.3V_K_X5R_0201



1



2



2 CG2609



2



+1.8V_AON



RG2601 0_0402_5%



@ 1



3



PEX_RX9 PEX_RX9_N PEX_TX10 PEX_TX10_N PEX_RX10 PEX_RX10_N PEX_TX11 PEX_TX11_N PEX_RX11 PEX_RX11_N PEX_TX12 PEX_TX12_N



B



PEX_RX12 PEX_RX12_N PEX_TX13 PEX_TX13_N PEX_RX13 PEX_RX13_N PEX_TX14 PEX_TX14_N PEX_RX14 PEX_RX14_N PEX_TX15 PEX_TX15_N PEX_RX15 PEX_RX15_N PEX_TERMP



AF25



PEX_TERMP



2.49K_0402_1% 2 OPT@



1 RG2605



OPT_NS@



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



GPU_PCIE Interface



Thursday, November 12, 2020 1



Sheet



28



of



110



5



4



3



2



1



UG1J UG1D



4/14 IFPAB



5/14 NC DVI HDMI SL/DL



D



AA15 AB8 AD10 AD7 AE22 AE3 AE4 AF2 AF22 AF3 AF4 AG3 D10 E10 F6 W5 F5



DP



IFPA_L3_N IFPA_L3



TXC/TXC



NC_2 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_21 NC_22 NC_20



AA6



IFPAB_RSET



TXD0/0



IFPA_L2_N IFPA_L2



TXD1/1



W7



IFPA_L1_N IFPA_L1



IFPAB_PLLVDD TXD2/2



IFPA_L0_N IFPA_L0 IFPA_AUX_SDA_N IFPA_AUX_SCL IFPB_L3_N IFPB_L3



TXC



W6



OPT_NS@



Y6



TXD0/3



IFP_IOVDD_1



IFPB_L2_N IFPB_L2



AC4 AC3



UG1K 10/14 MISC2



Y3 Y4 ROM_CS_N



AA2 AA3 [33] [33] [33] [33] [33] [33]



AA1 AB1 AA5 AA4



STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5



STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5



D1 D2 E4 E3 D3 C1



ROM_SI ROM_SO ROM_SCLK



STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5



AB4 AB5



BUFRST_N



D12



ROM_CS0_N



B12 A12 C12



ROM_SI ROM_SO ROM_SCLK



D



ROM_SI [33] ROM_SO [33] ROM_SCLK [33]



D11 BUFRST_N RG2701 2OPT_NS@ 1 10K_0402_5%



AB2 AB3



IFP_IOVDD_2 TXD1/4



IFPB_L1_N IFPB_L1



TXD2/5



IFPB_L0_N IFPB_L0 IFPB_AUX_SDA_N IFPB_AUX_SCL



AD2 AD3 AD1 AE1



OPT_NS@



AD5 AD4



IFPAB OPT_NS@ +1.8V_AON



C



C



UG1L 9/14 XTAL_PLL



L6 M6 F11 N6



XS_PLLVDD SP_PLLVDD GPCPLL_AVDD VID_PLLVDD



2



XS_PLLVDD SP_PLLVDD GPCPLL_AVDD VID_PLLVDD



RG2704 100K_0402_5% OPT_NS@ 1



150mA PEX_HVDD



1



A10



XTAL_IN



C11



RG2703 10K_0402_5% OPT@



XTAL_OUTBUFF



XTAL_SSIN



XTAL_IN



XTAL_OUT



1 OPT@



RC2706



RG2705 100K_0402_5% OPT@



2 RG2707 0_0402_5%



SP_PLLVDD XTAL_IN



1



2



1 4



RG3606



1



1



2 @ 0_0402_5%



VID_PLLVDD



IN



GND2



GND1



OUT



2 3



@ XTAL_OUT_R



Crystal



CG2707



0.47U 6.3V K X5R 0201



CG2706



1



2 OPT@



OPT@



OPT@



0.47U 6.3V K X5R 0201



CG2705



0.47U 6.3V K X5R 0201



2



XTAL_OUT



1



2 0_0402_5% @



B



B10



XTAL_OUT



2 10M_0402_5%



YG2701



Under GPU



RG2718



1



XTALOUT



OPT_NS@



Under GPU



1



C10



2



2



GP107S



EXT_REFCLK_FL



1



2



1



XTALSSIN



2



CG2702



OPT@ CR2703 10U 6.3V M X5R 0402



2



1



OPT@



OPT@



2



1



XS_PLLVDD



2 0_0402_5% @ CG2704



1



RG2713 1



0.47U 6.3V K X5R 0201



30ohms (ESR=0.05) Bead



TU117S



PLLVDD_GPU 4.7U_0402_6.3V6M



LG2701 OPT@ 2 HCB1608KF-300T60_2P OPT@ CG2701 10U 6.3V M X5R 0402



1



2 OPT@



27MHZ_10PF_7V27000050-1 CG2710 OPT@ 9P_50V_B_NPO_0402



1



2 OPT@



B



CG2711 9P_50V_B_NPO_0402



RG2719 GPCPLL_AVDD



2 0_0402_5% @ CG2708



+1.8V_AON 2



+1.8V_AON



OPT@



0.47U 6.3V K X5R 0201



1



1 2



1



the diffrent with Base: 1.3.S540 PLLVDD drictely, S360&V14V15 sepreated



RG2708 10K_0402_5% OPT18@



2



CG2712 10U 6.3V M X5R 0402 OPT_NS@



1 CG2713 0.1U_6.3V_K_X5R_0201 OPT18@



1



2



UG3 ROM_CS0_N ROM_SO



RG2709 1 OPT18@2 33_0402_5% 1 2 0_0402_5% @ RG2710



ROM_CS_N_R ROM_SO_R



1 2 3 4



CS# DO WP# GND



VCC HOLD# CLK DI



8 7 6 5



ROM_SCLK_R RG2711 1 OPT18@2 33_0402_5% ROM_SI_R RG2712 1 OPT18@2 33_0402_5%



ROM_SCLK ROM_SI



W25Q80EWSNIG_SO8 OPT18@



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev GPU_Display Interface 0.1



Wednesday, November 11, 2020 Sheet 1



29



of



110



5



4



3



2



1



UG1B



C



[30,37]



FBA_D[0..63]



[30,37]



FBA_CMD[31..0]



[30,37]



FBA_EDC[7..0]



[30,37]



FBA_DBI[7..0]



FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7



E19 C15 B16 B22 R25 W23 AB26 T26 F19 C14 A16 A22 P25 W22 AB27 T27



GP107S FBA_CMD34



FBA_CLK0 FBA_CLK0_N FBA_CLK1 FBA_CLK1_N



FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7



GP107S



N/A N/A



FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 TU117S



B



OPT_GND_0 OPT_GND_1 OPT_GND_2 OPT_GND_3 OPT_GND_4 OPT_GND_5 OPT_GND_6 OPT_GND_7



N/A N/A



FBA_WCK23 FBA_WCK23_N FBA_WCKB23 FBA_WCKB23_N



N/A N/A



FBA_WCK45 FBA_WCK45_N FBA_WCKB45 FBA_WCKB45_N



N/A N/A



FBA_WCK67 FBA_WCK67_N FBA_WCKB67 FBA_WCKB67_N



GP107S FBA_DQS_RN0 FBA_DQS_RN1



FBA_WCK01 FBA_WCK01_N FBA_WCKB01 FBA_WCKB01_N



FBA_CMD0 C27 FBA_CMD1 C26 FBA_CMD2 E24 FBA_CMD3 F24 FBA_CMD4 D27 FBA_CMD5 D26 FBA_CMD6 F25 FBA_CMD7 F26 FBA_CMD8 F23 FBA_CMD9 G22 FBA_CMD10 G23 FBA_CMD11 G24 FBA_CMD12 F27 FBA_CMD13 G25 FBA_CMD14 G27 FBA_CMD15 G26 FBA_CMD16 M24 FBA_CMD17 M23 FBA_CMD18 K24 FBA_CMD19 K23 FBA_CMD20 M27 FBA_CMD21 M26 FBA_CMD22 M25 FBA_CMD23 K26 FBA_CMD24 K22 FBA_CMD25 J23 FBA_CMD26 J25 FBA_CMD27 J24 FBA_CMD28 K27 FBA_CMD29 K25 +1.35VGS FBA_CMD30 J27 FBA_CMD31 J26 B19 F22 FBA_CMD33 RG2805 2 OPT_NS@ 1 60.4_0402_1% J22 FBA_CMD35 RG2806 2 OPT_NS@ 1 60.4_0402_1%



1



+1.35VGS



RG2801 10K_0201_1% OPT@ FBA_CMD14 FBA_CMD30



FBA_CMD13



FBA_CLK0_P FBA_CLK0_N FBA_CLK1_P FBA_CLK1_N



FBA_CLK0_P FBA_CLK0_N FBA_CLK1_P FBA_CLK1_N



[37] [37] [38] [38]



D18 FBA_WCLK01_P C18 FBA_WCLK01_N A17 A14



FBA_WCLK01_P FBA_WCLK01_N



[37] [37]



D17 FBA_WCLK23_P D16 FBA_WCLK23_N A23 A20



FBA_WCLK23_P FBA_WCLK23_N



[37] [37]



T24 FBA_WCLK45_P U24 FBA_WCLK45_N AC27 Y27



FBA_WCLK45_P FBA_WCLK45_N



[38] [38]



V24 FBA_WCLK67_P V25 FBA_WCLK67_N U27 P27



FBA_WCLK67_P FBA_WCLK67_N



[38] [38]



1



FBA_CMD29



RESET



D24 D25 N22 M22



RG2802 10K_0201_1% OPT@



2



CKE_A



RG2803 10K_0201_1% OPT@



RG2804 10K_0201_1% OPT@



2



FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 FBA_CMD32 FBA_CMD33 FBA_CMD35



D



1



D19 D14 C17 C22 P24 W24 AA25 U25



Note：GDDR5&GDDR6 differrent



2



FBA_DBI0 FBA_DBI1 FBA_DBI2 FBA_DBI3 FBA_DBI4 FBA_DBI5 FBA_DBI6 FBA_DBI7



FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63



1



E18 F18 E16 F17 D20 D21 F20 E21 E15 D15 F15 F13 C13 B13 E13 D13 B15 C16 A13 A15 B18 A18 A19 C19 B24 C23 A25 A24 A21 B21 C20 C21 R22 R24 T22 R23 N25 N26 N23 N24 V23 V22 T23 U22 Y24 AA24 Y22 AA23 AD27 AB25 AD26 AC25 AA27 AA26 W26 Y25 R26 T25 N27 R27 V26 V27 W27 W25



2



D



2/14 FBA



FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63



C



the diffrent with Base: 1. 2.S540 FBA_WCKB0x_N&P connect GDDR6 NC pin, S360&V14V15 NC 3.S540 LG2801 connect 1.8VGS, S360&V14V15 LG2801 connect PEX_HVDD 4.S540 B19&F22&J22 Pin Connect different with S360&V14V15 5.S540 CMD Pin Connect different with S360&V14V15,PULLUP power Different



A14:N18:FBA_WCKB01_N;N17 N/A: N18 Leave unconnected and folating A17:N18:FBA_WCKB01;N17 N/A: N18 Leave unconnected and folating A20:N18:FBA_WCKB23_N;N17 N/A: N18 Leave unconnected and folating A23:N18:FBA_WCKB23;N17 N/A: N18 Leave unconnected and folating Y27:N18:FBA_WCKB45_N;N17 N/A: N18 Leave unconnected and folating AC27:N18:FBA_WCKB45;N17 N/A: N18 Leave unconnected and folating P27:N18:FBA_WCKB67_N;N17 N/A: N18 Leave unconnected and folating U27:N18:FBA_WCKB67N;N17 N/A: N18 Leave unconnected and folating



B



FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5



Place close to BGA



FBA_DQS_RN6



+FB_PLLAVDD



FBA_DQS_RN7



200mA



PEX_HVDD LG2801



1



2



FB_VREF



2



OPT_NS@



2



2



1



2



1



4.7U_0402_6.3V6M



OPT@



CG2806



CG2805



2



4.7U_0402_6.3V6M CG2808 OPT@



2



Near GPU



CG2807



2



1



1U_6.3V_K_X5R_0201



1



1



OPT@



CG2804 OPT@



D23



3.9P_50V_B_NPO_0402



1



1U_6.3V_K_X5R_0201



OPT18@ CG2801



OPT@



2 49.9_0402_1% GPU_FB_VREF



OPT18@ RC2806 1



1



CG2803



Place close to ball



OPT@



H22



1U_6.3V_K_X5R_0201



+FB_PLLAVDD



P22



CG2802



FB_REFPLL_AVDD



Under GPU



F16



OPT@



FB_PLL_AVDD_2



1U_6.3V_K_X5R_0201



FB_PLL_AVDD_1



0.1U_6.3V_K_X5R_0201



These balls are shown as GND in the N18S GeForce Data Sheet. Please follow the below guidelines: a. If doing N18/GB2E-64 alone, connect these balls to GND. b. If doing N18/GB2E-64 and N17/GB2D-64/GB2C-64 co-layout, leave these balls unconnected and floating. c. If doing N17/GB2D-64/GB2C-64 (GDDR5) alone, leave these balls unconnected and floating.



1



30ohms (ESR=0.01) 0603 Bead



1



2



2 HCB1608KF-300T60_2P OPT@



CG2809 22UC_6.3VC_MC_X5RC_0603 OPT@



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev GPU_MEM Interface(A/B) 0.1



Tuesday, November 17, 2020 1



Sheet



30



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



GPU_MEM Interface(C/D) Tuesday, November 10, 2020



Sheet 1



31



of



110



Rev 0.1



5



4



3



2



1



+1.8V_AON +1.8V_AON



+1.8V_AON



UG1M



GPU Address



2 G1



1 0_0402_5% RG3030 2 OPT_NS@ C9 I2CB_SCL C8 I2CB_SDA



D



QG3003B OPT@ 3 PJT7838_SOT363-6



VGA_SMB_DATA



4



S2



D2



1 RG3022 2 OPT_NS@



EC_SMB_DA0



[77,79]



VGA_AC_DET_R



TG3006@



DG3001 2



VRAM_VDDQ_ADJ



[107]



GPIO10_FBVREF_ALTV



[37]



[102]



+3VS +3VALW



1 OPT@



VGA_AC_DET



RG3026 10K_0201_5% GC6@



[79]



RB521CM-30T2R_VMN2M-2



+1.8V_AON



GPIO18_FP_FUSE



GPIO18_FP_FUSE



GPIO18 N18:FP_FUSE;N17 Unused



2



1



[35,84]



PSI_VGA



[35]



1



PSI_VGA TEST_2 VRAM_VDDQ_ADJ VGA_ALERT_N GPIO10_FBVREF_ALTV



0_0402_5%



RG3025 10K_0402_5% GC6@ RG3023 10K_0201_5% OPT_NS@



+3VS



FB_GC6_EN_R



FB_GC6_EN_R [12,35]



3



2



NVVDD_PWM_VID NVVDD_PWM_VID [102] FB_GC6_EN GPU_EVENT_N_R TEST_1 1 TG3005@ GPIO3 N18:Reserved;N17 NWDDS_PWM_VID 1.8VGS_PWR_EN_R RG3010 1 OPT_NS@ 2 0_0402_5% 1.8VGS_PWR_EN 1.8VGS_PWR_EN



D2



[79]



C6 B2 D6 C7 F9 A3 A4 B6 E9 F8 C5 E7 D7 B4 B3 C3 D5 D4 C2 F7 E6 C4 A7 B7



FB_GC6_EN_N 5



QG3004B PJT7838_SOT363-6 GC6@



G2 S2



GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23



NC



2



NC



CG3003 220P_25V_K_X7R_0201 OPT_NS@



EC_WRST_N



[77,79]



GP107S



ADC_IN ADC_IN_N



F4&F3:N17 N18 :Leave UnConnected and floating



1 QG3001 LSI1012XT1G_SC-89-3 OPT_NS@



EC_SMB_CK0



S1



1



1



1.8VGS_PWR_EN



[35,84]



3



JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N NVJTAG_SEL



1.8VGS_PWR_EN_Q



5



D2



GPU_JTAG_TCK AE5 GPU_JTAG_TDI AE6 GPU_JTAG_TDO AF6 GPU_JTAG_TMS AD6 GPU_JTAG_TRST_N AG4 AD9 TESTMODE



QG3002B PJT7838_SOT363-6 GC6@



G2 S2



1 1 1 1



C



FB_GC6_EN



RG3027 1OPT_NS@ 2 0_0201_5% FB_GC6_EN_R



6



4



10K_0402_5% 10K_0402_5%



@TG3001 @TG3002 @TG3003 @TG3004 2 OPT@ 1 RG3003 2 OPT@ 1 RG3004



RG3024 10K_0402_5% GC6@



1.8VGS_PWR_EN



1



3/14 JTAG



QG3004A PJT7838_SOT363-6 GC6@



G1



1



2



RG3012 10K_0402_5% OPT@



RG3011 10K_0402_5% OPT@



UG1N



2



2



2



FB_GC6_EN



D1



+3VALW



OPT_NS@ N18S-G5-A1_BGA603



C



4



6



CG3004 0.01U_0201_10V6K OPT_NS@



3



1



D1



5 THERMDP



1



2 OVERT_N



S1



1



2



I2CB_SCL I2CB_SDA



TU117S



2



1



G2



THERMDN



F12



PLT_RST_VGA_R



VGA_SMB_CLK



Internal Thermal Sensor



QG3003A OPT@ PJT7838_SOT363-6 6



A9 I2CC_SCL B9 I2CC_SDA



2



E12



F3 F4 PLT_RST_VGA_N RG3002 1 2 OPT_NS@ 56_0402_5%



I2CC_SCL I2CC_SDA



D9 VGA_SMB_CLK D8 VGA_SMB_DATA



1



1



CG3002 0.1u_0201_10V6K OPT_NS@



D



I2CS_SCL I2CS_SDA



RG3021 2.2K_0402_5% OPT@ 1



RG3020 2.2K_0402_5% OPT@



GP107S



F10 RG3001 1 OPT18@2 0_0402_5% TS_AVDD TS_AVDD NC 2 F10:N17 NC,N18 TS_AVDD CG3001 OVERT_N A6 1U_6.3V_M_X5R_0201 GPU_TS_VREFAE2 OVERT OPT18@ TS_VREF 1



1



TU117S



2



2



8/14 MISC1



QG3002A



D1



2



G1



PJT7838_SOT363-6 GC6@



1



S1



1.8VGS_PWR_EN_R



OPT_NS@ N18S-G5-A1_BGA603



+1.8V_AON



+1.8V_AON



2



+1.8V_AON



RPG2 2 1



RG3028 10K_0402_5% GC6@



3 2.2K_0404_4P2R_5% 4



CG3007 OPT_NS@



1



I2CB_SCL I2CB_SDA



B



0.1U_6.3V_K_X5R_0201



B



2 2



OPT@



1



RPG3 I2CC_SCL I2CC_SDA



2 1



GPU_EVENT_N_R



3 2.2K_0404_4P2R_5% 4 OPT@



+3VS



3



1



GPU_EVENT_N



GPU_EVENT_N [12]



LSI1012XT1G_SC-89-3 QG3005 GC6@



VRAM_VDDQ_ADJ RG3013 1 OPT_NS@ 2 10K_0402_5%



RG3029 1OPT_NS@ 2 0_0201_5% 2



+1.8V_AON 2 10K_0402_5% RG3014 1 OPT_NS@



1 2



1



+1.8V_AON 0.1U_6.3V_K_X5R_0201



2 SYS_PEX_RST_MON_N



RG3008 1



2 0_0402_5%



PLT_RST_VGA_N



[28]



MC74VHC1G09DFT2G_SC70-5 OPT@ 1



100K_0402_5% RG3006 OPT_NS@



1.8VGS_PWR_EN_R



RG3015 1 OPT@



2 1K_0402_1%



OVERT_N



RG3016 1 OPT@



2 10K_0402_5%



VGA_ALERT_N



RG3017 1 OPT@



2 10K_0402_5%



VGA_AC_DET_R



RG3018 1 OPT@



2 100K_0402_5%



PSI_VGA



2 10K_0402_5% RG3019 1 OPT_NS@



@ 4



RG3032 100K_0402_5% OPT@



A



2



1 2



A



UG3001 Y



A



3



[12] PXS_RST_N



B



1



+1.8VGARST 1 5 PLT_RST_N



CG3005 OPT@



P



PLT_RST_N



GPIO10_FBVREF_ALTVRG3031 1 OPT_NS@ 2 10K_0402_5% RG3009 10K_0402_5% OPT@



G



[17,63,71,78,79]



2



RG3005 0_0402_5%



@



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



GPU_GPIO/JTAG



Tuesday, November 10, 2020 1



Sheet



32



of



110



5



4



+1.8V_AON



GPU



VRAMCFG



FB Memory (GDDR5)



N18S



RG3103 100K_0402_5% OPT_NS@ 1



RG3102 100K_0402_5% OPT_NS@



1



1



STRAP0 STRAP1 STRAP2



STRAP2



STRAP1



STRAP0



MT51J256M32HF-80:B



0x1



L



L



H



Hynix 8Gb



H5GC8H24AJR-R2C



0x2



L



H



L



Samsung 8Gb



K4G80325FC-HC25



0x4



H



L



L



STRAP2



STRAP1



STRAP0



FB Memory (GDDR5)



2



N17S RG3106 100K_0402_5% OPT_NS@



STRAP



Micron 8Gb



MT51J256M32HF-80:B



0x9



L



M



L



Hynix 8Gb



H5GC8H24AJR-R2C



0xA



L



M



H



Samsung 8Gb



K4G80325FC-HC25



0xB



L



H



M



D



1



RG3105 100K_0402_5% OPT_NS@



1



1



RG3104 100K_0402_5% OPT_NS@



STRAP



1



Micron 8Gb



GPU



2



STRAP0 STRAP1 STRAP2



2



[29] [29] [29]



2



2



2



2



X76



RG3101 100K_0402_5% OPT_NS@ D



3



+1.8V_AON



STRAP3



L



L



RG3109 100K_0402_5% OPT_NS@



L



1: SMB_ALT_ADDR ENABLE C



[29] [29] [29]



STRAP3 STRAP4 STRAP5



STRAP3 STRAP4 STRAP5



0: SMB_ALT_ADDR DISABLE 1: DEVID_SEL REBRAND



PCIE_CFG



VGA_DEVICE



0



0



0



0



DEVID_SEL



SMBUS_ALT_ADDR



0



0



0x9E (Default)



1



0x9C (Multi-GPU usage)



(Default)



C



2



2 1



RG3111 100K_0402_5% OPT@



RG3112 100K_0402_5% OPT@



1: PCIE_CFG LOW POWER



0



1: VGA_DEVICE ENABLE



(Default)



1



0: VGA_DEVICE DISABLE



B



VGA_DEVICE



PCIE_CFG



0: PCIE_CFG HIGH POWER



1



2 1



DEVID_SEL



1



0: DEVID_SEL ORIGNAL RG3110 100K_0402_5% OPT@



SMB_ALT_ADDR



1



RG3108 100K_0402_5% OPT_NS@ 1



1



RG3107 100K_0402_5% OPT_NS@



STRAP4



2



2



2



STRAP5



0



3D Device (Class Code 302h)



1



VGA Device (Default)



B



+1.8V_AON 2



ROM_SO RG3114 0_0402_5%



ROM_SCLK



SOR_EXPOSED[3:0]



N18S-G5



L



L



L



XXX0



1:ENABLE 0:DISABLE SOR0/1/2/3 DISABLE



N17S-G5



H



H



M



0000



1::DISABLE



1



@



ROM_SI



1



RG3117 100K_0402_5% OPT17@



N18:ROM_SO&ROM_SI&ROM_SCLK Pull down to Enable The failsafe_OVERT* function N17:SOR_EXPOSED[3:0]



2 RG3119 10K_0402_1% OPT18@



RG3120 100K_0402_5% OPT@



the diffrent with Base: 1.S540 RG3117---- OPT_NS@,S360&V14V15 RG3117---- OPT17@ 1.S540 No RG3113,S360&V14V15 RG3113---- OPT17@



1



2



RG3113 100K_0402_5% OPT_NS@ 1



1



RG3118 100K_0402_5% OPT18@



1



2



ROM_SI ROM_SO ROM_SCLK



ROM_SI ROM_SO ROM_SCLK



2



[29] [29] [29]



RG3116 10K_0402_1% OPT17@ 2



1



RG3115 100K_0402_5% OPT17@



SOR0/1/2/3 DISABLE



2



1



2



GPU_ROM_PUPWR



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



GPU_Strap



Tuesday, November 10, 2020 1



Sheet



33



of



110



5



4



3



2



1



+VGA_CORE



+VGA_CORE UG1C



UG1H 6/14 XVDD



D



G1 G2 G3 G4 G5 G6 G7 H3 H4 H6 J1 J2 J3 J4 J5 J6 J7 K1 K2 K3 K4 K5 K6 K7 L3 L4 M1 M2 M3 M4 M5 M7 N1 N2 N3



XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8 XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16 XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22 XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30 XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35



11/14 VDD 1 of 2



XVDD_36 XVDD_37 XVDD_38 XVDD_39 XVDD_40 XVDD_41 XVDD_42 XVDD_43 XVDD_44 XVDD_45 XVDD_46 XVDD_47 XVDD_48 XVDD_49 XVDD_50 XVDD_51 XVDD_52 XVDD_53 XVDD_54 XVDD_55 XVDD_56 XVDD_57 XVDD_58 XVDD_59 XVDD_60 XVDD_61 XVDD_62 XVDD_63 XVDD_64 XVDD_65 XVDD_66 XVDD_67 XVDD_68 XVDD_69



K10 K12 K14 K16 K18 L13 L15 M10 M12 M16 M18 N11 N13 N15 N17 P14 R11 R13 R15 R17 T10 T12 T16 T18 U13 U15 V10 V12 V14 V16 V18



N4 N5 N7 P3 P4 P6 R1 R2 R3 R4 R5 R6 R7 T1 T2 T3 T4 T5 T6 T7 U3 U4 U6 V1 V2 V3 V4 V5 V6 V7 W1 W2 W3 W4



+VGA_CORE



VDD_01 VDD_02 VDD_03 VDD_04 VDD_05 VDD_07 VDD_08 VDD_10 VDD_11 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_21 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_31 VDD_32 VDD_34 VDD_35 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41



+VGA_CORE



1 CG3230 33P_0402_50V8J OPT_RF@



For RF



CG3258 33P_0402_50V8J OPT_RF_NS@



For RF 2



1



2 D



VDD_SENSE GND_SENSE



F2 F1



NVVDD_VCC_SENSE NVVDD_VSS_SENSE



NVVDD_VCC_SENSE NVVDD_VSS_SENSE



[102] [102]



trace width: 16mils differential voltage sensing. differential signal routing. OPT_NS@ N18S-G5-A1_BGA603



OPT_NS@ N18S-G5-A1_BGA603



C



C



+VGA_CORE



+1.35VGS



UG1G UG1E



7/14 VDD 2 of 2



12/14 FBVDDQ



B26 C25 E23 E26 F14 F21 G13 G14 G15 G16 G18 G19 G20 G21 L22 L24 L26 M21 N21 R21 T21 V21 W21 H24 H26 J21 K21



B



L11 L17 M14 P10 P12 P16 P18 T14 U11 U17



FBVDDQ_01 FBVDDQ_02 FBVDDQ_03 FBVDDQ_04 FBVDDQ_05 FBVDDQ_06 FBVDDQ_07 FBVDDQ_08 FBVDDQ_09 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18



VDD_06 VDD_09 VDD_12 VDD_19 VDD_20 VDD_22 VDD_23 VDD_30 VDD_33 VDD_36



B



OPT_NS@ N18S-G5-A1_BGA603



N17:Use merged-rail design and connect to NVVDD N18:connect to NVVDD



the diffrent with Base: 1.S540No RG3204,S360&V14V15 RG3204---- OPT17@



+1.35VGS



FB_CAL_PD_VDDQ FB_CAL_PU_GND A



FB_CAL_TERM_GND



D22



FB_CAL_PD_VDDQ



RG3201 1 OPT@



2 40.2_0402_1%



C24



FB_CAL_PU_GND



RG3202 1 OPT@



2 40.2_0402_1%



B25



FB_CAL_TERM_GND



RG3203 1 OPT18@2 40.2_0402_1% RG3204 1OPT17@



260.4_0402_1%



CALIBRATION PIN



GDDR5 FB_CAL_x_PD_VDDQ 40.2Ohm FB_CAL_x_PU_GND 40.2Ohm FB_CAL_xTERM_GND 60.4ohm



A



Place near balls OPT_NS@ N18S-G5-A1_BGA603



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



GPU_PWR1



Tuesday, November 10, 2020 1



Sheet



34



of



110



5



4



3



2



1



+1.8VGS



Near GPU 1 RG3302



1



CG3306



S



6



QG3303B LBSS138DW1T1G_SOT363-6



D



OPT_NS@ QG3303A LBSS138DW1T1G_SOT363-6 OPT_NS@



+1.8V_AON



FP_FUSE_GPU UG11 A2



1



B1



VIN GND



Vout ON



A1



FP_FUSE_GPU



B2



GPIO18_FP_FUSE



GPIO18_FP_FUSE



[32]



2



2



D



2



AP22913CN4-7_X1-WLB0909-4 OPT18@



RG3304 10K_0402_5% OPT18@



1



2



1



4.7U_0402_6.3V6M



2



1



4.7U_0402_6.3V6M OPT@ CG3314



2



1



4.7U_0402_6.3V6M OPT@ CG3313



2



1



OPT@ CG3312



1



1U_6.3V_M_X5R_0201



1U_6.3V_M_X5R_0201 OPT@ CG3311



2



1U_6.3V_M_X5R_0201 OPT@ CG3310



CG3309



1



OPT@



2



1U_6.3V_M_X5R_0201



CG3308



1



OPT@



2



1U_6.3V_M_X5R_0201



1



0_0805_5%



S



2 G



RG3303 1 2 @



CG3315 2.2U_6.3V_M_X5R_0201 OPT18@



OPT_NS@ N18S-G5-A1_BGA603



Near GPU



VDD_AON CG3307



2



RG3301 1/16W_2.21K_1%_0402 2 OPT18@



FBVDDQ_PWR_EN



Under GPU



OPT@



1



1



D



1



AB6 FP_FUSE_GPU



FP_FUSE_SRC



2.2U_6.3V_M_X5R_0201 CG3301 OPT18@



NC



FBVDDQ_PWR_EN_Q



FBVDDQ_PWR_EN_N 5 G



TU117S



AB6:FP_FUSE_SRC; N17:N17,Leave unconnected and folating N18:Ref PDG



2



+1.8V_AON



D GP107S



RG3328 470_0402_5% OPT_NS@



RG3327 1/20W_47K_5%_0201



3



2



OPT_NS@ 2 1



2



1



+5VALW



4.7U_0402_6.3V6M



CG3305



4.7U_0402_6.3V6M



CG3303



CG3304



2



OPT_NS@



FP_FUSE_GPU



2



1



OPT17@



2



1



1U_6.3V_K_X5R_0201



VDD18_1 VDD18_2 1V8_AON_1 1V8_AON_2



VDD18 VDD18



1



OPT17@



G8 G9 G10 G12



0.1U_6.3V_K_X5R_0201



TU117S



OPT17@



GP107S



0.1U_6.3V_K_X5R_0201



1



14/14 VDD18



OPT17@



CG3302



UG1F



Discharge +1.35VGS



2 1/10W_0_5%_0603 OPT17@



4



Under GPU +VDD18



PXE_VDD & +1.8V_AON&1.0VGS PXS_PWREN



PXS_PWREN



242.2K_0402_1% PXS_PWR_EN_R



RG3305 1



PXS_PWR_EN_R



OPT@



[104]



1



[12]



RG3306 100K_0402_5% OPT_NS@



1.0VGS_EN



2



1



[35] +3VS



1



PXE_VDD_EN



CG3320 OPT_NS@



C



the diffrent with Base: 1.S540 RG3330----OPT_NS@,S360&V14V15 RG3330----OPT@ +1.0VGS



@ RG3310 1



PXE_VDD_EN_R



2 0_0402_5%



1.8VGS_PWR_EN_D1 3



1



RG3330 1/8W_5.11_1%_0805 OPT@



RG3331 1/8W_5.11_1%_0805 OPT_NS@



RB521CM-30T2R_VMN2M-2 OPT_NS@



RG3329 47K_0402_5% OPT@



+1.0VGS_PWR_EN_Q



D



1



2



+VGA_CORE&+1.25VGS



2



1



2



+5VALW CG3316 0.22U_6.3V_K_X5R_0402 OPT_NS@



2



1 DG3301



1



2



RG3309 10K_0402_5% OPT_NS@ 2



DG3302 OPT@ LBAT54AWT1G_SOT323-3



1



2



RG3334 14K_0402_1% OPT_NS@



2



[103]



1



RG3308 1 0_0402_5%



+1.8V_AON



RG3307 10K_0402_5% OPT@ 1



2 @



1.8VGS_PWR_EN



2 0_0201_5%



2



RB521CM-30T2R_VMN2M-2 OPT@



PXS_PWREN



@



2



1



1



DG3303



2



DGPU_PWROK



RG3312 1



PXE_VDD_EN_R



0.1U_25V_K_X5R_0201



C



DGPU_PWROK RG3311 1OPT_NS@ 2 0_0201_5% 1.0VGS_EN



+1.0VGS_PWR_EN_N



QG3304 AO3402_SOT-23-3 OPT@



G S



2



2 0_0402_5% PXS_PWREN_D 2



1.8VGS_PWR_EN



2 0_0402_5% 1.8VGS_PWR_EN_D2 3



RG3315 1OPT_NS@ 2 0_0402_5%



+1.8VGS



NVVDD_EN



DG3304 OPT@ LBAT54AWT1G_SOT323-3



NVVDD_EN



3



[102]



1



[32,84]



RG3314 1



B



QG3305 LBSS139WT1G_SC70-3 OPT@



1



@ 1.8VGS_PWR_EN



S



2



@ RG3313 1



D



PXE_VDD_EN_R 2 G



RG3317 10K_0402_5% OPT@ PXS_PWREN



1 B



3



1



+3VS



RG3318 100K_0402_1% OPT_NS@ 2



2 0_0402_5% RG3316 1 OPT_NS@



+VGA_CORE



1



1



+5VALW



2 3



D



S



2



NVVDD_EN_Q



4



RG3333 10_0603_5% OPT_NS@



RG3332 47K_0402_5% OPT_NS@



@ RG3322 1



NVVDD_EN_N



DG3305 2 0_0402_5%



GC6_EN



2 1



FBVDDQ_PWR_EN



DGPU_PWROK_EN 3



1.0VGS_PG



2 10K_0402_5% RG3323 1 OPT_NS@



1.0VGS_PG



RG3324 1



@



D



NVVDD_EN 2 G



BAV70W-7-F_SOT323-3 GC6@



5 G



QG3306B LBSS138DW1T1G_SOT363-6



QG3306A OPT_NS@ LBSS138DW1T1G_SOT363-6 S



OPT_NS@



2 0_0201_5%



A



1



1



[103]



DGPU_PWROK



OPT_NS@



RG3326 200K_0402_5% GC6@



CG3319 0.1u_0201_10V6K 2



2



A



DGPU_PWROK



FBVDDQ_PWR_EN [107]



1



[12,102]



6



[12,32] FB_GC6_EN_R



FB_GC6_EN_R



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



GPU_PWR2



Wednesday, November 18, 2020 Sheet 1



35



of



110



5



4



3



2



1



UG1I 13/14 GND



A2 AB17 AB20 AB24 AC2 AC22 AC26 AC5 AC8 AD12 AD13 A26 AD15 AD16 AD18 AD19 AD21 AD22 AE11 AE14 AE17 AE20 AB11 AF1 AF11 AF14 AF17 AF20 AF23 AF5 AF8 AG2 AG26 AB14 B1 B11 B14 B17 B20 B23 B27 B5 B8 E11 E14 E17 E2 E20 E22 E25 E5 E8



D



C



GND_001 GND_006 GND_007 GND_008 GND_010 GND_011 GND_012 GND_013 GND_014 GND_015 GND_016 GND_002 GND_017 GND_018 GND_019 GND_020 GND_021 GND_022 GND_023 GND_024 GND_025 GND_026 GND_004 GND_027 GND_028 GND_029 GND_030 GND_031 GND_032 GND_033 GND_034 GND_035 GND_036 GND_005 GND_037 GND_038 GND_039 GND_040 GND_041 GND_042 GND_043 GND_044 GND_045 GND_046 GND_047 GND_048 GND_049 GND_050 GND_051 GND_052 GND_053 GND_054



GND_059 GND_060 GND_061 GND_062 GND_063 GND_064 GND_065 GND_066 GND_067 GND_071 GND_072 GND_073 GND_074 GND_075 GND_076 GND_077 GND_078 GND_079 GND_080 GND_081 GND_082 GND_083 GND_084 GND_086 GND_087 GND_089 GND_090 GND_091 GND_092 GND_093 GND_094 GND_095 GND_096 GND_097 GND_098 GND_099 GND_100 GND_101 GND_102 GND_104 GND_105 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_003 GND_009



K11 K13 K15 K17 L10 L12 L14 L16 L18 L5 M11 M13 M15 M17 N10 N12 N14 N16 N18 P11 P13 P15 P17 P23 P26 R10 R12 R14 R16 R18 T11 T13 T15 T17 U10 U12 U14 U16 U18 U23 U26 V11 V13 V15 V17 Y2 Y23 Y26 Y5 AA7 AB7



D



C



B



B



OPTIONAL GND:



XVDD AREA



H2 H5 L2



GND_055 GND_058 GND_068



GND_085 GND_088 GND_103 GND_106



P2 P5 U2 U5



PCB ADR/CMD



H23 H25



PWR REFERENCE



GND_056 GND_057



GND_069 GND_070



L23 L25



OPT_NS@ N18S-G5-A1_BGA603



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



GPU_GND



Tuesday, November 10, 2020



Sheet 1



36



of



110



5



4



3



2



1



Lower 32 bits N18S_GDDR5_A_[31_0]



MF=0 No Mirror



UG4



MF=0



the diffrent with Base: 1.S540 GDDR6,S360&V14V15 GDDR5 D



[30,37]



FBA_D[0..63]



[30,37]



FBA_CMD[31..0]



[30,37]



FBA_EDC[7..0]



[30,37]



FBA_DBI[7..0]



FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3



C2 C13 R13 R2



FBA_DBI0 FBA_DBI1 FBA_DBI2 FBA_DBI3



D2 D13 P13 P2



FBA_CLK0_P J12 FBA_CLK0_N J11 FBA_CMD14 J3 FBA_CMD2 FBA_CMD4 FBA_CMD3 FBA_CMD1



H11 K10 K11 H10



FBA_CMD6 FBA_CMD11 FBA_CMD10 FBA_CMD7 FBA_CMD9



K4 H5 H4 K5 J5 A5 U5



RG3501 1 OPT@ RG3502 1 OPT@ RG3503 1 OPT@ [30]



FBA_CLK0_P



[30]



FBA_CLK0_N



FBA_CLK0_P FBA_CLK0_N



RG3504 1 OPT@ RG3505 1 OPT@



2 1/20W_1K_1%_0201 FBA_MF0 2 1/20W_1K_1%_0201 FBA_SEN0 FBA_ZQ0 2 121_0402_1%



J1 J10 J13



MF=1



EDC0 EDC1 EDC2 EDC3



EDC3 EDC2 EDC1 EDC0



DBI0# DBI1# DBI2# DBI3#



DBI3# DBI2# DBI1# DBI0#



MF=1



CK CK# CKE# BA0/A2 BA1/A5 BA2/A4 BA3/A3



BA2/A4 BA3/A3 BA0/A2 BA1/A5



A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC



A10/A0 A11/A6 A8/A7 A9/A1



VPP/NC1 VPP/NC2



2 40.2_0402_1% FBA_CLK0_C 1 CG3502 0.01U_0201_10V6K OPT@ 2



C



[30] [30]



FBA_WCLK01_N FBA_WCLK01_P



[30] [30]



FBA_WCLK23_N FBA_WCLK23_P



FBA_WCLK01_N FBA_WCLK01_P



D5 D4



FBA_WCLK23_N FBA_WCLK23_P



P5 P4



VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36



ABI# RAS# CS# CAS# WE#



CAS# WE# RAS# CS#



WCK01# WCK01



WCK23# WCK23



WCK23# WCK23



WCK01# WCK01



+1.35VGS FBA_VREFC



A10 U10 J14



FBA_CMD13



J2



1



FBA_VREFC



2



RG3506 1/16W_549_1%_0402 OPT@



CG3501 820P_0402_25V7 OPT@



2



VREFD1 VREFD2 VREFC



RESET#



1



FBA_VREFC



1



RG3507 1.33K_0402_1% OPT@ 2



H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14 +1.35VGS



B



1



FBA_VREFC



G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14



VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14



VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19 VSSQ20 VSSQ21 VSSQ22 VSSQ23 VSSQ24 VSSQ25 VSSQ26 VSSQ27 VSSQ28 VSSQ29 VSSQ30 VSSQ31 VSSQ32 VSSQ33 VSSQ34 VSSQ35 VSSQ36



VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14



2



GPIO10_FBVREF_Q



1 3



RG3508 931_0402_1% OPT@



D



S



170-BALL 2 G



SGRAM GDDR5 QG3501 LBSS139WT1G_SC70-3 OPT@



1



[32] GPIO10_FBVREF_ALTV



RG3509 100K_0402_5% OPT@



DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31



A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2



FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D20 FBA_D19 FBA_D22 FBA_D18 FBA_D23 FBA_D16 FBA_D21 FBA_D17 FBA_D30 FBA_D31 FBA_D25 FBA_D24 FBA_D29 FBA_D26 FBA_D28 FBA_D27



BYTE0 D



BYTE1



BYTE2



BYTE3



+1.35VGS



MF SEN ZQ



2 40.2_0402_1% FBA_CMD8 J4 FBA_CMD12 G3 FBA_CMD0 G12 FBA_CMD15 L3 FBA_CMD5 L12



MF=0



DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7



C



A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14



B



H5GQ1H24AFR-T2L_BGA170



2



OPT_NS@



B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



VRAM_A_[31:0]



Tuesday, November 10, 2020 1



Sheet



37



of



110



5



4



3



N18S_GDDR5_B_[63_32]



UG5 MF=0



[30,37]



FBA_D[0..63]



[30,37]



FBA_CMD[31..0]



[30,37]



FBA_EDC[7..0]



[30,37]



FBA_DBI[7..0]



[30]



FBA_CLK1_P



[30]



FBA_CLK1_N



1



MF=0 No Mirror



upper 32 bits



D



2



FBA_CLK1_P RG3604 1 OPT@



2 40.2_0402_1%



FBA_CLK1_N RG3605 1 OPT@



2 40.2_0402_1% FBA_CLK1_C 1 CG3602 0.01U_0201_10V6K OPT@ 2



FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7



C2 C13 R13 R2



FBA_DBI4 FBA_DBI5 FBA_DBI6 FBA_DBI7



D2 D13 P13 P2



FBA_CLK1_P FBA_CLK1_N FBA_CMD30



J12 J11 J3



FBA_CMD18 FBA_CMD20 FBA_CMD19 FBA_CMD17



H11 K10 K11 H10



FBA_CMD22 FBA_CMD27 FBA_CMD26 FBA_CMD23 FBA_CMD25



K4 H5 H4 K5 J5 A5 U5



RG3601 1 OPT@ RG3602 1 OPT@ RG3603 1 OPT@



the diffrent with Base: 1.S540 GDDR6,S360&V14V15 GDDR5



2 1/20W_1K_1%_0201 2 1/20W_1K_1%_0201 2 121_0402_1%



C



[30] [30] [30] [30]



FBA_WCLK45_N FBA_WCLK45_P FBA_WCLK67_N FBA_WCLK67_P



FBA_MF1 FBA_SEN1 FBA_ZQ1



J1 J10 J13



FBA_CMD24 FBA_CMD28 FBA_CMD16 FBA_CMD31 FBA_CMD21



J4 G3 G12 L3 L12



FBA_WCLK45_N FBA_WCLK45_P



D5 D4



FBA_WCLK67_N FBA_WCLK67_P



P5 P4 A10 U10 J14



FBA_VREFC FBA_VREFC



CG3601 820P_0402_25V7 OPT@



MF=1



EDC0 EDC1 EDC2 EDC3



EDC3 EDC2 EDC1 EDC0



DBI0# DBI1# DBI2# DBI3#



DBI3# DBI2# DBI1# DBI0#



MF=1



CK CK# CKE# BA0/A2 BA1/A5 BA2/A4 BA3/A3



BA2/A4 BA3/A3 BA0/A2 BA1/A5



A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC



A10/A0 A11/A6 A8/A7 A9/A1



VPP/NC1 VPP/NC2



DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7



J2



ABI# RAS# CS# CAS# WE#



CAS# WE# RAS# CS#



WCK01# WCK01



WCK23# WCK23



WCK23# WCK23



WCK01# WCK01



VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29 VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36



VREFD1 VREFD2 VREFC



RESET#



2



H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14



VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14



VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19 VSSQ20 VSSQ21 VSSQ22 VSSQ23 VSSQ24 VSSQ25 VSSQ26 VSSQ27 VSSQ28 VSSQ29 VSSQ30 VSSQ31 VSSQ32 VSSQ33 VSSQ34 VSSQ35 VSSQ36



+1.35VGS B



G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14



DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31



A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2



FBA_D32 FBA_D38 FBA_D34 FBA_D39 FBA_D33 FBA_D37 FBA_D35 FBA_D36 FBA_D44 FBA_D42 FBA_D46 FBA_D43 FBA_D45 FBA_D41 FBA_D47 FBA_D40 FBA_D55 FBA_D48 FBA_D52 FBA_D50 FBA_D53 FBA_D49 FBA_D54 FBA_D51 FBA_D61 FBA_D58 FBA_D63 FBA_D59 FBA_D60 FBA_D56 FBA_D62 FBA_D57



BYTE4 D



BYTE5



BYTE6



BYTE7



+1.35VGS



MF SEN ZQ



1 FBA_CMD29



MF=0



VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14



170-BALL SGRAM GDDR5



B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14



C



A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14



B



OPT_NS@ H5GQ1H24AFR-T2L_BGA170



A



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



VRAM_A_[64:32]



Tuesday, November 10, 2020 1



Sheet



38



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



VRAM_B_[31:0]



Tuesday, November 10, 2020



Sheet 1



39



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



VRAM_B_[64:32]



Tuesday, November 10, 2020



Sheet 1



40



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



VRAM_C_[31:0]



Tuesday, November 10, 2020



Sheet 1



41



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



VRAM_C_[64:32]



Tuesday, November 10, 2020



Sheet 1



42



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



VRAM_D_[31:0]



Tuesday, November 10, 2020



Sheet 1



43



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



VRAM_D_[64:32]



Tuesday, November 10, 2020



Sheet 1



44



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



eDP MUX



Tuesday, November 10, 2020



Sheet 1



45



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



NV DDS LOGIC



Tuesday, November 10, 2020



Sheet 1



46



of



110



5



4



LCD EDP Display



2



CI101



High Active 2A



@ 2



CV4 1 @ 2



1



CV5 @



2



2



1



CV6



2



CV7



1



2



EMC_NS@ 0.1U_25V_K_X5R_0201



2



SY6288C20AAC_SOT23-5



CV3 1



10U_25V_M_X5R_0603



CV2 1



3



2



3A_32V_ERBRD3R00X



0.1U_25V_K_X5R_0201



OCB



33P_50V_J_NPO_0201



EN



0.1U_6.3V_K_X5R_0201



[7] PCH_ENVDD



2 10U 6.3V M X5R 0402



4



@



1



RV1 1 2 @ 0_5%_0603



1



1A_32V_ERBRD1R00X Panasonic:LBG:NON-AVL



1 CI102 2



RI101 1



1 CI103 @



2



.047U_0201_6.3V6K



OUT GND



D



1



+LEDVDD



2 10U 6.3V M X5R 0402



2



IN



W=40mils



1



FV1



UV1 5



+3VS_CAMERA



FI101



B+



W=60mils



1



ERBRD1R00X 1.0A 32V 125 mohm max



+3VS



0.1U_6.3V_K_X5R_0201



+LCDVDD_CON



+LCDVDD



1



Camera



the diffrent with Base: 1.S540 EDP connector pindefine different with S360&V14V15 2.S540 no touch screen



+3VS



CV1 0.1U_6.3V_K_X5R_0201 @



3



D



2 10_0402_5%



LI101 EMC_NS@ [14]



USB20_5_P



[14]



USB20_5_N



USB20_5_P



1



USB20_5_N



4



1



2



4



3



2



USB20_5_CON_P



3



USB20_5_CON_N



1



+3VS



DISPOFF_N



CPU_EDP_TX0_P CPU_EDP_TX0_N



[7] [7]



CPU_EDP_TX1_P CPU_EDP_TX1_N



1 1



2 0.1u_0201_10V6KEDP_AUX_CON_P 2 0.1u_0201_10V6KEDP_AUX_CON_N



CPU_EDP_TX0_P CPU_EDP_TX0_N



CV10 1 CV11 1



2 0.1u_0201_10V6KEDP_TX0_CON_P 2 0.1u_0201_10V6KEDP_TX0_CON_N



CPU_EDP_TX1_P CPU_EDP_TX1_N



CV12 1 CV13 1



2 0.1u_0201_10V6KEDP_TX1_CON_P 2 0.1u_0201_10V6KEDP_TX1_CON_N USB20_5_CON_N USB20_5_CON_P DMIC_CLK_CON DMIC_DAT_CON



C



close to connector



DMIC_DAT_CON



DMIC_CLK_CON



DISPOFF_N



2



100P_0402_50V8J



100P_0402_50V8J



2



1



CA84 EMC_NS@



CA87 EMC@



+3VS_CAMERA



INVT_PWM RV8



1



For Camera



+3VS



RV9



1



1



2



CV14 CV15 470P_0402_50V_X7R_0402 470P_50V_K_X7R_0201 2 EMC_NS@ EMC_NS@



1 1



@ @



2 100K_0201_5% EDP_AUX_CON_N



+LCDVDD_CON



2 100K_0201_5% EDP_AUX_CON_P



1



GND1 GND2



31 32



2



1



3



2



S



RV907



1



@



VCC_TS_ON



0_0402_5%



1



2



2



S



Touch_I2C0_SCL



2 0_0402_5%



TS@



CV902 TS@



2



CV901



DMIC_DAT_CON



2 0_0201_5%



DMIC_CLK_CON



[66]



CODEC_DMIC_CLK



[13]



PCH_DMIC_CLK0



+3VS_TS



PCH_TS_RST PCH_TS_INT_N PCH_TS_STOP



1 G



L2N7002KN3T5G_SOT883-3



2



S



2 0_0201_5%



@



1 0_0201_5%



DMIC_DATA



RA82 2



@



1 0_0201_5%



DMIC_CLK



RA17 1



@



2 0_0201_5%



1



2



2



DMIC_CLK



3



QV905 TS@



4



1 2 3 4 5 6 7 8 9 10 GND1 GND2



1



2 UA5 VCCA



B0



A1



B1



GND



+1.8VS



8



VCCB



A0



OE



RA77 0_0201_5%



7



DMIC_DAT_CON



6



DMIC_CLK_CON



5



DMIC_OUTPUT_EN



@



FXMA2102UMX_U-MLP8_1P2X1P4



RA76 100K_0201_5%



A



HIGHS_WS83100-S0171-HF ME@



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



B



2



1 3 2 VCC_TS_ON A



1 2 3 4 5 6 7 8 9 10 11 12



Touch_I2C0_SDA Touch_I2C0_SCL



TS_PWR_DIS D



@



RA80 2



+3VS



DMIC_DATA



JTS1



+3VS_TS [12] PCH_TS_RST [12] PCH_TS_INT_N [12] PCH_TS_STOP



RA81 1



+1.8VS



1



RV908 100_0402_5% TS@



CA88 0.1U_6.3V_K_X5R_0201 EMC_NS@



2 0_0201_5%



CODEC_DMIC_DAT



DMIC 1.8V Level



confirm Pin define with ME TS DISCHARGER



2



RA79 1 @



PCH_DMIC_DAT0



RPA2



2



S



QV902 @



RV905 100K_0402_5% @



L2N7002KN3T5G_SOT883-3 QV904



2



G 1



G D



PCH_I2C0_SCL 3



@



0.1U_6.3V_K_X5R_0201



TS@ 2



1 RV904



1



1



VCC_TS_ON



1



[12]



2



RA78 1 @



[66]



1 2



D



2 0_0402_5%



@



VCC_TS_ON_N_R 0.1U_6.3V_K_X5R_0201



1



RV906



L2N7002KN3T5G_SOT883-3



1



DMIC_CLK



[13]



4 3



Touch_I2C0_SDA



2



L2N7002KN3T5G_SOT883-3 TS@ QV903



RV902 100K_0201_5% TS@ RV903 1 2 @ VCC_TS_ON_N D 0_0402_5%



1



DMIC_DATA



2



1 2 3



1 QV901 LP2301ALT1G_SOT-23-3 TS@



1



1



3



2



CA89 1A_32V_ERBRD1R00X CA90 10U 6.3V M X5R 0402 0.1U_6.3V_K_X5R_0201 @



G



PCH_I2C0_SDA



B



D



G



+3VALW_PCH S



RPV901 2.2K_0404_4P2R_5% TS@



W=40mils



DMIC 3.3V Level



+3VS_TS RV901 1 2 1/10W_0_5%_0603 @



4 3



Touch Screen



+3VS_MIC



FA1



2



+3VS_TS



[12] PCH_I2C0_SCL



+3VS



1 100K_0201_5% CPU_EDP_HPD



+3VS



2



1A_32V_ERBRD1R00X @



HIGHS_FC5AF301-3181H ME@



+3VS_TS



[12] PCH_I2C0_SDA



DMIC



1 RV7



C



FA2



2.2K_0404_4P2R_5%



EMC



+3VS_MIC



+1.8VS



2



[7] [7]



CV8 CV9



1



INVT_PWM



CPU_EDP_HPD



CPU_EDP_AUX_P CPU_EDP_AUX_N



2 10_0402_5%



RPA3



2 0_0201_5%



@



CPU_EDP_AUX_P CPU_EDP_AUX_N



RI102 1



2.2K_0404_4P2R_5%



RV4 1



1



PCH_EDP_PWM



[7] [7]



EXC24CH900U_4P



4 3



2



[7] RV5 1K_0201_5% @ [7] PCH_EDP_PWM



DISPOFF_N INVT_PWM CPU_EDP_HPD



+3VS



1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30



1 2



2



@



0_0201_5%



1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30



1



RV2 1



+LEDVDD



CA86 100P 25V J NPO 0201



EC_BKOFF_N



[79] EC_BKOFF_N



JEDP1



RV3 1/20W_4.7K_5%_0201 @



2 0_0201_5%



@



CA85 100P 25V J NPO 0201



RV10 1



2



PCH_ENBKL



[7,79] PCH_ENBKL



4



3



2



Document Number



Rev eDP_DDI/CAM/DMIC/ISH 0.1



Thursday, November 19, 2020 1



Sheet



47



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



DP



Tuesday, November 10, 2020



Sheet 1



48



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Rev 0.1



HDMI_RETIMER



Tuesday, November 10, 2020



Sheet 1



49



of



110



5



4



HDMI Power



3



2



1



+1.8VS @ RV501



1



2 0_0402_5%



+5VS_HDMI_F QV501 LP2301ALT1G_SOT-23-3



RV502 1 1M_0402_5%



+5VS_HDMI



2



1.1A_8V_1206L110THYR



Ihold:1.1A,Itrip:2.2A, Rmax:0.21ohm



2 G



D



[84] SUSP



1



2



CV501 0.1u_0201_10V6K



[7] CPU_HDMI_TX0_P [7] CPU_HDMI_TX0_N [7] CPU_HDMI_TX1_P



+3VS



[7] CPU_HDMI_TX1_N



G



2



[7] CPU_HDMI_TX2_P [7] CPU_HDMI_TX2_N [7] CPU_HDMI_CLK_P DDPB_CLK_U



6



S



1



D



[7] CPU_HDMI_DDC_CLK



[7] CPU_HDMI_CLK_N



1



HDMI_DET



RV503 20K_0402_5%



D



CPU_HDMI_TX0_P CV502 1



2 0.1u_0201_10V6K



HDMI_TX0_DP_C



CPU_HDMI_TX0_N CV503 1



2 0.1u_0201_10V6K



HDMI_TX0_DN_C



CPU_HDMI_TX1_P CV504 1



2 0.1u_0201_10V6K



HDMI_TX1_DP_C



CPU_HDMI_TX1_N CV505 1



2 0.1u_0201_10V6K



HDMI_TX1_DN_C



CPU_HDMI_TX2_P CV506 1



2 0.1u_0201_10V6K



HDMI_TX2_DP_C



CPU_HDMI_TX2_N CV507 1



2 0.1u_0201_10V6K



HDMI_TX2_DN_C



CPU_HDMI_CLK_P CV508 1



2 0.1u_0201_10V6K



HDMI_CLK_DP_C



CPU_HDMI_CLK_N CV509 1



2 0.1u_0201_10V6K



HDMI_CLK_DN_C



HDMI_TX0_DP_C RV504 1



2 470_0402_5%



HDMI_TX0_DN_C RV505 1



2 470_0402_5%



HDMI_TX1_DP_C RV506 1



2 470_0402_5%



HDMI_TX1_DN_C RV507 1



2 470_0402_5%



HDMI_TX2_DP_C RV508 1



2 470_0402_5%



HDMI_TX2_DN_C RV509 1



2 470_0402_5%



HDMI_CLK_DP_C RV510 1



2 470_0402_5%



HDMI_CLK_DN_C RV511 1



2 470_0402_5%



G



5



L2N7002KDW1T1G_SOT363-6 QV503A



3



Recommend 50 ohm nominal trace impedance with reasonable noise isolation; power supply must be turned off when the CPU power is off



QV502 LSI1012XT1G_SC-89-3



1



1



S



D



3



CPU_HDMI_HPD



[7] CPU_HDMI_HPD



FV501 1



2



2



+5VS



2



HDMI_HPD_PWR



DDPB_DATA_U



D QV503B L2N7002KDW1T1G_SOT363-6



C



QV504



HDMI_CRLS_Q C



1



3



S



4



[7] CPU_HDMI_DDC_DATA



D



2



+3VS



RV512 1 @ 100K_0402_5%



3



G 2



S L2N7002KWT1G_SOT323-3



the diffrent with Base: 1.S540 No HDMI,S360&V14V15 have



B



HDMI_CLK_DN_C



@



1



2



EMC_CMC@ 2



@ 1



HDMI_TX1_DN_C



1



1



2



HDMI_CLK_CON_N



2 0_0402_5%



HDMI_TX0_CON_P



1



RV520



+5VS_HDMI RV521 300_0402_5% EMC_HDMI@



EMC_CMC@ 2



@



2 0_0402_5%



HDMI_TX1_CON_P



2 0_0402_5%



LV503 EXC24CH900U_4P 4 3 4 3



+5VS_HDMI



HDMI_TX1_CON_N



2 0_0402_5%



JHDMI1



@ 1



RV522



HDMI_TX0_DN_C



1



1



2



1



EMC_CMC@ 2



@ RV517



1



RV518 300_0402_5% EMC_HDMI@



2 0_0402_5%



HDMI_TX2_DP_C



1



1



DV501 HDMI_TX1_CON_N 1 1



10 9



HDMI_TX1_CON_N



EMC_CMC@ 2



@ 1



2 0_0402_5%



DV502 1 1



HDMI_DET



10 9



HDMI_TX2_CON_N



9 8



HDMI_TX1_CON_P



DDPB_CLK_U 2 2



9 8



7 7



HDMI_TX2_CON_N



DDPB_DATA_U 4 4



7 7 DDPB_DATA_U



HDMI_TX2_CON_P 5 5



6 6



HDMI_TX2_CON_P



+5VS_HDMI



6 6



5 5 3 3



8



8



DV503 HDMI_CLK_CON_P 1 1



10 9



HDMI_CLK_CON_P



HDMI_CLK_CON_N 2 2



9 8



HDMI_CLK_CON_N



HDMI_TX0_CON_P 4 4



7 7



HDMI_TX0_CON_P



HDMI_TX0_CON_N 5 5



6 6



HDMI_TX0_CON_N



7 9 4 6 1 3 8 5 2



HDMI_DET



HDMI_TX2_CON_N 4 4



3 3



HDMI_TX0_CON_P HDMI_TX0_CON_N HDMI_TX1_CON_P HDMI_TX1_CON_N HDMI_TX2_CON_P HDMI_TX2_CON_N



RV524 300_0402_5% EMC_HDMI@



HDMI_TX1_CON_P 2 2



AZ1045-04F_DFN2510P10E-10-9 EMC_NS@ A



2



HDMI_TX0_CON_N RV523



HDMI_TX2_CON_P



2 0_0402_5%



LV504 EXC24CH900U_4P 4 3 4 3



HDMI_TX2_DN_C



2



HDMI_TX0_DP_C



LV502 EXC24CH900U_4P 4 3 4 3



18



@



1



1



2



RV516



B



RPV501 2.2K_0404_4P2R_5% 3 4



RV514



HDMI_TX1_DP_C RV515 300_0402_5% EMC_HDMI@



1



RV519



1



1



LV501 EXC24CH900U_4P 4 3 4 3 1



HDMI_CLK_CON_P



2 0_0402_5%



2



HDMI_CLK_DP_C



1



2 1



@ RV513



2



EMC



HDMI_CLK_CON_P HDMI_CLK_CON_N



DDPB_CLK_U



+5VS_HDMI



11 10 12



+5V_Power TMDS_Data0+ TMDS_Data0TMDS_Data1+ TMDS_Data1TMDS_Data2+ TMDS_Data2-



SCL SDA



13 17 19



CEC DDC/CEC_Ground Hot_Plug_Detect



TMDS_Data0_Shield TMDS_Data1_Shield TMDS_Data2_Shield TMDS_Clock_Shield TMDS_Clock+ TMDS_Clock-



Utility



GND1 GND2 GND3 GND4



15 16



DDPB_CLK_U DDPB_DATA_U



HDMI_DET



14



20 21 22 23



ALLTO_C128AF-K1935-L ME@



Conector list USE C128AF-K1939-L,Gold Plating diffrent



AZ1045-04F_DFN2510P10E-10-9 EMC_NS@ A



3 3



LCFC Highly Confidential Information



Security Classification



8



Issued Date AZ1045-04F_DFN2510P10E-10-9 EMC_NS@



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



HDMI_CONN



Wednesday, November 18, 2020 Sheet 1



50



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



TYPEC_Controller_PortA Tuesday, November 10, 2020



Sheet 1



51



of



Rev 0.1 110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



TYPEC_MUX_PortA Tuesday, November 10, 2020



Sheet 1



Rev 0.1 52



of



110



5



4



3



2



1



VBUS_P0 +5VALW +5VALW +3VALW



+5V_TYPEC



+3V_TYPEC



pin16



2



Close



1



1 2 16



pin5



1



1



5



2



RU15 47K_0402_5% @ TYPEC_RP_SEL1



1



1



TYPEC_RP_SEL0



RU16 47K_0402_5% @



EC_VBUS_EN



2 0_0402_5% TYPEC_VBUS_EN



1



11 6 7 12 19 24



@ [79]



EC_RP_SEL0



[79]



EC_RP_SEL1



EC_RP_SEL0 RU6 EC_RP_SEL1 RU7



2 0_0402_5% TYPEC_RP_SEL0



1 1



2 0_0402_5% TYPEC_RP_SEL1



@



9 8



VBUS_IN1



VBUS_OUT1



VBUS_IN2



VBUS_OUT2



VCONN_IN



CC2



5V_IN



CC1



EN



#FLT



NC1 NC2 NC3 NC4 NC5



#ATTD #PLG_ORI #DBG



RP_SEL0 RP_SEL1



38W DC change 1.5A



2



CU5



1



2



CU6



1



2



CU7



1



2



1



CU8



2



D



#AUDIO VMON REXT



1



3 4 @



17



2



1 CU19 CU20 220P_25V_K_X7R_0201 220P_25V_K_X7R_0201 2 @ TYPEC_CC2 TYPEC_CC1



15 23



TYPEC_OCP_N



22



TYPEC_ATTD_N



21



TYPEC_PLG_ORI_N



20



TYPEC_DBG_N



10 18 13



TYPEC_AUDIO_N VMON TYPEC_REXT1 RU8 2 100K_0402_1%



TYPEC_OCP_N



[14]



TYPEC_ATTD_N



[79]



TYPEC_PLG_ORI_N[79]



VBUS_P0 RU91



2 69.8K_0402_1% RU10 10K_0402_1%



UU3



Note



Low Active



RU18 mount



1



TYPEC_VBUS_EN



High Active



RU18 47K_0402_5% @



2 0.1U_6.3V_K_X5R_02018



1



2 1U_6.3V_M_X5R_0201 USB20_2_R_P 2 USB20_2_R_N



+3VALW



6



VCC



NC



HSD+



D+



HSD-



D-



JUC1 A1



3



USB20_2_P



USB30_TX3_CON_P A2



5



USB20_2_N



USB30_TX3_CON_N A3 A4



RU33 1 100K_0402_5%



RU17 mount



USBSWITCH_EN_N 1



2



@



2



[79,84,93]



GND



4



TS3USB31ERSER_UQFN8_1P5X1P5



TYPEC_CC1



A5



USB20_2_CON_P



A6



USB20_2_CON_N



A7



2USBSWITCH_EN 1



RU34 1 0_0402_5%



EC_ON_PCH



D



OE#



G



QU1 2



L2N7002KN3T5G_SOT883-3



2 2 2 2



1/16W_220K_5%_0402 1/16W_220K_5%_0402 1/16W_220K_5%_0402 1/16W_220K_5%_0402



S



1 1 1 1



RU39 USB30_RX3_CON_N RU40 USB30_RX3_CON_P RU41 USB30_RX2_CON_N RU42 USB30_RX2_CON_P



A8 A9



1 2



RU37 47K_0402_5%



RU11



1



@



2 47K_0402_5%



TYPEC_DBG_N



TYPEC_PLG_ORI_N



RU12



1



@



2 47K_0402_5%



TYPEC_AUDIO_N



RU38 47K_0402_5% @



VBUS power fault indicator. Output Hi-z: no fault. Drive Low: VBUS power switch is in current limit state or IC is in over temperature condition. PCB pulled up(1) if connected to external controller. Leave floating if not used. DU1



4



USB30_RX2_CMC_N



5



USB30_RX2_CMC_P



DU4&DU5DU6&DU7 SC400006500 Chane to SC400006510 VBUS_P0



8



Line-3



GND1 GND2



SSTXn1



SSRXn1



Vbus1



Vbus4



CC1



SBU2



Dp1



Dn2



Dn1



Dp2



SBU1



CC2



Vbus2



ATOB_066-12A1-3211 ME@



USB30_RX3_CON_N



B7



USB20_2_CON_N



B6



USB20_2_CON_P



B5



TYPEC_CC2



B4



SSTXp2



GND2



USB30_RX3_CON_P



B10



B8



SSTXn2



SSRXp2



B11



B9



Vbus3



SSRXn2



B3



USB30_TX2_CON_N



B2



USB30_TX2_CON_P



B1



GND3



RU23 1 EMC_NS@



USB20_2_R_P



1



USB20_2_R_N



4



2 0_0402_5%



B



EMC@



1



2



4



3



2



USB20_2_CON_P



3



USB20_2_CON_N



2 0_0402_5%



@ 1



@ 2 0_0402_5%



RU29



1



2 0_0402_5%



1 DU5 AZ5425-01F_DFN1006P2E2 EMC_NS@



LU4 [14]



USB30_TX3_N



[14]



USB30_TX3_P



USB30_TX3_N



1



USB30_TX3_P



4



1



EMC_NS@ 2 2



4



3



LU1 USB30_TX3_CMC_N USB30_TX3_CMC_P



3



[14]



USB30_TX2_N



[14]



USB30_TX2_P



USB30_TX2_N



1



USB30_TX2_P



4



EXC24CH900U_4P @ 1 2 0_0402_5% RU26



1



EMC_NS@ 2 2



4



3



5 3



TYPEC_CC1



8



DU6 AZ5425-01F_DFN1006P2E2 EMC_NS@



USB30_TX2_CMC_P



@ @



TYPEC_CC2



USB30_RX3_CMC_P



3



USB30_TX2_CMC_N



EXC24CH900U_4P @ 1 2 0_0402_5% RU30



1



RU31



1



LU3 [14]



CU23



1



EMC_NS@ 2



DU7 AZ5425-01F_DFN1006P2E2 EMC_NS@



CU24



1



EMC_NS@ 2



[14]



USB30_RX3_P USB30_RX3_N



USB30_RX3_P



1



USB30_RX3_N



4



1 4



EMC_NS@ 2 2 3



USB30_RX3_CMC_P [14]



USB30_RX2_P



USB30_RX3_CMC_N [14]



USB30_RX2_N



USB30_RX2_P



1



USB30_RX2_N



4



Issued Date



Deciphered Date



3



3



USB30_RX2_CMC_N



Title



S360-TGL



2014/07/01



Date: 3



4



USB30_RX2_CMC_P



EXC24CH900U_4P @ 2 0_0402_5%



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 4



EMC_NS@ 2 2



RU32 1



LCFC Highly Confidential Information 2012/07/01



1



A



3



EXC24CH900U_4P @ 1 2 0_0402_5% RU28



Security Classification



2 0_0402_5%



2 0_0402_5% LU2



AZ1143-04F-R7G_DFN2510P10E10 EMC@



5



SSRXp1



EMC Request



220P_25V_K_X7R_0201



Line-4



USB30_RX3_CMC_N



USB20_2_R_N



RU27



220P_25V_K_X7R_0201



NC4



4



USB20_2_R_P



2 0_0201_5%



1



6



Line-2



NC3



USB30_TX2_CMC_N



2 0_0201_5%



@



RU25



DU4 AZ5425-01F_DFN1006P2E2 EMC_NS@



1



USB30_RX3_CMC_P



NC2



USB30_TX2_CMC_P



2



USB20_2_CON_P USB20_2_CON_N



1



7



1



@



USB20_2_N RU22 1



2



3



USB20_2_P RU21 1



2



DU3 EMC_NS@



2



USB30_RX3_CMC_N



Line-1



USB20_2_P USB20_2_N



1



USB30_TX3_CMC_N



2



9



2 0.33U_25V_K_X5R_0402 USB30_RX2_CON_N 2 0.33U_25V_K_X5R_0402 USB30_RX2_CON_P 2 0.1U_25V_K_X5R_0402 USB30_TX2_CON_N 2 0.1U_25V_K_X5R_0402 USB30_TX2_CON_P



[14]



1



Line-4



USB30_TX3_CMC_P



2



DU2 USB30_TX2_CMC_N



1 1 1 1



RU24 1 EMC_NS@



2



Line-3



NC4



NC1



CU15 CU16 CU17 CU18



SSTXp1



VBUS_P0



EXC24CH900U_4P



2



NC3



1



AZ1143-04F-R7G_DFN2510P10E10 EMC@



10



USB30_RX2_CMC_N USB30_RX2_CMC_P USB30_TX2_CMC_N USB30_TX2_CMC_P



A12



B12



GND4



1



Line-2



GND2



USB30_TX2_CMC_P



2 0.33U_25V_K_X5R_0402 USB30_RX3_CON_N 2 0.33U_25V_K_X5R_0402 USB30_RX3_CON_P 2 0.1U_25V_K_X5R_0402 USB30_TX3_CON_N 2 0.1U_25V_K_X5R_0402 USB30_TX3_CON_P



[14]



1



6



1 1 1 1



2



USB30_RX2_CMC_P



NC2



CU11 CU12 CU13 CU14



2



7



Line-1



1



USB30_RX2_CMC_N



NC1



1



9



2



USB30_TX3_CMC_N



2



10



USB30_RX3_CMC_N USB30_RX3_CMC_P USB30_TX3_CMC_N USB30_TX3_CMC_P



LU5



AZ5725-01F.R7GR_DFN1006P2X2



USB30_TX3_CMC_P



GND1



A



USB30_RX2_CON_PA11



GND1



2



2



RU36 47K_0402_5% @



2



RU20 47K_0402_5% @



B



TYPEC_ATTD_N



1



TYPEC_OCP_N



USB30_RX2_CON_NA10



+3V_TYPEC



1



2



RU35 47K_0402_5%



1



2



RU19 47K_0402_5%



Add resistor 0701



+3V_TYPEC



1



+3V_TYPEC



1



+3V_TYPEC



C



7



GND5 GND6 GND7 GND8



CU26



Power switch enable pin



1



3



1



Chip enable control.High acitve.PCB pulled up if not connected to SOC



RU17 47K_0402_5% @ 2



CU25



GND10 GND9



VBUS_P0



C



GND6 GND5



+3VALW



+3V_TYPEC



GND1 GND2 GND3 GND4



2



14



2



2



RU14 47K_0402_5% @



[79]



RU5



1



UU2 RTS5467A-GRT_QFN24_4X4 CU29



@



Type-C current mode selection {RP_SEL1,RP_SEL0} 2'b00: Standard USB mode. 2'b01: Standard USB mode. 2'b10: 1.5A current mode. 2'b11: 3A current mode PCB pull selection if not connected to SOC



CU4 @



1



1 2



@



1 CU28



+3V_TYPEC



RU13 47K_0402_5% @ 2



CU21



0.1u_0201_10V6K



Close



10U_0603_10V6K



+3V_TYPEC



2



0.1u_0201_10V6K



the diffrent with Base: 1.S540 No type-c USB3.0 only,S360&V14V15 have



1 CU22



2



E-PAD



CU10 0.1u_0201_10V6K



1



CU3



25



1 2



2



+5V_TYPEC



10U_0603_10V6K



4.7U_0402_6.3V6M



CU9



1



2



CU27



GND



2



1



2



2 0_0402_5%



@



D



CU2



1



1



+



2



RU2



@



0.47U_0402_25V6K



RU4



0.47U_0402_25V6K



1 CU1 @



0.47U_0402_25V6K



2 0_0402_5%



0.47U_0402_25V6K



1



+3VS



4.7U_0805_25V6-K



2 0_0402_5%



+5VS



10U_0805_25V6K



RU31



0.1u_0201_10V6K



2 0_0402_5%



47U_6.3V_M_X5R_0805_H1.25



RU11



150U_B2_6.3VM_R35M



@ @



2



Document Number



Rev 0.1



TYPEC_CONN_PortA Tuesday, November 17, 2020 1



Sheet



53



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



TYPEC_Controller_PortB Tuesday, November 10, 2020



Sheet 1



54



of



Rev 0.1 110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



TYPEC_MUX_PortB Tuesday, November 10, 2020



Sheet 1



Rev 0.1 55



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



TYPEC_CONN_PortB Tuesday, November 10, 2020



Sheet 1



Rev 0.1 56



of



110



A



B



C



D



E



USB3.0 PORT +5VALW +USB_VCCA 1 1



CU601 1U_6.3V_M_X5R_0201



+USB_VCCA +USB_VCCA



UU601 2



5



IN



OUT GND



EC_USB_ON_N 4



[58,79] EC_USB_ON_N



ENB



OCB



close to USB Conn



JUA1 1



USB30_TX1_CON_P



1 2



1 USB_OC2_N



3



USB_OC2_N



[7] 2



USB30_TX1_CON_N USB20_4_CON_P



1 CU602 100U_1206_6.3V6M



2



CU603 1U_0402_16V6K @



USB20_4_CON_N USB30_RX1_CON_P USB30_RX1_CON_N



SY6288D20AAC_SOT23-5



9 1 8 3 7 2 6 4 5



Low Active 2A



StdA_SSTX+ VBUS StdA_SSTXD+ GND_DRAIN DStdA_SSRX+ GND_1 StdA_SSRX-



GND_2 GND_3 GND_4 GND_5



10 11 12 13



ALLTO_C19043-10905-L ME@



1



RU601



2



@



LU601 [14]



USB20_4_P



USB20_4_P



1



EMC



2 0_0402_5%



close to USB Conn



EMC@



1



USB20_4_CON_P



2



2



DU601 USB30_RX1_CON_N 10



[14]



USB20_4_N



USB20_4_N



4



4



USB20_4_CON_N



3



3



USB30_RX1_CON_P



9



USB30_TX1_CON_N



7



USB30_TX1_CON_P



6



EXC24CH900U_4P RU602 1



2 0_0402_5%



@



NC1



Line-1



NC2



Line-2



NC3



Line-3



NC4



Line-4



@ RU603



1



2



LU602 EMC_NS@



USB30_RX1_N



1



USB30_RX1_N



4



1



2



4



3



2



USB30_RX1_CON_P



3



USB30_RX1_CON_N



4



USB30_TX1_CON_N



5



USB30_TX1_CON_P



AZ1143-04F-R7G_DFN2510P10E10 EMC@



USB20_4_CON_P



EXC24CH900U_4P @ 2 0_0402_5% RU604 1



3



+USB_VCCA USB20_4_CON_N 1



3



USB30_RX1_CON_P



DU603



1



DU602



2



[14]



USB30_RX1_P



1



USB30_RX1_P



2



8



GND2 [14]



USB30_RX1_CON_N



3



GND1



2 0_0402_5%



1



@



[14] USB30_TX1_N



CU604 USB30_TX1_N



0.1U_6.3V_K_X5R_0201 USB30_TX1_C_N 1 2



LU603 EMC_NS@ 1 4



1



2



4



3



USB30_TX1_CON_P



2



3



USB30_TX1_P



2 0_0402_5%



2



[14] USB30_TX1_P



CU605 0.1U_6.3V_K_X5R_0201 USB30_TX1_C_P 1 2



1



2



RU605



AZ5725-01F.R7GR_DFN1006P2X2 EMC_NS@



AZ5515-02FPR7GR_DFN1006P3X EMC@



USB30_TX1_CON_N



3



EXC24CH900U_4P @ 2 0_0402_5% RU606 1



4



4



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



A



B



C



D



Document Number



USBA_PortA



Tuesday, November 10, 2020



Rev 0.1 Sheet E



57



of



110



5



4



3



2



1



USB2.0 Port and CMC&TVS&CAP MOVE to SUB Board



D



D



USB2.0 PORT +5VALW



1



+USB_VCCB



CU401 1U_6.3V_M_X5R_0201 UU401



2 5



IN



OUT



C



GND [57.79] EC_USB_ON_N



EC_USB_ON_N



4



ENB



OCB



1 C



2 3



USB_OC1_N



USB_OC1_N



[7]



SY6288D20AAC_SOT23-5



Low Active 2A



the diffrent with Base: 1.S540 No USB2.0 only,S360&V14V15 have



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



USBA_PortB



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



58



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



USBA_PortC



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



59



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



USB HUB



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



60



of



110



5



4



3



HDD Power



2



HDD Without Redriver



+5VS



+5VS_HDD JK1 1



D



1



2



2



2



CK6 RF_NS@



the diffrent with Base: 1.S540 No HDD,S360&V14V15 have



2



CK7 RF_NS@



1



2



33P_0402_50V8J



2



CK5



1



33P_0402_50V8J



2



CK4



1



0.1u_0201_10V6K



2



CK2 @



1



10U_0603_10V6K



CK1 @



1



22U_10V_M_X5R_0603



@



1



22U_10V_M_X5R_0603



JUMP_43X39



[14]



SATA_PTX_DRX0_P



RK1 0_0201_5% CK8 SATA_PTX_DRX0_P SATA_NRE@ 1 2SATA_PTX_DRX0_R_P SATA_NRE@ 1



2 0.01U_6.3V_K_X7R_0201



[14]



SATA_PTX_DRX0_N



RK2 0_0201_5% CK9 SATA_PTX_DRX0_N SATA_NRE@ 1 2SATA_PTX_DRX0_R_N SATA_NRE@ 1



2 0.01U_6.3V_K_X7R_0201 SATA_PTX_DRX0_CON_N



[14]



SATA_PRX_DTX0_N



RK3 0_0201_5% CK10 SATA_PRX_DTX0_N SATA_NRE@ 1 2SATA_PRX_DTX0_R_N SATA_NRE@ 1



2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX0_CON_N



[14]



SATA_PRX_DTX0_P



RK4 0_0201_5% CK11 SATA_PRX_DTX0_P SATA_NRE@ 1 2SATA_PRX_DTX0_R_P SATA_NRE@ 1



2 0.01U_6.3V_K_X7R_0201



SATA_PTX_DRX0_CON_P D



SATA_PRX_DTX0_CON_P



+3VS



C



1



C



1



HDD with Redriver Only For 17' Type



RK5 1/20W_4.7K_5%_0201 SATA_8527@



ME@ +5VS_HDD



2



Add RK31 0627



CO-design with PI3EQX6741STZDEX



[14] SATA_PTX_DRX0_P [14] SATA_PTX_DRX0_N [14] SATA_PRX_DTX0_P [14] SATA_PRX_DTX0_N



UK1



2 0.1u_0201_10V6K



SATA_PTX_DRX0_P SATA_RE@ SATA_PTX_DRX0_N SATA_RE@



CK15 1 CK16 1



2 0.01U_6.3V_K_X7R_0201SATA_PTX0_P 1 2 0.01U_6.3V_K_X7R_0201SATA_PTX0_N 2



SATA_PRX_DTX0_P SATA_RE@ SATA_PRX_DTX0_N SATA_RE@



CK17 1 CK18 1



2 0.01U_6.3V_K_X7R_0201SATA_PRX0_P 5 2 0.01U_6.3V_K_X7R_0201SATA_PRX0_N 4



RK22 0_0201_5% 2 SATA_8527@ 1



7



A_EQ1 A_EQ2 B_EQ1 B_EQ2



17 18 19 13



SATA_RE_GND



3 21



B



+3VS



EN



VDD1 VDD2



A_INP A_INN



REXT DEW



B_OUTP B_OUTN A_EQ1 A_EQ2 B_EQ1 B_EQ2



A_DE B_DE A_OUTP A_OUTN



GND1 EPAD



B_INP B_INN



10 20



SATA_PRX_DTX0_CON_P SATA_PRX_DTX0_CON_N



1



1



SATA_RE_EN



CK14 1



6 16



REXT DEW



9 8



A_DE B_DE



15 14



SATA_R_PTX0_P SATA_R_PTX0_N



SATA_RE@ SATA_RE@



CK19 1 CK20 1



2 0.01U_6.3V_K_X7R_0201 SATA_PTX_DRX0_CON_P 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_DRX0_CON_N



11 12



SATA_R_PRX0_P SATA_R_PRX0_N



SATA_RE@ SATA_RE@



CK21 1 CK22 1



2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX0_CON_P 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX0_CON_N



2



@



+3VS



CK12 0.1u_0201_10V6K SATA_RE@



2



CK13 0.01U_0201_10V6K SATA_RE@



SATA_PTX_DRX0_CON_N SATA_PTX_DRX0_CON_P



JHDD1 1 2 3 4 5 6 7 8 9 10



1 2 3 4 5 6 7 8 9 10



GND2 GND1



12 11



HIGHS_FC5AF101-2931H



B



PS8527CTQFN20GTR2A2_TQFN20_4X4 SATA_8527@



1/20W_4.7K_5%_0201 2 RK6



1 @



A_EQ1



1/20W_4.7K_5%_0201 2 RK7



1SATA_RE@ RK6,RK7,RK26,RK27 avoid the two IC different EQ level ,reserve



1/20W_4.7K_5%_0201 2 RK8



1 @



1/20W_4.7K_5%_0201 2 RK10



1 @



A_EQ2



1/20W_4.7K_5%_0201 2 RK9



B_EQ1



1/20W_4.7K_5%_0201 2 RK11



1SATA_RE@



1SATA_RE@



A_EQ A_EM A_OS



1/20W_4.7K_5%_0201 2 RK12



1 @



B_EQ2



1/20W_4.7K_5%_0201 2 RK14



1 @



REXT



1/20W_4.7K_5%_0201 2 RK16



1 @



DEW



1/20W_4.7K_5%_0201 2 RK13



1SATA_8527@



4.99K_0402_1% 1 RK15



2SATA_8527@



1/20W_4.7K_5%_0201 2 RK17



1SATA_8527@



1 1/20W_4.7K_5%_0201 2 RK18 SATA_8527@



A_DE 1/20W_4.7K_5%_0201 2 RK19



1SATA_8527@



1 1/20W_4.7K_5%_0201 2 RK20 SATA_8527@



B_DE 1/20W_4.7K_5%_0201 2 RK21



1SATA_RE@



REXT：external res for output swiing adjustment it canbe left open or tie to GND,internally generated bias current be used and the output is as default swing setting;



Equalization adjustment Output emphasis adjustment for Channel A. Allows analog resistive adjustment of emphasis Channel A output swing adjustment. Allows analog resistive adjustment of output swing leve



the pin canbe connected 4.99k to GND,the output swing willbe at the default value with Reference to the ex RES DEW:De-emphasis width setting for A&B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



HDD



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



61



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



ODD



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



62



of



110



4



3



1



@



2 0_5%_0603



PCIE_PTX_DRX5_N PCIE_PTX_DRX5_P



[14] [14]



PCIE_PRX_DTX6_N PCIE_PRX_DTX6_P



[14] [14]



PCIE_PTX_DRX6_N PCIE_PTX_DRX6_P



[14] [14]



PCIE_PRX_DTX7_N PCIE_PRX_DTX7_P



[14] [14]



PCIE_PTX_DRX7_N PCIE_PTX_DRX7_P



2



PCIE_PRX_DTX8_P PCIE_PRX_DTX8_N



[14] [14]



PCIE_PTX_DRX8_N PCIE_PTX_DRX8_P



[16] [16]



2



PCIE_PRX_DTX5_N PCIE_PRX_DTX5_P CK201 1 CK202 1



2 0.22U_6.3V_K_X5R_0201 2 0.22U_6.3V_K_X5R_0201



PCIE_PTX_C_DRX5_N PCIE_PTX_C_DRX5_P PCIE_PRX_DTX6_N PCIE_PRX_DTX6_P



CK203 1 CK204 1



2 0.22U_6.3V_K_X5R_0201 2 0.22U_6.3V_K_X5R_0201



C



[14] [14]



@



PCIE_PTX_C_DRX6_N PCIE_PTX_C_DRX6_P PCIE_PRX_DTX7_N PCIE_PRX_DTX7_P



CK205 1 CK206 1



2 0.22U_6.3V_K_X5R_0201 2 0.22U_6.3V_K_X5R_0201



PCIE_PTX_C_DRX7_N PCIE_PTX_C_DRX7_P PCIE_PRX_DTX8_P PCIE_PRX_DTX8_N



CK207 1 CK208 1



2 0.22U_6.3V_K_X5R_0201 2 0.22U_6.3V_K_X5R_0201



PCIE_PTX_C_DRX8_N PCIE_PTX_C_DRX8_P CLK_PCIE_SSD_N CLK_PCIE_SSD_P



CLK_PCIE_SSD_N CLK_PCIE_SSD_P



@ [14]



SSD_SATA_PCIE_DET1_N



RK202



1



2 0_0402_5%



SSD_DET1



+3VS_SSD JSSD1 GND15 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57



3.3V_1 3.3V_2 N/C_2 N/C_3 DAS/DSS#(I/O)/LED1#(I)(0/3.3V) 3.3V_3 3.3V_4 3.3V_5 3.3V_6 N/C_4 N/C_5 N/C_6 N/C_7 N/C_8 N/C_9 N/C_10 N/C_11 N/C_12 DEVSLP(O) N/C_13 N/C_14 N/C_15 N/C_16 N/C_17 PERST#(O)(0/3.3V) or N/C CLKREQ#(I/O)(0/3.3V) or N/C PEWAKE#(I/O)(0/3.3V) or N/C N/C_18 N/C_19



N/C_1 PEDET(NC-PCIe/GND-SATA) GND12 GND13 GND14



SUSCLK(32kHz)(O)(0/3.3) 3.3V_7 3.3V_8 3.3V_9 GND16



2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58



RK203 @



C



PCH_SATA_DEVSLP_R RK204 1



@



2 0_0201_5%



SSD_PLT_RST_N RK205 SSD_CLKREQ_Q_N RK206 PEWAKE# 1 TK201 @



@ @



2 0_0402_5% 2 0_0402_5%



+3VS_SSD 68 70 72 74 CK214



1



77



ARGOS_NASM0-S6705-TSH4 ME@



@



2



1 1



CK213 @



1



2



0.1U_6.3V_K_X5R_0201



67 69 71 73 75



GND1 GND2 PERn3 PERp3 GND3 PETn3 PETp3 GND4 PERn2 PERp2 GND5 PETn2 PETp2 GND6 PERn1 PERp1 GND7 PETn1 PETp1 GND8 PERn0/SATA-B+ PERp0/SATA-BGND9 PETn0/SATA-APETp0/SATA-A+ GND10 REFCLKn REFCLKp GND11



76



10U 6.3V M X5R 0402



SSD_DET# 0--SATA 1--PCIE



B



D



10K_0201_5%



[14] [14]



2



CK212



1



0.1U_10V_K_X7R_0402



PCIE_PRX_DTX5_N PCIE_PRX_DTX5_P



@



CK211



1



0.1U_6.3V_K_X5R_0201



2



CK210



1



10U 6.3V M X5R 0402



1



10U 6.3V M X5R 0402



CK209



[14] [14]



+3VS_SSD



1



RK201



D



1



the diffrent with Base MODULE: 1.Module add RK206 Stuff pullup 3vs for SSD_CLKREQ1_N, add RK205 noStuff pullup 3vs for SATA_DEVSLP1 S360&V14V15 remove 2.Module no rk205&rk206,S360&V14&V15 add for debug



+3VS



Min 3A



2



2



5



PCH_SATA_DEVSLP1 [14]



PLT_RST_N SSD_CLKREQ1_N



[17,32,71,78,79] [16]



B



+3VS_SSD SSD_CLKREQ1_N RC207



SSD_SATA_PCIE_DET1_N



CK215



1



1



2 10K_0201_5%



2 0.1U_10V_K_X7R_0402 EMC_NS@



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



SSD



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



63



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



EMMC



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



64



of



110



5



4



3



2



1



FP Power Control @ RI8 1 FP_PWR



+3VL QI3 LP2301ALT1G_SOT-23-3 D



S



1FPR_PWR_OUT FP@



3



1



2



2 RI4 1 @



2



CI3 0.1U_6.3V_K_X5R_0201 @



FPR_PWR_EN_R



2 0_0201_5%



2



2



1



CI1 1 0.047U_0402_16V_X7R_0402 FP@



RI6 1 @ 0_0201_5%



2



CI2 0.1u_0201_10V6K FP@



1



LI1



EMC_NS@



1



2



4



3



USB20_7_P



4



GPIO_AL0_R



FP_RESETN_R 1



2 RI12 1 @ 1/20W_4.7K_5%_0201



1



FPR_DELINK_R



2



RI11 1/20W_47K_1%_0201 FP@



RI13 1/20W_4.7K_5%_0201 @ 2



RI10 100K_0201_5% @



C



RI7 330_0402_1% FP@



QI1 FP@ 32



2



S



USB20_7_CON_P



3



FP_PWR



CI4 0.1U_6.3V_K_X5R_0201 @



D



D



2



2



USB20_7_CON_N



2



EXC24CH900U_4P @ 2 0_0402_5% RI9 1



1



3 1



USB20_7_P



1



1 2



1



1 G



RI1 100K_0201_5% FP@



L2N7002KN3T5G_SOT883-3



2



FPR_PWR_EN_N_R



D



1 G QI2 S FP@



the diffrent with Base: 1.S540 No Fingerprinter,S360&V14V15 have



2



L2N7002KN3T5G_SOT883-3



B



[14]



USB20_7_N



FPR_PWR_EN



FP_PWR



[79] FPR_PWR_EN



USB20_7_N



FPR_PWR_EN_N



RI3 100K_0201_5% FP@



C



[14] 2 0_0201_5%



G



+3VL



RI5 1 @



1



D



RI2 1/20W_200K_5%_0201 FP@



2 0_0402_5%



EMC close to Conn



B



FP_PWR



JFP1 10 9



USB20_7_CON_N DI1



FP_RESETN_R 7 GPIO_SCL_R



6



NC2



Line-2



NC3



Line-3



NC4



Line-4 GND1 GND2



2



GPIO_AL0_R



4



FP_RESETN_R



5



GPIO_SCL_R



USB20_7_CON_P



DI2



USB20_7_CON_N USB20_7_CON_P



2



9



Line-1



FPR_DELINK_R



1



GPIO_AL0_R



NC1



1



[12.79] [79] [12] [79]



FPR_DELINK_R GPIO_AL0_R FP_RESETN_R GPIO_SCL_R



FPR_DELINK_R GPIO_AL0_R FP_RESETN_R GPIO_SCL_R



3 8



AZ1143-04F-R7G_DFN2510P10E10 EMC_FP@



8 7 6 5 4 3 2 1



8 7 6 5 4 3 2 1 HIGHS_FC5AF081-2931H ME@



3



FPR_DELINK_R10



GND2 GND1



AZ5515-02FPR7GR_DFN1006P3X EMC_FP@



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



FPR



Tuesday, November 17, 2020



Rev 0.1 Sheet 1



65



of



110



5



4



2



DVDD_IO +3VS



DVDD DVDD_IO



@



+5VS



+5VA



+5VD +5VS



2 0_0402_5%



@



2



0_5%_0603



2



2



1



2



1



2



CA13 0.1U_6.3V_K_X5R_0201



RA13 1



1



CA12 0.1U_6.3V_K_X5R_0201



1



HPOUT_R



[69]



MIC2_VREFOL



[69]



MIC2_VREFOR



27



HPOUT_R



26



MIC2_VREFOL



28 29



20



HPOUT-L



PDB BCLK SYNC



HPOUT-R JD2 MIC2-VREFO-L JD1



RING2_CONN [69] [69]



30



RING2_CONN RING3_CONN



31



PC_BEEP



34



RING3_CONN



GPIO0/DMIC-DATA12 MIC2-L/RING2 GPIO1/DMIC-CLK MIC2-R/SLEEVE I2C-DATA PCBEEP I2C-CLK



1



1



@



SPKR_MUTE_N RA16 1



EC_MUTE_N



2 0_0402_5%



14



HDA_BITCLK_AUDIO



15



HDA_SYNC_AUDIO



47 48



JSENSE



RA7



2



@



1 100K_0402_1%



RA8



1



@



2 0_0402_5%



EC_MUTE_N [79]



HDA_BITCLK_AUDIO



[13]



HDA_SYNC_AUDIO



[13]



+3VS



PLUG_IN PLUG_IN



[69]



Note: need to configuration 1*JD mode by verb table



1 4



DMIC_DATA_R RA9



5



DMIC_CLK_R



1



@



2 0_0402_5% CODEC_DMIC_DAT



RA10 1



@



2 0_0402_5% CODEC_DMIC_CLK



CODEC_DMIC_DAT



[47]



CODEC_DMIC_CLK



[47]



6 7



+5VA RA12 1



+1.8V_AUDIO



2 10K_0402_5%



[69]



LINE2-R



[69]



LINE2-L



C



VDD_STB



33



LINE2-R



35



LINE2-L



36



NC1 5VSTB NC2 LINE2-R NC3 LINE2-L NC4



+1.8VS



NC5



@ RA2 1



2



D



2 CA1 2 CA2



MIC2-VREFO-R SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN



1



CA11 10U 6.3V M X5R 0402



2



CA10 10U 6.3V M X5R 0402



2



CA9 @



2 LA1 1 BLM15PD600SN1D_2P EMC_NS@



1U_6.3V_M_X5R_0201



1



0.1U_6.3V_K_X5R_0201



CA8



[69]



HPOUT_L



MIC2_VREFOR



@ 1 RA11



HPOUT_L



CPVDD/AVDD2



[69]



AVDD1



Close to Pin7



41



UA1



40



2



PVDD1



1



46



2



Analog power for DACs, ADCs



2.2U_0402_6.3V6M



2



+5VA



0.1U_6.3V_K_X5R_0201



2 0_0402_5%



2



+5VD



+5VA



1



1



CA5 @ 1



+5VD



RA6



1



CA4



DVDD 10U 6.3V M X5R 0402



@



CA6



0.1U_6.3V_K_X5R_0201



2.2U_0402_6.3V6M



+1.8VALW D



+1.8V_AUDIO



2 0_0402_5%



0.1U_6.3V_K_X5R_0201



CA3



1



PVDD2



RA1



3



2 0_0402_5%



18



@



DVDD



1



DVDD-IO



RA3



1



the diffrent with Base MODULE: 1.Module no ra3 to DVDD_IO,S360&V14&V15 reserve 2.Module no ra5 CA21 to EC_BEEP,S360&V14&V15 reserve 3.RA9&RA10 BOMStructure different with module



Note: DVDD-IO must be equal to or smaller than DVDD +3VALW



3



8 9 10 C



11 12



2 0_0402_5% CA14 1



2 1U_6.3V_M_X5R_0201 CBP



23



CBN



24



CBP



SPK-OUT-R+



CBN



SPK-OUT-RSPK-OUT-L-



2.2U_0402_6.3V6M 2



1 CA16



VREF



2.2U_0402_6.3V6M 1



2 CA17



LDO3-CAP 19



2.2U_0402_6.3V6M 1



2 CA18



LDO2-CAP 21



2.2U_0402_6.3V6M 1



2 CA19



LDO1-CAP 39



MIC2-CAP DC DET/EAPD



SPK_R+ SPK_R-



43



SPK_L-



42



SPK_L+



SPK_R+ [69] SPK_R- [69] SPK_L- [69] SPK_L+ [69] 13



VREF LDO3-CAP



SDATA-IN



LDO2-CAP



SDATA-OUT



LDO1-CAP



22



37



AVSS1



38



SPK-OUT-L+



CPVEE



Thermal Pad



MIC2-CAP 32



AVSS2



1 CA15



16



SDATA_IN RA14 2



17



HDA_SDOUT_AUDIO



25



1 33_0402_5%



HDA_SDIN0 HDA_SDIN0



[13]



HDA_SDOUT_AUDIO[13]



CPVEE 2



1



CA20 1U_6.3V_M_X5R_0201



ALC3287-CG_MQFN48_6X6



49



2.2U_0402_6.3V6M 2



45 44



Note: power beep function is removed from BIOS spec



B



B



@ RA21 1 RA18 1



2 4.7K_0402_5%



PC_BEEP1_RCA22 1



2 0_0402_5%



PC_BEEP



2



@



1



[12] PCH_BEEP



PCH_BEEP



RA26 1



0.1U_6.3V_K_X5R_0201 RA19 10K_0402_5% @



2 0_0402_5% @



2



RA27 1



2 0_0402_5% @



RA29 1



2 0_0402_5%



RA83



1EMC_NS@ 2 0_0402_5%



RA84



1EMC_NS@ 2 0_0402_5%



HDA_SYNC_AUDIO HDA_SDOUT_AUDIO RA28 HDA_BITCLK_AUDIO_R1 2 HDA_BITCLK_AUDIO 1/16W_27_5%_0402 EMC_NS@ HDA_SDIN0



CODEC_DMIC_DAT



HPOUT_R



2



1



2



1



2



GND



GNDA



1000P 25V K X7R 0201 CA92 EMC_NS@



1



1000P 25V K X7R 0201 CA91 EMC_NS@



2



HPOUT_L



100P 25V J NPO 0201 CA32 EMC_NS@



2



1



100P 25V J NPO 0201 CA31 EMC_NS@



2



1



CA36 EMC_NS@ 33P_50V_J_NPO_0201



2



1



CA35 EMC_NS@ 33P_50V_J_NPO_0201



A



1



CA34 EMC_NS@ 22P_0201_258J



2



CA33 EMC_NS@ 22P_0201_258J



1



CODEC_DMIC_CLK



A



LCFC Highly Confidential Information



Security Classification Issued Date



2012/07/01



Deciphered Date



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize C DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Date: 5



4



3



2



Document Number



Rev 0.1



Audio_Codec Wednesday, November 11, 2020 Sheet 1



66



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Audio_Amplifier Tuesday, November 10, 2020



Sheet 1



Rev 0.1 67



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Audio_DSP



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



68



of



110



5



4



3



2



1



Speaker



JSPK1 [66] [66] [66] [66]



SPK_R+ SPK_RSPK_L+ SPK_L-



SPK_R+ SPK_RSPK_L+ SPK_L-



RA23 RA22 RA24 RA25



1 1 1 1



2 2 2 2



EMC@ EMC@ EMC@ EMC@



SPK_R+_CONN SPK_R-_CONN SPK_L+_CONN SPK_L-_CONN



HCB1608KF-121T30_0603 HCB1608KF-121T30_0603 HCB1608KF-121T30_0603 HCB1608KF-121T30_0603



1 2 3 4



1 2 3 4



GND1 GND2



5 6



D



D



1



2



1



2



1



CA30 @ 220P_25V_K_X7R_0201



2



2



CA29 @ 220P_25V_K_X7R_0201



1



CA28 @ 220P_25V_K_X7R_0201



the diffrent with Base MODULE: 1.S360&V14&V15 RA86&RA87 VALUE different with module, Module have RA85&RA88,S360&V14&V15 Remove 2.for EMC TVS EMC_NS@ type different with module 3.GND type different 4.module no CA37&CA41 part circuit,,S360&V14&V15 reserve



2



CA27 @ 220P_25V_K_X7R_0201



2



1



CA26 EMC@ 1500P_25V_K_X7R_0201



1



CA25 EMC@ 1500P_25V_K_X7R_0201



C



2



CA24 EMC@ 1500P_25V_K_X7R_0201



CA23 EMC@ 1500P_25V_K_X7R_0201



For EMC Near CODEC



1



2



HIGHS_WS33041-S0191-HF ME@



1



For EMC Near Conn.



6pin&7pin audio jack comon design,stuff 6pin default; need vitrual symbol control



C



Audio Jack



JHP1



1 RA30 0_0402_5% RA15



1



2HPOUT_L_R_C



@



[66] [66]



2 @ HPOUT_L_R CA37 1 470P_50V_K_X7R_0201



[66]



2 100K_0402_1%



@



MIC2_VREFOL HPOUT_L



1 2.2K_0402_5% 2 56_0402_5%



2 1U_6.3V_M_X5R_0201



RA87 1



2 56_0402_5%



HPOUT_R_R



2



MIC2_VREFOR



RA36 2



1 2.2K_0402_5%



RING3_CONN



4



MIC2_VREFOR



1 1 2 2



1 1 2 2



1 1 2 2



1 1 2 2



1 1 2 2



DA5



2



1



2



1



2



7



G/M L 5 6 R M/G MS ATOB_063-RT04-0601 ME@



Conector list USE 063-RT04-0701



B



EMC@ AZ5123-01F.R7GR_DFN1006P2X2



DA4



EMC_NS@ AZ5123-01F.R7GR_DFN1006P2X2



DA3



EMC_NS@ AZ5123-01F.R7GR_DFN1006P2X2



DA7



EMC_NS@ AZ5123-01F.R7GR_DFN1006P2X2



EMC_NS@ AZ5123-01F.R7GR_DFN1006P2X2



2



CA39 EMC_NS@ 47P_25V_J_NPO_0201



1



1



100P 25V J NPO 0201 CA45 EMC@



1



100P 25V J NPO 0201 CA44 EMC@



[66] PLUG_IN



5



HPOUT_R



RING3_CONN RING2_CONN HPOUT_L_R HPOUT_R_R PLUG_IN



[66] RING3_CONN [66] RING2_CONN



PLUG_IN



6



2 B



3 1



2 1U_6.3V_M_X5R_0201



2 10K_0402_5%



@



RING2_CONN HPOUT_L_R



100P 25V J NPO 0201 CA43 EMC_NS@



1



CA38 1 @ CA40 1 @



HPOUT_R



[66]



2 @ HPOUT_R_R CA41 1 470P_50V_K_X7R_0201



RA31 2 RA86 1



100P 25V J NPO 0201 CA42 EMC_NS@



RA85



2HPOUT_R_R_C



@



LINE2-R



LINE2-R



[66] 1 RA35 0_0402_5%



LINE2-L



LINE2-L



[66]



MIC2_VREFOL HPOUT_L



DA2



For EMI A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Audio_SPK/Jack Tuesday, November 10, 2020



Sheet 1



Rev 0.1 69



of



110



5



4



3



2



1



D



D



Card reader Circuit MOVE to SUB Board S360



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Card Reader



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



70



of



110



A



B



C



D



E



+1.8VALW_PCH @



RN1 1



3



[12,13] PCH_BT_OFF_N



2



@



2



BT_OFF_N



RN6 10K_0402_5%



QN2 L2N7002KN3T5G_SOT883-3 2 @



3



LSI1012XT1G_SC-89-3 +3V_WLAN



@ [16]



JWLAN1 [14] [14]



USB20_10_P USB20_10_N



[15] [15]



CNV_WR_D1_N CNV_WR_D1_P



[15] [15]



CNV_WR_D0_N CNV_WR_D0_P



[15] [15]



CNV_WR_CLK_N CNV_WR_CLK_P



2



1 3 5 7 9 11 13 15 17 19 21 23



USB20_10_P USB20_10_N CNV_WR_D1_N CNV_WR_D1_P CNV_WR_D0_N CNV_WR_D0_P CNV_WR_CLK_N CNV_WR_CLK_P



GND1 USB_D+ USB_DGND2 SDIO_CLK SDIO_CMD SDIO_DATA0 SDIO_DATA1 SDIO_DATA2 SDIO_DATA3 SDIO_WAKE# SDIO_RESET#



25 27 29 31 CN8 0.1U_6.3V_K_X5R_02011 0.1U_6.3V_K_X5R_02011 CN9



[14] PCIE_PTX_DRX9_P [14] PCIE_PTX_DRX9_N



[14] PCIE_PRX_DTX9_P [14] PCIE_PRX_DTX9_N [16] CLK_PCIE_WLAN_P [16] CLK_PCIE_WLAN_N



3



2 2



33 35 37 39 41 43 45 47 49 51 53 55 57



PCIE_PTX_C_DRX9_P PCIE_PTX_C_DRX9_N



PCIE_PRX_DTX9_P PCIE_PRX_DTX9_N CLK_PCIE_WLAN_P CLK_PCIE_WLAN_N WLAN_CLKREQ_Q_N PCIE_WAKE_N_WLAN



CNV_WT_D0_N CNV_WT_D0_P



[15] [15]



CNV_WT_CLK_N CNV_WT_CLK_P



59 61 63 65 67 69 71 73 75



CNV_WT_D0_N CNV_WT_D0_P CNV_WT_CLK_N CNV_WT_CLK_P



1 RN8 1/20W_200K_5%_0201



[17] CNVI_RF_RESET_N



[13]



CNVI_MODEM_CLKREQ



[13]



GND14



32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74



1 CNVI@ 21/20W_49.9_1%_0201



EC_TX_RSVD EC_RX_RSVD



1 @ 1 @



@



2



PCIE_WAKE_N_WLAN



2



CNVI_BRI_RSP [15]



RN15 RN16



RN17 RN18 RN19



1 1



@ @



2 0_0201_5% 2 0_0201_5%



WLAN_SMB_DATA WLAN_SMB_CLK



RN20 RN21 RN22



1 1 1



@ @



2 0_0201_5% 2 0_0201_5% 2 100K_0201_5%



1 REFCLK0



TN3



1



@



CNVI_RGI_DT CNVI_RGI_RSP CNVI_BRI_DT



EC_TX EC_RX



2 0_0201_5% 2 0_0201_5%



SUSCLK_R WLAN_PERST_N BT_OFF_N_R WLAN_OFF_N



2 0_0201_5%



SUSCLK



BT_OFF_N



RN5



2



110K_0201_5%



@



110K_0201_5% +1.8VALW



CNVI_RGI_DT



RN2



2 CNVI@



1100K_0201_5%



CNVI_BRI_DT



RN3



2



1100K_0201_5%



@



3



[16]



PCH_WLAN_OFF_N [12] EC_RX EC_TX



1



1



2



1



2



1



2



[79] [79]



WLAN_PERST_N RN12 1 0_0201_5%



Deciphered Date



@



2



@



2



PCH_WLAN_PERST_N [12]



@



RN11 1



PLT_RST_N [17,32,62,77,78]



0_0201_5% 4



Title



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



C



2



BT_OFF_N



LCFC Highly Confidential Information 2012/07/01



RN4



+3V_WLAN



4



Security Classification



[15] [15] [15]



WLAN_OFF_N



@



76



ARGOSY_NASE0-S6701-TSH4 ME@



B



2



0_0201_5%



1 CNVI@ 21/20W_49.9_1%_0201



CNVI_RGI_RSP_R RN14



2



A



1



RN10



[12] PCH_PCIE_WAKE_N_WLAN



@



+3V_WLAN



RSRVD/PETP1 I2C_DATA RSRVD/PETN1 I2C_CLK GND8 ALERT# RSRVD/PERP1 RSRVD RERVD/PERN1 UIM_SWP/PERST1# GND9 UIM_POWER_SNK/CLKREQ1# RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# RSRVD/REFCLKN1 3.3VAUX3 GND10 3.3VAUX4



Issued Date



1 RN9 0_0201_5%



PCIE_WAKE_N



24 26 28 30



UART_TXD UART_CTS UART_RTS VENDOR_DEFINED1 VENDOR_DEFINED2 VENDOR_DEFINED3 COEX3 COEX2 COEX1 SUSCLK PERST0# W_DISABLE2# W_DISABLE1#



GND15



+3V_WLAN



2



0.01U_6.3V_K_X7R_0201 CN6



77



WLAN_CLKREQ_Q_N



2



CN3 0.01U_6.3V_K_X7R_0201



100U_1206_6.3V6M CN7



[15] [15]



CNV_WT_D1_N CNV_WT_D1_P



GND3 PETP0 PETN0 GND4 PERP0 PERN0 GND5 REFCLKP0 REFCLKN0 GND6 CLKREQ0# PEWAKE0# GND7



CNVI_BRI_RSP_R RN13



1



RN7



WLAN_CLKREQ_N



0_0402_5% 1



0.1U_6.3V_K_X5R_0201 CN5



CNV_WT_D1_N CNV_WT_D1_P



KEY E PIN24~PIN31 NC PIN



2 4 6 8 10 12 14 16 18 20 22



2



10U 6.3V M X5R 0402 CN4



[15] [15]



3.3VAUX1 3.3VAUX2 LED1# PCM_CLK/I2S_SCK PCM_SYNC/I2S_WS PCM_IN/I2S_SD_IN PCM_OUT/I2S_SD_OUT LED#2 GND11 UART_WAKE# UART_RXD



1



0.1U_6.3V_K_X5R_0201 CN2



2



10U 6.3V M X5R 0402 CN1



1



1



D



S



0_5%_0603



1



2



+3V_WLAN



G



1



+3V_WLAN



1



100K_0201_5%1 +3VSUS



+3VS



2 0_0402_5% PCH_BT_OFF_PUPWR 2 RN29 QN3 2



RN30 1



1



WLAN



D



Document Number



WLAN



Tuesday, November 17, 2020



Rev 0.1 Sheet E



71



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



WWAN



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



72



of



110



5



4



3



2



1



D



D



LAN Circuit MOVE to SUB Board in V360 DB



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



LAN_Chipset



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



73



of



110



5



4



3



2



1



D



D



LAN Circuit MOVE to SUB Board in V360 DB



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



LAN_Transformer Tuesday, November 10, 2020



Sheet 1



Rev 0.1 74



of



110



5



4



3



2



1



D



D



LAN Circuit MOVE to SUB Board in V360 DB C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



LAN_CONN



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



75



of



110



5



4



3



2



1



D



D



C



C



B



B



A



A



Issued Date



Title



LCFC Highly Confidential Information



Security Classification 2012/07/01



Deciphered Date



S360-TGL



2014/07/01



THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.



Size B Date:



5



4



3



2



Document Number



Sensor



Tuesday, November 10, 2020



Rev 0.1 Sheet 1



76



of



110



5



4



3



2



1



Near CHARGER



Near CPU 1



REMOTE2+_R



REMOTE1+ CS302 2200P_25V_K_X7R_0201 2 REMOTE1-



2



REMOTE2+



4



2



C



3



5



SDA



DN1



ALERT#



DP2



THERM#



DN2



GND



1



E 3



REMOTE2-_R



10



EC_SMB_CK0



9



EC_SMB_DA0



8



SEN_ALERT_N



7



SEN_THERM_N



EC_SMB_CK0



[32,79]



EC_SMB_DA0



[32,79]



Near GPU REMOTE+ CS307 100P 25V J NPO 0201 OPT@



6



1 2



B



2



QS303 LMBT3904WT1G_SOT323-3 OPT@



REMOTE-



REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: Trace width/space:10/10 mil the diffrent Trace length: