5 0 3 MB
A
B
C
D
E
1
1
LCFC Confidential 2
2
KENOBI NM-A821 Rev2.0 Schematic Intel KabyLake Processor with DDR4 + PCH-LP NVIDA N16V-GMR GDDR3 2GB 3
3
2016-08-24 Rev2.0
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification 2015/10/5
Deciphered Date
COVER PAGE
2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number Custom
Date: A
B
C
D
KENOBI
Thursday, August 25, 2016 E
Sheet
Re v 2.0 1
of
82
A
B
C
D
E
Kenobi KBL U Block Diagram GPU VRAM
Page 25~30
DDR5
1
NVIDIA
Page 31~32
PCIE x 4
(PCIE Lane 1~4)
GDDR3
N16V-GMR1-S-A2 N16S-GTR-S-A2
DIS only (SWG)
DDR4 2133/2400 Mhz SODIMM A
DDR4 2133/2400MHz Channel A
Page22
DDR4 2133/2400 Mhz SODIMM B
PCIe x 1
Intel CPU Kabylake U 15W (UM A& DIS) Kabylake PCH-LP 10 USB 2.0/1.1 Ports 6 USB 3.0 Ports 3 SATA Ports 12 PCIE Ports HD Audio LPC I/F ACPI 3.0
NGFF Card WLAN
(PCIE Lane 9)
Page 48 1
USB 2.0 x 1
(Port 6)
802.11 a/b/g/n BT V4.0 combo
SATA x 1
HDD Page42
DDR4 2133/2400MHz Channel B
Page23
Finger Print
USB 2.0 x 1
Page61
(Port 9)
Touch Panel (Optional)
WORLD FAIR VAL1167
EDP x 2
15" LCD FHD/HD
USB 2.0 x 1
(Port 5)
2D Camera (Digital MIC)
2
DMIC_DATA DMIC_CLK
PCIe x 2
M2 Slot for SSD
(PCIE Lane11/12)
USB 2.0 x 1
Page42
2
(Port 7)
USB 2.0 x 1
IR Camera (Optional)
(Port 8)
Page37
Card Reader Bayhub
DDI1
PCIe x 1
Page49
HDMI v1.4 Page36
(PCIE Lane 5)
OZ621FJ1LN
USB Type-C PD
USB 3.0 x 1
Right- Fr ont
(Port 4)
JUSB4 (USB3.0)
Cypress
USB 2.0 x 1
Page44
(Port 4)
I2C
DDI2
Reserve
Right- Back
JUSB3 (USB3.0) Page44
3
JUSB2 (USB2.0)
Page55
(Port 3)
USB 3.0 x 1
USB 2.0 x 1
(Port 1)
(Port 3)
USB 2.0 x 1
Page45
Page44
TI
I2C
LPC BUS
USB 2.0 x 1
PCIe x 1
Page46
(PCIE Lane 10)
Realtek
Thermal Sensor Fintek
Page62
F75303M
EC Page57
R8111GUS
PS2
ITE
Click Pad
BGA1356 40mm*24mm
HP R/L
Page53
Track Point
Page63
IT8586EX
MIC IN/GND
Combol Jack
3
Page55
SMBus
LAN 10/100/1000
Page47
Type C Conn.
PS8743
(Port 2)
TPS2546RTER
RJ45 Conn.
Parade
(Port 1)
(Port 2)
USB charger (AOU)
Power Control
Switch MUX
USB 3.0 x 1
USB 3.0 x 1
AOU
Page54
CYPD3125
Mirror function SPI BUS
Int. K/B Matrix
Page63
I2C
Page 5~20
SPI BUS
Stereo Speaker
4
Page52
(2CH 2W/4ohm)
HDA Codec
Page21
HDA
Page51
Flash ROM 4M/8M
FAN
Int. KB
Page61
Page60
G-sensor Page59
Fintek
4
LIS3DSHTR
CONEXANT
CX11852-11Z
TPM 1.2 Page58
Infineon
SLB9670VQ1.2
Issued Date
Title
LC Future Center Secret Data
Security Classification 2015/09/01
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. A
B
www.vinafix.com C
BLOCK DIAGRAM
2016/12/31 Size A1
Document Number
KENOBI
Thursday, August 25, 2016
Date: D
E
Sheet
Re v 2.0 2
of
82
A
B
Voltage Rails ( O --> Means ON
C
, X --> Means OFF )
D
SMBUS Control Table Main VGA
SOURCE
+5VS
Power Plane
E
BATT (Charger) SODIMM
WLAN WiMAX
Thermal Sensor
PCH
CP Module
LAN PHY
G sensor
X
X
X
X
+3VS
1
B+ +3VL State
+3VALW +5VALW +2.5V +1VALW +1.2V +1.8VALW +VCC_STG
+VCC_CORE
EC_SMB_CK1
IT8580F
+VCC_IO
EC_SMB_DA1
+3VL
+VCC_ST
EC_SMB_CK2
IT8580F
+VGA_CORE
EC_SMB_DA2
+3VL
+1.5VS_VGA
EC_SMB_CK3
IT8580F
+3VS_AON
EC_SMB_DA3
+3VS
X
V
X
X
X
+VCC_SA
X
X
1
X
X
X
X
X
X
X
X
V
X
S0
O
O
O
O
S3
O
O
O
X
O
O
X
X
S5 S4/AC Only S5 S4 Battery only
O
S5 S4 AC & Battery don't exist
STATE
3
4
1 2 3 4 5 6 7 8 9
X
X
X
V
+3VS_VGA
PCH_SML1CLK PCH_SML1DAT
X
X
V
X
+3VS
V +3V_PCH
V
X
EC_ON2 EC_ON
SUSP#
SYSON
HIGH
HIGH
ON
ON
ON
HIGH
S1(Power On Suspend)
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
HIGH
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
HIGH
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
ON
OFF
LOW
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
ON
OFF
LOW
JUSB1 TYPE-C JUSB2 JUSB3 JUSB4 Touch Panel BT CMOS IR CAMERA FP/Smart
Port 1 2 3 4
Device JUSB1 TYPE-C JUSB2 JUSB3 JUSB4
SATA Port
Port
Device
1 2 3 4 5 6 7 8 9 10 11 12
GPU GPU GPU GPU CardReader X X X WLAN LAN M.2 SSD M.2 SSD
X
X
V +3VS
X
X
X
X
X
X
X
+5VS
X
X
X
X
X
X
Structure
NOTE
Port 1 2 3 4
Device HDD X X X
PCB@
For PCB load BOM
XDP@
Debug port
UMA@
UMA SKU ID
DIS@
Optimus SKU ID
SSD@
SSD setting
FRP@
Finger printer setting
TYPEC@
For USB Type-C function
ME@
ME Connector
EMC@
For EMC function
EMC_2D@
For EMC function
EMC_NS@
For EMC function
RF_NS@
For RF function
S2G@
For VRAM Strap
CHA@
For VRAMA function
CHB@
For VRAMB function
RANKA@
GPU DDR5 Setting
X76@
GPU VRAM Setting
3DCCD@
3D Camera Setting
VGA@
VGA Setting
MUX@
MUX Setting
ODD@
ODD Setting
TPM@
Trusted Platform Module (TPM)
MIRROR@
For mirror function
NGC6@
For VGA Non GC6 function
GC6@
For VGA GC6 function
2015/10/5
Deciphered Date
4
Title
LC Future Center Secret Data
Security Classification Issued Date
3
NOTE LIST
2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number Custom
Date: A
B
+3VS_GS
2
X
PCIE Port
X
BOM
HIGH
Device
PCH +3V_PCH
X
V
+3VPD_VDD
BOM Structure Table
HIGH
USB3 Port
PCH +3V_PCH
X
X
SLP_A# SLP_S3# SLP_S4# SLP_S5#
PCH_SMB_CLK PCH_SMB_DATA
Full ON
USB2 Port Port
SIGNAL
X
X
+3VS_VGA
+0.6VS
X
+3VALW
+1VS_VGA
2
USB Type-C
C
D
KENOBI
Thursday, August 25, 2016 E
Sheet
Re v 2.0 3
of
82
5
4
3
2
1
[KENOBI PWR Sequence_SKL-U_DDR4_Non-Deep Sx]
[DC Mode]
[AC Mode]
BATT+
D
AC_IN
170mS
D
AC_PRESENT
B+ B+ +3VLP/+VL
9mS
+3VLP/+VL
200uS
ON/OFFBTN#
MAINPWON_EC
EN_5V/EN_3V
moniter AC_IN (51_ON) EC_ON Min:50nS
+3VALW
T=10ms Moniter ON/OFFBTN#
+5VALW/+3VALW PCH_PWR_EN
moniter EN_3V
+1VALW/+1.8VALW
3V5V_ON Min:50nS
+5VALW
EC_RSMRST#
15mS
EC_ON2
T=10ms Moniter ON/OFFBTN# and EN_3/5V both of risgin edge
SUSPWRDNACK Min:60nS
PBTN_OUT#
+1VALW/+1.8VALW
ON/OFFBTN#
415mS
PBTN_OUT#
95~100mS
20ms
T=110ms
Moniter ON/OFFBTN# rising edge
Moniter ON/OFFBTN# rising edge 20ms
20mS
EC_RSMRST#
SUSPWRDNACK C
C
AC_PRESENT
PM_SLP_S5#
Montier PBTN_OUT# falling edge.
PM_SLP_S4# PM_SLP_S3# SYSON +1.2V
DDR_PG_CTRL
immediately, After PM_SLP_S4# falling edge
+0.6VS
T=20ms After PM_SLP_S3# moniter SYSON rising edge.
SUSP#
immediately, After PM_SLP_S3# falling edge
+5VS +3VS
+1.5VS
B
B
VCCST_PG_EC (ALL_SYS_PWRGD,non CPU code VR)
T=20ms After SUSP# risign edge
VR_ON
immediately, VCCST_PG_PWR & VCCST_PG_EC risign edge
+VCC_CORE
immediately, After SUSP# falling edge
Vboot
VGATE T=10ms After VCCST_PG_EC rising edge
PCH_PWROK
immediately, After SUSP# falling edge
H_CPUPWRGD_R T=99ms
SYS_PWROK
After VCCST_PG_EC assertion
immediately, After SUSP# falling edge
PLT_RST# After CPUPWRGD/PCH_PWRGD/SYS_PWROK assertion
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification 2015/10/5
Deciphered Date
Power Sequence
2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size D
Document Number
4
3
2
R ev 2.0
KENOBI
Thursday, August 25, 2016
Date: 5
1
Sheet
4
of
82
5
4
3
2
1
D
D SKL_ULT
UC1A
HDMI
USB TYPE C
[36] [36] [36] [36] [36] [36] [36] [36]
PCH_HDMI_TX2PCH_HDMI_TX2+ PCH_HDMI_TX1PCH_HDMI_TX1+ PCH_HDMI_TX0PCH_HDMI_TX0+ PCH_HDMI_TXCPCH_HDMI_TXC+
[55] [55] [55] [55] [55] [55] [55] [55]
DDI2_MUX_TX0DDI2_MUX_TX0+ DDI2_MUX_TX1DDI2_MUX_TX1+ DDI2_MUX_TX2DDI2_MUX_TX2+ DDI2_MUX_TX3DDI2_MUX_TX3+
PCH_HDMI_TX2PCH_HDMI_TX2+ PCH_HDMI_TX1PCH_HDMI_TX1+ PCH_HDMI_TX0PCH_HDMI_TX0+ PCH_HDMI_TXCPCH_HDMI_TXC+
E55 F55 E58 F58 F53 G53 F56 G56
DDI2_MUX_TX0DDI2_MUX_TX0+ DDI2_MUX_TX1DDI2_MUX_TX1+ DDI2_MUX_TX2DDI2_MUX_TX2+ DDI2_MUX_TX3DDI2_MUX_TX3+
C50 D50 C52 D52 A50 B50 D51 C51
DDI1_TXN[0] DDI1_TXP[0] DDI1_TXN[1] DDI1_TXP[1] DDI1_TXN[2] DDI1_TXP[2] DDI1_TXN[3] DDI1_TXP[3] DDI2_TXN[0] DDI2_TXP[0] DDI2_TXN[1] DDI2_TXP[1] DDI2_TXN[2] DDI2_TXP[2] DDI2_TXN[3] DDI2_TXP[3]
EDP
DDI
HDMI_CLK HDMI_DAT
HDMI_CLK HDMI_DAT
L13 L12
PCH_MUX_CLK PCH_MUX_DAT +VCC_IO
N11 N12 RC1
C
1
2 24.9_0402_1%
EDP_COMP E52
[SKL PDG]EDP_RCOMP Pull up to VCCIO via 24.9 ohm resistor [SKL PDG]EDP_RCOMP 1. Trace width=20 mils, Spacing=25mil, Max length=100mils 2. RC1 close to MCP
DDPB_CTRLDATA,
DDPC_CTRLDATA
N7 N8
EDP_AUXN EDP_AUXP
EDP
EDP_DISP_UTIL
DISPLAY
[36] [36]
EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]
DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP
SIDEBANDS
GPP_E18/DDPB_CTRLCLK GPP_E19/DDPB_CTRLDATA
GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3 GPP_E17/EDP_HPD
GPP_E20/DDPC_CTRLCLK GPP_E21/DDPC_CTRLDATA GPP_E22/DDPD_CTRLCLK GPP_E23/DDPD_CTRLDATA
EDP_BKLTEN EDP_BKLTCTL EDP_VDDEN
EDP_RCOMP SKYLAKE-U_BGA1356 REV = 1 @
C47 C46 D46 C45 A45 B45 A47 B47
CPU_EDP_TX0CPU_EDP_TX0+ CPU_EDP_TX1CPU_EDP_TX1+
E45 F45
CPU_EDP_AUX# CPU_EDP_AUX
CPU_EDP_AUX# CPU_EDP_AUX
[37] [37]
DDI2_MUX_AUX# DDI2_MUX_AUX
[55] [55]
EDP
G50 F50 E48 F48 G46 F46
DDI2_MUX_AUX# DDI2_MUX_AUX
L9 L7 L6 N9 L10
HDMI_HPD PCH_MUX_HPD
R12 R11 U13
ENBKL PCH_EDP_PWM PCH_ENVDD
HDMI_HPD [36] PCH_MUX_HPD [54,55]
CPU_EDP_HPD
CPU_EDP_HPD
[37]
ENBKL [57] PCH_EDP_PWM PCH_ENVDD
[37] [37] C
1 OF 20 ? ?
Internal PD 20K
RC4
1
2 2.2K_0402_5%
PCH_MUX_CLK
RC6
1
2 2.2K_0402_5%
PCH_MUX_DAT
RC7
1
2 3.3K_0402_5%
HDMI_CLK
RC8
1
2 3.3K_0402_5%
HDMI_DAT
ENBKL
RC2
1
2 100K_0402_5%
CPU_EDP_HPD
RC3
1
2 100K_0402_5%
[SKL PDG]EDP_HPD Pull down to ground via 100k ohm resistor PCH_MUX_HPD
RC5
1 2 100K_0402_5% TYPEC_NS@
20160824 Change RC5 from @ to TYPEC_NS@ (Only for Non Type-C SKU)
20160218 Staff RC7/RC8 for HDMI detect issue
B
[37] [37] [37] [37]
B52
+3VS
@
CPU_EDP_TX0CPU_EDP_TX0+ CPU_EDP_TX1CPU_EDP_TX1+
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification 2015/09/01
Deciphered Date
KBL(1/16):DDI/EDP
2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number Custom
Date: 5
4
3
2
Re v 2.0
KENOBI
Thursday, August 25, 2016 1
Sheet
5
of
82
5
4
3
+VCC_STG
2
1
+VCC_ST
+VCC_ST
D
D
RC10
2
1 1K_0402_1%
[SKL PDG]1 K to VCCST
pull- up
1
1
THRMTRIP#
RC11 1K_0402_5%
UC1D
2
2
RC213 1K_0402_5% @
[57] [57,67,70]
H_PECI VR_HOT# TC30
H_PECI VR_HOT# RC13 1 1H_THERMTRIP# RC12 1
TC1 @
2 499_0402_1% 2 0_0402_5%
[SKL PDG]If THERMTRIP# goes active, the CPU is indicating an overheat condition, and the PCH will immediately transition to an S5 state. CPU_GP can be used from external sensors for the thermal management.
EC_WAKE# [57]
1
EC_WAKE#
TC2 TC3 TC4 TC5
2 0_0402_5%
RC18
1
1 1 1 1
VR_HOT#_R THRMTRIP#
D63 A54 C65 C63 A65
XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3
C55 D55 B54 C56
EC_WAKE#_L
@ RC21 RC23 RC24 RC25
1 1 1 1
2 2 2 2
49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1%
C
PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP
A6 A7 BA5 AY5 AT16 AU16 H66 H65
CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#
SKL_ULT
+VCC_STG
JTAG
PROC_TCK PROC_TDI PROC_TDO PROC_TMS PROC_TRST#
CPU MISC
BPM#[0] BPM#[1] BPM#[2] BPM#[3]
PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_TRST# JTAGX
GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP
B61 D60 A61 C60 B59
XDP_TCLK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#
XDP_TDI
RC14
1 @
2 51_0402_5%
XDP_TMS
RC15
1 @
2 51_0402_5%
PCH_JTAG_TDI
RC16
1 @
2 51_0402_5%
B56 D59 A56 C59 C61 A59
PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TRST# PCH_JTAGX
PCH_JTAG_TMS
RC17
1 @
2 51_0402_5%
PCH_JTAG_TDO
RC19
1
2 100_0402_5%
XDP_TDO
RC20
1 @
2 100_0402_5%
PCH_JTAGX
RC22
1 @
2 1K_0402_5%
20160119 Unmount RC16,RC17,RC20
SKYLAKE-U_BGA1356 REV = 1 @
? 4 OF 20
20160525 Change RC19/RC20 to100 ohm for PROC_TDO termination
?
[SKL PDG]PROC_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm ∮ 1 %. [SKL PDG]PCH_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm ∮ 1 %. [SKL PDG]On Package Interface Compensation (OPI) Guidelines Should be referenced to VSS plane only. VSS reference planes must be continuous Require low DC resistance routing 15mils 2.No trace under crystal 3.Place on oppsosit side of MCP for temp inf l uence 4.The exact capacitor values forC1 and C2 must be based on the crystal maker recommendat i ons. Typical values for C1 and C2 are 18 pF, based on crystal load of 12.5 pF.
B
1
RTC Crystal
2
[SKL PDG] 1.A 24 MHz crystal with crystal frequency tolerance and stability of +/ -30 ppm 2.Two External Load Capacitors (Ce1 and Ce2) 3.A 1-Mohm bias resistor (Rf)
PCH_RTCX1
PCH_XTAL24_IN
PCH_RTCX2
PCH_XTAL24_OUT
1
RC57 10M_0402_5%
1
2
1
[SKL PDG]Max Crystal ESR = 50k Ohm.
2
A
1 GND1
1 CC7 6.8P_0402_50V8-D
2
RC58 1M_0402_5%
YC1 32.768KHZ_12.5PF_9H03200042
1
B
2
2
1 CC8 6.8P_0402_50V8-D
CC9 12P_0402_50V8-J
3 3 GND2 YC2 4 24MHZ_10PF_8Y24000011
2
1
2
CC10 12P_0402_50V8-J
A
20160127 Change CC7/CC8 to 6.8p by vender suggestion
Issued Date
Title
LC Future Center Secret Data
Security Classification 2015/09/01
Deciphered Date
2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
KBL(6/16):CLOCK SIGNALS Size Document Number Custom
Date: 5
4
3
2
Re v 2.0
KENOBI
Thursday, August 25, 2016 1
Sheet
10
of
82
5
Functional
D
Strap
4
3
2
1
Definitions
L:Disable Intel ME Crypto TLS cipher suite (no confidentiality). *H:Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality).Support Intel AMT with TLS and Intel SBA (Small Business Advantage) with TLS.
D
+3VALW_PCH
1
SMBALERT#
2 1K_0402_5%
RC59
GPP_C2, Internal PD 20K
SKL_ULT
UC1E
close to CPU [21,58] [21,58] [21,58] [21] [21] [21] [21] [58]
JTAG ODT +3VALW_PCH
SPI_CLK SPI_SO SPI_SI SPI_IO2 SPI_IO3 SPI_CS0#_8MB SPI_CS1#_4MB SPI_CS2#_TPM
SPI - FLASH
SPI_CLK SPI_SO SPI_SI SPI_IO2 SPI_IO3 SPI_CS0#_8MB SPI_CS1#_4MB SPI_CS2#_TPM
AV2 AW3 AV3 AW2 AU4 AU3 AU2 AU1
SMBUS, SMLINK
SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#
GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C2/SMBALERT# GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_C5/SML0ALERT# GPP_C6/SML1CLK GPP_C7/SML1DATA GPP_B23/SML1ALERT#/PCHHOT#
SPI - TOUCH
SPI0_MOSI
SPI_SI
1
@
RC62
2 8.2K_0402_5% [25]
M2 M3 J4 V1 V2 M1
RC107 1 2 0_0402_5% All_GPU_PWRGD_R GPU_EVENT# [28] GPU_EVENT# EC_SCI# [57] EC_SCI#
All_GPU_PWRGD
GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#
LPC
C LINK
C
[48] [48] [48]
G3 G2 G1
CL_CLK_WLAN CL_DATA_WLAN CL_RST_WLAN#
+3VALW_PCH [57] SPI_SO
1
@
RC65
1
2 8.2K_0402_5%
AW13
KBRST#
KBRST#
10P_0402_50V8-J
[57,58] CC183 EMC_NS@
CL_CLK CL_DATA CL_RST#
SERIRQ
SERIRQ
GPP_A9/CLKOUT_LPC0/ESPI_CLK GPP_A10/CLKOUT_LPC1 GPP_A8/CLKRUN#
GPP_A0/RCIN#
AY11
GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3 GPP_A5/LFRAME#/ESPI_CS# GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A6/SERIRQ SKYLAKE-U_BGA1356 REV = 1 @
2
5 OF 20
R7 R8 R10
PCH_SMB_CLK PCH_SMB_DATA SMBALERT#
R9 W2 W1
SML0ALERT#
W3 V3 AM7
PCH_SML1CLK PCH_SML1DATA SML1ALERT#
AY13 BA13 BB13 AY12 BA12 BA11 AW9 AY9 AW11
DIMM1, DIMM2, Security EEPROM, Click Pad
EC,dGPU,Thermal Sensor
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME#
SUS_STAT#
[57] [57] [57] [57] [57]
RC63 0_0402_5% 1 @ 2
PCH_PCI_CLK_R
1 EMC@
CLKRUN#
RC64 22_0402_5%
+3VS RC66 8.2K_0402_5% 1 2
? ?
C
1
2
TC7 CLK_PCI_EC
1 10P_0402_50V8-J
[57]
CC184 EMC_NS@
2
Close to UC1
GPP_C5, Internal PD 20K *L: LPC H: eSPI
+3VALW_PCH
1
SML0ALERT# RC67
@
2 1K_0402_5%
B
B
RC71 RC73 RC74 RC75
1 1 1 1
SML1ALERT#
RC77
1
2 2 2 2
2.2K_0402_1% 2.2K_0402_1% 2.2K_0402_1% 2.2K_0402_1%
S
EC_SMB_DA3
[28,57,59,62]
2
G
[28,57,59,62]
Plan to remove QC1 after SDV 5
2 10K_0402_5% GPU_EVENT#
+3VS PCH_SMB_CLK PCH_SMB_DATA PCH_SML1CLK PCH_SML1DATA
EC_SMB_CK3
G
RC212 1
PCH_SML1CLK
G
2 4.7K_0402_5% CP_SMB_CLK 2 4.7K_0402_5% CP_SMB_DAT
+3VS
2
RC72 1 RC76 1
[22,23,63]
5
2 10K_0402_5% SERIRQ 2 10K_0402_5% EC_SCI# 2 10K_0402_5% KBRST#
CP_SMB_CLK
SB00000YS00 2N7002KDWH_SOT363-6 QC2A 6 1
G
RC179 1 RC180 1 RC181 1
PCH_SMB_CLK
S
Place RC179,180,181 close together
SB00000YS00 2N7002KDWH_SOT363-6 QC1A 6 1
D
+3VALW_PCH
D
+3VS
Add RC212 PU by NV suggestion CP_SMB_DAT
PCH_SML1DATA 3
[22,23,63]
4
S
4
D
PCH_SMB_DATA 3
S
2 1K_0402_5%
D
@
QC1B 2N7002KDWH_SOT363-6 SB00000YS00
QC2B 2N7002KDWH_SOT363-6 SB00000YS00
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification 2015/09/01
Deciphered Date
2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
KBL(7/16):LPC/SPI/SMBUS/CL Size Document Number Custom
Date: 5
4
3
2
Re v 2.0
KENOBI
Thursday, August 25, 2016 1
Sheet
11
of
82
5
4
3
+VCC_ST
D
2
1
D
SKL_ULT
UC1K
1
SYSTEM POWER MANAGEMENT
+3VALW_PCH
RC85 1K_0402_5%
1 2
[57]
[57]
EC_RSMRST#
VCCST_PG_EC [57] [57]
EC_RSMRST#
PCH_SYSPWROK PCH_PWROK
2
RC78 RC89
PLTRST# SYS_RESET# EC_RSMRST#
10K_0402_5%
1
AN10 B5 AY17
1 TC10 2 60.4_0402_1%
H_CPUPWRGD VCCST_PWRGD PCH_SYSPWROK PCH_PWROK EC_DPWROK_R
B6 BA20 BB20
SUSPWRDNACK SUSACK#
AR13 AP11
PCIE_WAKE#
BB15 AM15 AW17 AT15
RC81
1
2 0_0402_5%
RC82
1
2 0_0402_5%
1
TC12
A68 B65
GPP_B12/SLP_S0# GPD4/SLP_S3# GPD5/SLP_S4# GPD10/SLP_S5#
GPP_B13/PLTRST# SYS_RESET# RSMRST#
SLP_SUS# SLP_LAN# GPD9/SLP_WLAN# GPD6/SLP_A#
PROCPWRGD VCCST_PWRGD SYS_PWROK PCH_PWROK DSW_PWROK
GPD3/PWRBTN# GPD1/ACPRESENT GPD0/BATLOW#
GPP_A13/SUSWARN#/SUSPWRDNACK GPP_A15/SUSACK#
GPP_A11/PME# INTRUDER#
WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC GPD7/RSVD
GPP_B11/EXT_PWR_GATE# GPP_B2/VRALERT#
SKYLAKE-U_BGA1356 REV = 1 @ +3VALW
PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#
1
AN15 AW15 BB17 AN16
PCH_SLP_SUS# PCH_SLP_LAN#
1
PM_SLP_A#
1
BA15 AY15 AU13
PBTN_OUT# AC_PRESENT BATLOW#
AU11 AP16
PME# PCH_INTRUDER#
1
AM10 AM11
EXT_PWR_GATE# VRALERT#
1 1
TC8 PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#
[57] [57] [57]
TC9 PCH_SLP_LAN#
[46]
TC28 PBTN_OUT# AC_PRESENT
[57] [57] +RTCVCC
TC11
2 RC83
1 1M_0402_5%
TC13 TC14
Connect to Power
? ?
Place RC183.184.185.186 close together AC_PRESENT 2 10K_0402_5% 2 BATLOW# 10K_0402_5% PCIE_WAKE# 2 10K_0402_5% PCH_SLP_LAN# 2 10K_0402_5%
1 RC183 1 RC184 1 RC185 1 RC186
C
11 OF 20
AT11 AP15 BA16 AY16
1 RC87
@
C
PBTN_OUT# 2 10K_0402_5%
+3VALW
1 +3VS PCH_PWROK
3
NC
VCC
5
IN_A GND
OUT_Y
4
PLT_RST#
[28,42,46,48,49,57,58]
1
2 PME# 20K_0402_5%
20160408 1.Add RC218 for PME# by BIOS request
2
1
2
RC218
2
PLTRST#
EC_RSMRST#
UC3
RC94 10K_0402_5%
RC88 100K_0402_5%
1
1
2
RC93 10K_0402_5%
TC7SG17FE_SON5
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification 2015/09/01
Deciphered Date
KBL(8/16):SYSTEM PM
2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number Custom
Date: 5
4
3
2
Re v 2.0
KENOBI
Thursday, August 25, 2016 1
Sheet
12
of
82
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
10U_0603_6.3V6-M CC180 10U_0603_6.3V6-M CC179 10U_0603_6.3V6-M CC178 10U_0603_6.3V6-M CC177 10U_0603_6.3V6-M CC176 10U_0603_6.3V6-M CC175 10U_0603_6.3V6-M CC174 10U_0603_6.3V6-M CC173 10U_0603_6.3V6-M CC26 10U_0603_6.3V6-M CC25 10U_0603_6.3V6-M CC24 10U_0603_6.3V6-M CC23
1U_0201_6.3V6-M CC22 1U_0201_6.3V6-M
1U_0402_10V6-K CC50 1U_0402_10V6-K CC49 1U_0402_10V6-K CC48 1U_0402_10V6-K CC47 1U_0402_10V6-K CC46 1U_0402_10V6-K CC45 1U_0402_10V6-K CC44 1U_0402_10V6-K CC43 1U_0402_10V6-K CC42 1U_0402_10V6-K CC41 1U_0402_10V6-K CC40 1U_0402_10V6-K CC39 1U_0402_10V6-K CC38 1U_0402_10V6-K CC37
1U_0201_6.3V6-M
1U_0201_6.3V6-M
1U_0201_6.3V6-M CC72 1U_0201_6.3V6-M CC170 1U_0201_6.3V6-M CC71 1U_0201_6.3V6-M
CC62 1U_0201_6.3V6-M CC61 1U_0201_6.3V6-M
CC36 1U_0201_6.3V6-M CC35 1U_0201_6.3V6-M
CC21 1U_0201_6.3V6-M CC20 1U_0201_6.3V6-M CC19 10U_0402_6.3V6-M
CC34 1U_0201_6.3V6-M
CC60 1U_0201_6.3V6-M
CC69 1U_0201_6.3V6-M
CC171 10U_0402_6.3V6-M
CC33 1U_0201_6.3V6-M
CC59 1U_0201_6.3V6-M
CC70 1U_0201_6.3V6-M
CC18 10U_0402_6.3V6-M
CC32 1U_0201_6.3V6-M
CC58 1U_0201_6.3V6-M
CC67 1U_0201_6.3V6-M
CC17 10U_0402_6.3V6-M
CC31 1U_0201_6.3V6-M
CC57 1U_0201_6.3V6-M
CC68 1U_0201_6.3V6-M
CC16 10U_0402_6.3V6-M
CC30 1U_0201_6.3V6-M
CC56 1U_0201_6.3V6-M
CC65 1U_0201_6.3V6-M CC66 1U_0201_6.3V6-M CC64 1U_0201_6.3V6-M
CC55 1U_0201_6.3V6-M CC54 1U_0201_6.3V6-M
CC29 1U_0201_6.3V6-M CC28 1U_0201_6.3V6-M
CC15 10U_0402_6.3V6-M CC14 10U_0402_6.3V6-M CC13
CC27
CC53
CC63
10U_0402_6.3V6-M CC172 10U_0402_6.3V6-M CC79 10U_0402_6.3V6-M CC78 10U_0402_6.3V6-M CC77 10U_0402_6.3V6-M CC76 10U_0402_6.3V6-M CC75 10U_0402_6.3V6-M CC74 10U_0402_6.3V6-M CC73
Re v 2.0 Size Document Number Custom
1
82 of 13 Sheet Thursday, August 25, 2016
Date:
KENOBI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
KBL(9/16):Decoupling 2016/12/31 Deciphered Date
2015/09/01 Issued Date
Title
LC Future Center Secret Data Security Classification
2 3 4 5
1 1 1 1
B
Place decoupling cap on bottom side B
2 2 2 2 2 2
2 2 2
2
1 1 1
2 2
2
1 1 1
2 2 2
1
2 2
1
2 2 2
1 1 1 1 1
1
2 2
2
1 1
2
1 1 1
2 2 2 2 2
1
C
1
2
2
1 1
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1 1 1 1 1
1
C
1
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2
Power 22uF x9, 47uF x8
1 1 1
2
2 2 2
2
2
1 1 1 1 1 1 1 1 1 1 1
[KBL PDG]VCCGT [KBL PDG] EE 10uF x12,1uF x14, Power 47uF x8,22uFx12 [KBL PDG]VCC [KBL PDG] EE 10uF x7, 10uF x8, 1uF x35
D
Place decoupling cap on TOP side +VCC_GT
Place decoupling cap on TOP side +VCC_CORE D
1 2 3 4 5
A A
5
4
3
2
1
GPP_B22, Internal PD 20K
D
Project ID +3VS
*L: SPI H: LPC GSPI1_MOSI
2 RC95
@
1 1K_0402_5%
D
PLANARID0 (GPP_C8)
PLANARID1 (GPP_C9)
PLANARID2 (GPP_C10)
L
14"
UMA
Skylake
H
15"
DIS
Kabylake
+3VS
PLANARID0
*L: Disable ¨ No Reboot 〃 mode H: Enable ¨ No Reboot 〃 mod e
LPSS
[48]
[48]
RF_OFF#
GSPI0_MOSI
AN8 AP7 AP8 AR7
GSPI1_MOSI
AM5 AN7 AP5 AN5
BT_ON
BT_ON
PLANARID0 PLANARID1 PLANARID2
[48] [48] [60] [37]
B
UART2_RX UART2_TX F4_LED# PCH_TSOFF#
UART2_RX UART2_TX F4_LED# PCH_TSOFF#
AB1 AB2 W4 AB3 AD1 AD2 AD3 AD4 U7 U6 U8 U9 AH9 AH10
2
MIC_HW_EN
RC108 0_0402_5%
GPP_D9 GPP_D10 GPP_D11 GPP_D12
GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI
GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL
GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#
GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL GPP_D15/ISH_UART0_RTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL GPP_F4/I2C2_SDA
GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 ? GPP_A23/ISH_GP5 GPP_A12/BM_BUSY#/ISH_GP6
6 OF 20
P2 P3 P4 P1
DCI_CLK DCI_DATA
DCI_CLK DCI_DATA
[55] [55]
M4 N3 N1 N2 AD11 AD12 U1 U2 U3 U4
B
AC1 AC2 F1_LED# AC3 AB4 AY8 BA8 BB7 BA7 AY7 AW7 AP13
F1_LED#
1
[60]
TC17
GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL
1
@
C
ISH
GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI
GPP_F5/I2C2_SCL SKYLAKE-U_BGA1356 AH11 REV = 1 AH12 GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL AF11 AF12
RC104 10K_0402_5%
? SKL_ULT
UC1F
RF_OFF#
2
To enable no reboot on TCO Timer expiration , this signal should be pulled-up to V3.3S through a 1k to 2.2 K ∮5 % resisto r
C
RC54 10K_0402_5% UMA@
1
RC101 10K_0402_5% SKL@
1
PLANARID2
1 1K_0402_5%
2
@
PLANARID1
2
2 RC102
+3VS
1
GSPI0_MOSI
RC99 10K_0402_5%
2
GPP_B18, Internal PD 20K
RC52 10K_0402_5% @ DIS@
2
2
RC96 10K_0402_5% KBL@
1
1
1
To enable boot to LPC, this signal should be pulled up to V3.3S through a 1k to 2.2 K ∮5 % resistor
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification 2015/09/01
Deciphered Date
2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
KBL(10/16):GPIO/CPU/MISC Size Document Number Custom
Date: 5
4
3
2
Re v 2.0
KENOBI
Thursday, August 25, 2016 1
Sheet
14
of
82
5
4
3
2
1
D
D
USB Port Number SKL_ULT
SSIC / USB3
[25] [25]
[25] PCIE_CRX_GTX_N3 [25] PCIE_CRX_GTX_P3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P3
[25] [25]
[25] PCIE_CRX_GTX_N4 [25] PCIE_CRX_GTX_P4 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_P4
GPU
C
Card Reader
HDD
[49] [49]
[42] [42]
[49] PCIE_PRX_DTX_N5 [49] PCIE_PRX_DTX_P5 PCIE_PTX_C_DRX_N5 PCIE_PTX_C_DRX_P5
CC88 CC89
CC90 CC91
CC92 CC93
CC84 CC85
1 2 0.22U_0402_10V6-K 1DIS@ 2 0.22U_0402_10V6-K DIS@ 1 2 0.22U_0402_10V6-K 1DIS@ 2 0.22U_0402_10V6-K DIS@ 1 2 0.22U_0402_10V6-K 1DIS@ 2 0.22U_0402_10V6-K DIS@ 1 2 0.22U_0402_10V6-K 1DIS@ 2 0.22U_0402_10V6-K DIS@ 1 1
2 2 0.1U_0402_10V7-K 0.1U_0402_10V7-K
H13 G13 B17 A17
PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P2
G11 F11 D16 C16
PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P3
H16 G16 D17 C17
PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P4
G15 F15 B19 A19
PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5
F16 E16 C19 D19 G18 F18 D20 C20
SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0
[42] SATA_PRX_DTX_N0 [42] SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0
F20 E20 B21 A21 G21 F21 D21 C21
WLAN
LAN
[48] [48]
[46] [46]
[48] PCIE_PRX_DTX_N9 [48] PCIE_PRX_DTX_P9 PCIE_PTX_C_DRX_N9 PCIE_PTX_C_DRX_P9 [46] PCIE_PRX_DTX_N10 [46] PCIE_PRX_DTX_P10 PCIE_PTX_C_DRX_N10 PCIE_PTX_C_DRX_P10
CC82 CC83
CC80 CC81
1 1
2 2 0.1U_0402_10V7-K 0.1U_0402_10V7-K
1 1
2 2 0.1U_0402_10V7-K 0.1U_0402_10V7-K 1 2 RC115 100_0402_1% TC18 TC19
B
[42] [42]
M.2 SSD [42] [42]
[42] PCIE_PRX_DTX_N11 [42] PCIE_PRX_DTX_P11 PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 [42] PCIE_PRX_DTX_N12 [42] PCIE_PRX_DTX_P12 PCIE_PTX_DRX_N12 PCIE_PTX_DRX_P12
1 1
PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9
E22 E23 B23 A23
PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10
F25 E25 D23 C23
PCIE_RCOMP
F5 E5
XDP_PRDY_N XDP_PREQ_N PIRQA#
D56 D61 BB11
PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 PCIE_PRX_DTX_N12 PCIE_PRX_DTX_P12 PCIE_PTX_DRX_N12 PCIE_PTX_DRX_P12
E28 E27 D24 C24 E30 F30 A25 B25
USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP
PCIE1_RXN/USB3_5_RXN PCIE1_RXP/USB3_5_RXP PCIE1_TXN/USB3_5_TXN PCIE1_TXP/USB3_5_TXP
USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP
PCIE2_RXN/USB3_6_RXN PCIE2_RXP/USB3_6_RXP PCIE2_TXN/USB3_6_TXN PCIE2_TXP/USB3_6_TXP
USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP
PCIE3_RXN PCIE3_RXP PCIE3_TXN PCIE3_TXP
USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP
PCIE4_RXN PCIE4_RXP PCIE4_TXN PCIE4_TXP
USB2N_1 USB2P_1
PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP
USB2N_2 USB2P_2 USB2N_3 USB2P_3
PCIE6_RXN PCIE6_RXP PCIE6_TXN PCIE6_TXP PCIE7_RXN/SATA0_RXN PCIE7_RXP/SATA0_RXP PCIE7_TXN/SATA0_TXN PCIE7_TXP/SATA0_TXP
USB2N_4 USB2P_4 USB2N_5 USB2P_5
USB2
USB2N_6 USB2P_6
PCIE8_RXN/SATA1A_RXN PCIE8_RXP/SATA1A_RXP PCIE8_TXN/SATA1A_TXN PCIE8_TXP/SATA1A_TXP
USB2N_7 USB2P_7 USB2N_8 USB2P_8
PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP PCIE_RCOMPN PCIE_RCOMPP PROC_PRDY# PROC_PREQ# GPP_A7/PIRQA# PCIE11_RXN/SATA1B_RXN PCIE11_RXP/SATA1B_RXP PCIE11_TXN/SATA1B_TXN PCIE11_TXP/SATA1B_TXP PCIE12_RXN/SATA2_RXN PCIE12_RXP/SATA2_RXP PCIE12_TXN/SATA2_TXN PCIE12_TXP/SATA2_TXP
USB2N_9 USB2P_9 USB2N_10 USB2P_10 USB2_COMP USB2_ID USB2_VBUSSENSE GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3# GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2 GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_E8/SATALED#
SKYLAKE-U_BGA1356 REV = 1 @
J6 H6 B13 A13
USB3P2_RXN USB3P2_RXP USB3P2_TXN USB3P2_TXP
USB3P1_RXN USB3P1_RXP USB3P1_TXN USB3P1_TXP
[55] [55] [55] [55]
TYPE C
USB3P2_RXN USB3P2_RXP USB3P2_TXN USB3P2_TXP
[44] [44] [44] [44]
On Board (Lef t)
USB3P4_RXN USB3P4_RXP USB3P4_TXN USB3P4_TXP
USB3P4_RXN USB3P4_RXP USB3P4_TXN USB3P4_TXP
AB9 USB20_N1 AB10 USB20_P1
USB20_N1 USB20_P1
AD6 USB20_N2 AD7 USB20_P2 AH3 USB20_N3 AJ3 USB20_P3 AD9 USB20_N4 AD10 USB20_P4 AJ1 AJ2
USB20_N5 USB20_P5
AF6 USB20_N6 AF7 USB20_P6 AH1 USB20_N7 AH2 USB20_P7 AF8 USB20_N8 AF9 USB20_P8 AG1 USB20_N9 AG2 USB20_P9
Port4
+3VALW_PCH
J10 H10 B15 A15 E10 F10 C15 D15
Port3
USB_OC3#
USB_OC0# USB_OC1# USB_OC2# USB_OC3#
[44] [44] [44] [44]
RC190 1 RC191 1 RC192 1 RC193 1
2 2 2 2
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
On Board (Right-Front)
[55] [55]
C
TYPE C
20160308 1. Add RC215,RC217 for SSD detect
USB20_N2 USB20_P2
[44] [44]
On Board (AOU)
USB20_N3 USB20_P3
[45] [45]
On Board (Right-Back)
USB20_N4 USB20_P4
[44] [44]
On Board (Right-Front)
USB20_N5 USB20_P5
[37] [37]
Touch Panel
USB20_N6 USB20_P6
[48] [48]
BT
USB20_N7 USB20_P7
[37] [37]
CAMERA
USB20_N8 USB20_P8
[37] [37]
IR CAMERA
USB20_N9 USB20_P9
[61] [61]
FPR
SSD_DEVSLP1
RC216
2
SSD_DET#
RC215
2
1 10K_0402_5%
HDD_DEVSLP0
RC110
2
1 10K_0402_5%
PIRQA#
RC113
2
1 10K_0402_5%
RC217
2
1 10K_0402_5%
SSD_DEVSLP1
+3VS
1 10K_0402_5%
@
AH7 AH8 AB6 USBCOMP AG3 USB2_ID AG4 USB2_VBUSSENSE A9 C9 D9 B9
USB_OC0# USB_OC1# USB_OC2# USB_OC3#
J1 J2 J3
HDD_DEVSLP0
H2 H3 G4
1 RC114
2 113_0402_1% USB2_ID
USB_OC1# USB_OC2# USB_OC3#
SSD_DEVSLP1
[44] [44] [44]
B
USB2_VBUSSENSE
HDD_DEVSLP0
[42]
SSD_DEVSLP1
[42]
SSD_DET#
SSD_DET#
2
[25] [25]
[25] PCIE_CRX_GTX_N2 [25] PCIE_CRX_GTX_P2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P2
CC86 CC87
PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P1
USB3P1_RXN USB3P1_RXP USB3P1_TXN USB3P1_TXP
RC116 1K_0402_5%
RC117 1K_0402_5%
1
[25] [25]
[25] PCIE_CRX_GTX_N1 [25] PCIE_CRX_GTX_P1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P1
H8 G8 C13 D13
Port2
USB_OC2#
2
PCIE/USB3/SATA
Reserve
USB_OC1#
1
UC1H
USB_OC0#
[42]
H1
8 OF 20 ? ?
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification 2015/09/01
Deciphered Date
2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
KBL(11/16):PCIE/USB/SATA Size Document Number Custom
Date: 5
4
3
2
Re v 2.0
KENOBI
Thursday, August 25, 2016 1
Sheet
15
of
82
5
4
3
+VCC_CORE
1
G20
+VCC_ST
0_0402_5% 0_0402_5%
B63 VR_SVID_ALRT#_R A63 VR_SVID_CLK D64 VR_SVID_DAT
VCC_SENSE VSS_SENSE
[70] [70]
RC123 100_0402_1%
+VCC_STG
VR_SVID_CLK
VR_SVID_ALRT#_R 1 RC126
+VCC_GT
Place CC109 on bottom side
2
1
2
1
1 2
1 2
1 2
2
+VCC_IO
+VCC_SA
1
14 OF 20 ? ?
1 2
1 2
1
1 2
2
2
RC133 100_0402_1%
VSSSA_SENSE VCCSA_SENSE
[70] [70]
1
1 2
2 100_0402_1% 2 100_0402_1%
2
1
RC135 100_0402_1%
2
1 2
2
1
1U_0402_10V6-K
AK62 AL61
A
1
VCCGTX_SENSE VSSGTX_SENSE
2
1
CC127 1U_0402_10V6-K
VCCGT_SENSE VSSGT_SENSE
VCCIO_SENSE RC129 1 VSSIO_SENSE RC130 1 RC131 H21VSSSA_SENSE_R 1 2 0_0402_5% @ H20VCCSA_SENSE_R 1 2 @
AM23 AM22
1
CC125 1U_0402_10V6-K
J70 J69
2
0_0402_5% RC132 SKYLAKE-U_BGA1356 REV = 1 @
10U_0603_6.3V6-M
2 0_0402_5% 2 0_0402_5%
VSSSA_SENSE VCCSA_SENSE
2
1
CC126 1U_0402_10V6-K
@ @
VCCIO_SENSE VSSIO_SENSE
CC119 10U_0603_6.3V6-M
1 1
VCCPLL_K20 VCCPLL_K21
Place decoupling cap on TOP side
B
1
CC123 1U_0402_10V6-K
RC136 RC137
VCCGT_SENSE VSSGT_SENSE
VCCPLL_OC
AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30
CC118 10U_0603_6.3V6-M
[70] [70]
A
K20 K21
1U_0402_10V6-K
RC134 100_0402_1%
+VCC_SFR
VCCSTG_A22
Place decoupling cap on TOP side
[KBL PDG]VCCSA [KBL PDG]10uF x13, 1uF x7
CC124 1U_0402_10V6-K
+VCC_GT
AL23
2
CC117 10U_0603_6.3V6-M
Preferred to place the 10uF cap on the secondary under the package shadow near VDDQC pin and short to VDDQ rail under with a shape
+VCC_SFROC
VCCST
CC105 1U_0402_10V6-K
[SKL PDG]VCCPLL [SKL PDG]1uF x1
A22
2
1
+VCC_SA
CC122 1U_0402_10V6-K
[SKL PDG]VDDQC [SKL PDG]10uF x1
+VCC_STG
VDDQC
VCCSA_AK23 VCCSA_AK25 VCCSA_G23 VCCSA_G25 VCCSA_G27 VCCSA_G28 VCCSA_J22 VCCSA_J23 VCCSA_J27 VCCSA_K23 VCCSA_K25 VCCSA_K27 VCCSA_K28 VCCSA_K30
2
1
CC116 10U_0603_6.3V6-M
2
Place CC130 on bottom side
AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66
A18
VCCIO_AK28 VCCIO_AK30 VCCIO_AL30 VCCIO_AL42 VCCIO_AM28 VCCIO_AM30 VCCIO_AM42
1
CC103 1U_0402_10V6-K
1
1U_0402_10V6K
0_0402_5%
VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56 VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66
AM40
VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51
AK28 AK30 AL30 AL42 AM28 AM30 AM42
CC121 10U_0603_6.3V6-M
+VCC_SFROC should be sourced from the VDDQ VR
2 CC130
10U_0603_6.3V6-M
CC129
Place CC129 on bottom side
RC128
2
CPU POWER 3 OF 4
CC120
1
+VCC_ST
SKL_ULT
1
CC115 10U_0603_6.3V6-M
+VCC_SFROC
UC1N
AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51
+1.2V
[KBL PDG]VCCIO [KBL PDG]1uF x4
CC104 1U_0402_10V6-K
+1.2V
C
+VCC_IO [KBL PDG]VDDQ [KBL PDG]10uF x4
CC114
+1.2V
VCCGT_N70 VCCGT_N71 VCCGT_R63 VCCGT_R64 VCCGT_R65 VCCGT_R66 VCCGT_R67 VCCGT_R68 VCCGT_R69 VCCGT_R70 VCCGT_R71 VCCGT_T62 VCCGT_U65 VCCGT_U68 VCCGT_U71 VCCGT_W63 VCCGT_W64 VCCGT_W65 VCCGT_W66 VCCGT_W67 VCCGT_W68 VCCGT_W69 VCCGT_W70 VCCGT_W71 VCCGT_Y62
CC102
B
VCCGT_A48 VCCGT_A53 VCCGT_A58 VCCGT_A62 VCCGT_A66 VCCGT_AA63 VCCGT_AA64 VCCGT_AA66 VCCGT_AA67 VCCGT_AA69 VCCGT_AA70 VCCGT_AA71 VCCGT_AC64 VCCGT_AC65 VCCGT_AC66 VCCGT_AC67 VCCGT_AC68 VCCGT_AC69 VCCGT_AC70 VCCGT_AC71 VCCGT_J43 VCCGT_J45 VCCGT_J46 VCCGT_J48 VCCGT_J50 VCCGT_J52 VCCGT_J53 VCCGT_J55 VCCGT_J56 VCCGT_J58 VCCGT_J60 VCCGT_K48 VCCGT_K50 VCCGT_K52 VCCGT_K53 VCCGT_K55 VCCGT_K56 VCCGT_K58 VCCGT_K60 VCCGT_L62 VCCGT_L63 VCCGT_L64 VCCGT_L65 VCCGT_L66 VCCGT_L67 VCCGT_L68 VCCGT_L69 VCCGT_L70 VCCGT_L71 VCCGT_M62 VCCGT_N63 VCCGT_N64 VCCGT_N66 VCCGT_N67 VCCGT_N69
10U_0603_6.3V6-M
[SKL PDG]VCCPLL [SKL PDG]1uF x1
[70]
+1.2V
CC100 10U_0603_6.3V6-M
[SKL PDG]VCCST [SKL PDG]1uF x1
A48 A53 A58 A62 A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71 J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71 M62 N63 N64 N66 N67 N69
N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62
1
SKL_ULT
2
UC1M
CC99 10U_0603_6.3V6-M
2
Place CC110 on bottom side
VR_SVID_ALRT#
? ?
CC98 10U_0603_6.3V6-M
1
1U_0402_10V6K
0_0402_5% CC110
[SKL PDG]VCCSTG [SKL PDG]1uF x1
1U_0402_10V6K
CC109
1U_0402_10V6K
CC108
2
2
VR_SVID_ALRT# 2 220_0402_1%
1
12 OF 20
+VCC_SFR RC127
[KBL PDG]VIDALERT#
Rpu1 RC125 56_0402_1%
CC97
+VCC_ST
[70]
Rs1
VCCEOPIO_SENSE VSSEOPIO_SENSE
+VCC_ST
Place CC109 on bottom side
VR_SVID_CLK
VCCEOPIO_AE62 VCCEOPIO_AG62
1
2
RC124 100_0402_1%
+VCC_ST
CPU POWER 2 OF 4
1
@
VCCOPC_SENSE VSSOPC_SENSE
+VCC_GT
1
[KBL PDG]VIDSCK
Rpu1
VCC_OPC_1P8_G61
SKYLAKE-U_BGA1356 REV = 1 @
+VCC_STG
2
1 2 2 RC121 2 RC122
@ @
[70]
2
AL63 AJ62
C
E32 VCC_SENSE_R 1 E33 VSS_SENSE_R 1
VR_SVID_DAT
1
AE62 AG62
VCCSTG_G20
VCC_OPC_1P8_H63
VR_SVID_DAT
RC120 100_0402_1%
2
AC63 AE63
VIDALERT# VIDSCK VIDSOUT
VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62
RC119 100_0402_1%
1
G61
RSVD_AK32
Rpu2
2
H63
VCC_SENSE VSS_SENSE
+VCC_CORE
[KBL PDG]VIDSOUT
1
AB62 P62 V62
RSVD_K32
D
+VCC_ST
2
AK32
VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42 VCC_J30 VCC_J33 VCC_J37 VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43
1
K32
VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30
G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43
2
CPU POWER 1 OF 4
D
1
SKL_ULT
UC1L +VCC_CORE
A30 A34 A39 A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40 AM32 AM33 AM35 AM37 AM38 G30
2
SKYLAKE-U_BGA1356 REV = 1 @
? ?
2
RC138 100_0402_1%
13 OF 20
Issued Date
Title
LC Future Center Secret Data
Security Classification 2015/09/01
Deciphered Date
KBL(12/16):POWER
2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number Custom
Date: 5
4
3
2
Re v 2.0
KENOBI
Thursday, August 25, 2016 1
Sheet
16
of
82
5
4
3
2
1
+1VALW_PCH
D
Reserve for Sense
VccMPHYGT(Mod PHY Externally Gated Primary 1.0 V: Externally gated primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.)
Resistor
+1.8VALW 0_0603_5% 2
+3VALW_PCH
+1VALW_PCH RC141 1
0_0805_5% 2
RC202 1
0_0805_5% 2
+1VALW
[SKL PDG]VccAPLLEBB [SKL PDG]1uF x1 [SKL PDG]Close N18, Placement type:Edge