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Compal EL5C3/EL531/EL431 2
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DIS M/B Schematic Document Intel Whiskey Lake Processor with DDR4
2018-09-20 3
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LA-H101P REV: 0.A (EVT)
4
4
Security Classification Issued Date
2018/09/21
Compal Secret Data Deciphered Date
Compal Electronics, Inc. 2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
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Title
Cover Page
Size Document Number Custom Date:
R ev 0.A
LA-H101P
Thursday, September 20, 2018 E
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51
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N17S-G0/G2 TDP:18W VRAM(GDDR5) X2 2GB
1
DDR4 2400MHz
PCIe x4 , Gen3 8Gb/s
CH-A DDR4-SO-DIMM X1 CH-B on board RAM x4 1
for DIS
USB Charger
USB2.0 x1, 480Mb/s
NGFF (Key M)
PCIe x4 , Gen3 8Gb/s SATA , Gen3 6Gb/s
PCIE/SATA SSD 2242/2280 conn.
USB2.0 x1, 480Mb/s
TI SN1702001 USB3.1 x1, Gen1 5Gb/s
USB3 redriver
USB3.1 x1, Gen1 5Gb/s
USB Conn. with AOU
Parade PS8713B
NGFF (Key E)
PCIe x1 , Gen1 2.5Gb/s
WLAN/BT 2230 conn.
USB2.0 x1, 480Mb/s
USB3.1 x1, Gen1 5Gb/s
USB3.1 x1, Gen1 5Gb/s
USB3 redriver Parade PS8713B
USB Conn.
USB2.0 x1, 480Mb/s
Whiskey Lake-U
eDP Panel
2
On Sub Board
eDP x2 , HBR 2.7Gb/s
2
FHD LCD USB2.0 x1, 480Mb/s
HDMI Re-driver
HDMI Conn.
DDI x4 , 2.97GT/s
USB2.0 x1, 480Mb/s
SATA , Gen3 6Gb/s
I2C
FingerPrint Int. Camera
PS8407A USB2.0 x1, 480Mb/s
HDD Conn.
15W
Touch Panel HP
HDA
Audio Codec Type-C Conn. USB3.1 Gen1
USB3.1,Gen1
CC/Vconn
USB3.1x1,Gen1
MUX/CC Realtek RTS5448
I2C_3VLP
FAB#TA601
DMIC
Int. Array Mic *2
EC
3
PCIe x1 , Gen1 2.5Gb/s
Card Reader Realtek RTS5232S
VBus
Int. Speaker
Realtek ALC3287
USB2.0 x1, 480Mb/s 3
Combo Jack
SPK
SDIO
SD Card Conn.
On Sub Board
1528pin
5V Switch
BGA I2C
SPI
SPI ROM TouchPad
16MB LPC
Int. KBD
4
Hall Sensor
KBC
LED
4
ENE KB9022
Security Classification Issued Date
Compal Secret Data Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
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Compal Electronics, Inc.
Title
Document Number Size Custom Date:
Block Diagram LA-H101P
Thursday, September 20, 2018 E
Sheet
Re v
0.A
2
of
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Voltage Rails
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BOM Structure Table Item DIS Only Components UMA Only Components HDMI Logo Touch Screen Memory Down - SDP Package Memory Down - DDP Package GPU GC6 Components Un-Mount GPU GC6 Components Connectors Intel CNVi EMI Category ESD Category RF Category Test Point
+5VS
power plane
+3VS +VCCPLL_OC B+
A
+5VALW
+1.2V
+1.05VS_VCCSTG
+3VALW
+2.5V
+VCC_CORE
+1.8VALW
+VCC_GT
+1.05VALW
+VCC_SA +1.05V_VCCST
State
+1.05VS_VCCIO +1.8VS +0.6VS
Keyboard BackLight S0
O
O
O
O
S3
O
O
O
X
O
O
X
X
S5 S4/AC S5 S4/ Battery only
O
X
X
X
S5 S4/AC & Battery don't exist
X
X
X
X
Project select
GPU select
Memory Down select
B
MIC select
EC SM Bus2 address
EC SM Bus1 address Device
Address
Device
Address
Smart Battery
0001 011x 16h
NCT7718W
1001 100x 98h
PCH SM Bus address Device
Address
DDR_JDIMM1 Touch Pad
1010 000x
TypeC 20V_PRTCT
USB 2.0 Port Table BOM Structure
DIS@ UMA@ 45@ TS@ SDP@ DDP@ GC6@ NOGC6@ ME@ CNVi@ EMI@ ESD@ RF@ TP@ KBL@ NOKBL@ S540@ S340@ C340@ S340_14@ S340_15@ N17S_G1@ N17S_G0@ N16V@ N16S@ N16@ N17@ MD@ NO_MD@ Arrary_MIC@ Single_MIC@ 20V_PRTCT@
Item S340_15 MD (Hynix 4GB) S340_15 MD (Micron 4GB) S340_15 MD (Samsung 4GB) C340 MD (Hynix 4GB) C340 MD (Micron 4GB) C340 MD (Samsung 4GB) On Board RAM X76 Resistors S340_15@ VRAM (Hynix 2GB) S340_15@ VRAM (Micron 2GB) S340_15@ VRAM (Samsung 2GB) C340 VRAM (Hynix 2GB) C340 VRAM (Micron 2GB) C340 VRAM (Samsung 2GB) S340_14 MD (Hynix 4GB) S340_14 MD (Micron 4GB) S340_14 MD (Samsung 4GB) S340_14@ VRAM (Hynix 2GB) S340_14@ VRAM (Micron 2GB) S340_14@ VRAM (Samsung 2GB)
BOM Structure
Port
H4G_S340_15@ M4G_S340_15@ S4G_S340_15@ H4G_C340@ M4G_C340@ S4G_C340@ X76RAM@ VH2G_S340_15@ VM2G_S340_15@ VS2G_S340_15@ VH2G_C340@ VM2G_C340@ VS2G_C340@ H4G_S340_14@ M4G_S340_14@ S4G_S340_14@ VH2G_S340_14@ VM2G_S340_14@ VS2G_S340_14@
Device
Address
Internal thermal sensor
1001 111x 9Eh
USB2/3 Port (IO - 1) USB2/3 Port (IO - 2) USB2/3 Port (Type-C) Touch Screen
Camera Fingrt Print
NGFF WLAN+BT
Port 1 2 3 4 5 6
C
Port 0 1A
HDD
1B
SSD1
EC_SMB_CK2
NECP388 +3VS
EC_SMB_DA2 EC_SMB_CK4 SOC_SMBCLK SOC_SML0CLK SOC_SML0DATA EC_SMB_CK2 EC_SMB_DA2
PCH +3VS
BATT
CHARGER
V
+19V_VIN
+3VALW
NECP388 SODIMM
TP
PCH
GSENSOR
THM sensor
V
X
X
X
X
X
X
X
X
V +3VS
X
X
V +3VS
X
V +3VS
X
X
X
X
X
X
X
+3VS
V
X
X
X
X
X
+3VS
V
+3VS
V
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
+3VS
V
X
X
X
X
X
PCH +3VALW
+3VS
ZZZ
H4G_C340@
Full ON
HIGH
S1(Power On Suspend) D
LOW
CardReader NGFF WLAN+BT
0 3 2 1 0
B
SSD
ZZZ
X76 MICRON 4GB MD
S4G_C340@
X76 SAMSUNG 4GB MD
X7680538LA2
X7680538LA3
HIGH HIGH
HIGH HIGH
HIGH HIGH
+VALW
+V
+VS
ON
ON
ON
ZZZ
GPU UV1
ON
ON
ON
M4G_S340_15@
ZZZ
S4G_S340_15@
C
X76 SAMSUNG 4GB MD
X7680438L82
X7680438L83
UC1
H4G_S340_14@
ZZZ
ZZZ
M4G_S340_14@
X76 HYNIX 4GB MD X76 MICRON 4GB MD N17S_G0@
UV1
XXXXXXXXX
N17S_G2@
X76 SAMSUNG 4GB MD
XXXXXXXXX
N17S-G2-A1
UC1
SRD1W i3_R1@
XXXXXXXXX
S4G_S340_14@
SA0000CCB00
PCB
X4E
Clock ON
ZZZ
S340-14
WHL CPU SLP_S1# SLP_S3# SLP_S4# SLP_S5#
H4G_S340_15@
X7680438L81
N17S-G0-A1
SIGNAL
M4G_C340@
ZZZ
X76 HYNIX 4GB MD X76 MICRON 4GB MD
SA0000CC900
STATE
DGPU
C340 ZZZ
V +3VS
PCH +3VALW
SOC_SMBDATA
0 0 1 2 3 1 0
S340-15
X
NECP388 +3VS
EC_SMB_DA4
Lane
ON BOARD RAM * 4 (total 4GB)
X7680538LA1
DGPU
NECP388 +3VL
EC_SMB_DA1
Port 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
USB2/3 Port (IO - 1) USB2/3 Port (IO - 2) USB2/3 Port (Type-C)
X76 HYNIX 4GB MD
EC_SMB_CK1
PCIE Port Table
SATA Port Table
SMBUS Control Table SOURCE
A
USB 3.0 Port Table
GPU SM Bus address
A0h
External USB Port
1 2 3 4 5 6 7 8 9 10
SREJQi 5_R1@
UC1
SRFFW i7_R1@
S340-15 ZZZ
PCB@
ZZZ
S340_15@
C340-14 S340-14 ZZZ
C340@
ZZZ1
S340_14@
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
I3-8145U SA0000C6R20
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
UC1
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
I5-8265U SA0000C6Q20
SRFG1 Pentium 5405U@
I7-8565U SA0000C6P20
PCB
DA8001H6000
X4E S340-15
X4EAF838L51
X4E C340
X4EAF838L01
D
X4E S340-14 XXXXXXXXXX
I3-8145U SA0000C6R30
Compal Secret Data
Security Classification Issued Date
Deciphered Date
2018/09/21
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1
2
3
4
Compal Electronics, Inc. List Notes Document Number Custom LA-H101P Date: Thursday, September 20, 2018 Sheet 3 of 51 Title
Size
5
Rev 0.A
5
4
3
2
1
-PowerMap_DDR4_Volume_NON CS] B+
D
D
C
C
B
B
A
A
Security Classification Issued Date
2018/09/21
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Compal Electronics, Inc.
Title
Power MAP
Size Date:
Document Number
1
Rev
LA-H101P
Thursday, September 20, 2018
Sheet
0.A
4
of
51
5
4
3
S0->S3/DS3
G3->S0
2
S3/ DS3 ->S0
1
S0->S5
+3VL_RTC
+3VL_RTC tPCH01_Min : 9 ms
D
SOC_RTCRST#
SOC_RTCRST#
B+
B+
+3VLP/+5VLP
D
+3VLP/+5VLP
EC_ON
EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW/+3VALW_DSW
+5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW#
PM_BATLOW#
PCH_PWR_EN (SLP_SUS#)
PCH_PWR_EN (SLP_SUS#)
+3V_PRIM
+3V_PRIM
+1.8V_PRIM
+1.8V_PRIM
EXT_PWR_GATE#
If EXT_PWR_GATE# Toffmin is too small, Pwr gate may choose to completely ignore it
EXT_PWR_GATE#
+1.0V_MPHYPLL
+1.0V_MPHYPLL
+1.0V_PRIM_CORE
+1.0V_PRIM_CORE tPCH34_Max : 20 ms
+1.0V_PRIM
tPCH06_Min : 200 us
+1.0V_PRIM
SUSACK#
SUSACK# tPCH02_Min : 10 ms
PCH_DPWROK
PCH_DPWROK tPCH03_Min : 10 ms
EC_RSMRST#
EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms C
AC_PRESENT
AC_PRESENT
ON/OFF
ON/OFF
C
tPCH43_Min : 95 ms PBTN_OUT#
PBTN_OUT# Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
PM_SLP_S5#
PM_SLP_S5# tPCH18_Min : 90 us
ESPI_RST#
ESPI_RST#
PM_SLP_S4#
PM_SLP_S4#
SYSON
SYSON
+1.0V_VCCST/+1.0V_VCCSFR
+1.0V_VCCST/+1.0V_VCCSFR
+1.35V_VDDQ/+1.35V_VCCSFR_OC
+1.35V_VDDQ/+1.35V_VCCSFR_OC
PM_SLP_S3#
PM_SLP_S3#
SUSP#
SUSP# tCPU04 Min : 100 ns
+1.0VS_VCCSTG
+1.0VS_VCCSTG tCPU10 Min : 1 ms
B
+1.0VS_VCCIO
+1.0VS_VCCIO
B
T
+1.05VS_VCCIO 2
RC2
1
2 24.9_0201_1%
CH4 CH3
CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA
CP4 CN4
TS_I2C_RST#
CR26 CP26
EDP_COMP
AG4 AG3 AG2 AG1 AJ4 AJ3 AJ2 AJ1
E
EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1
AH4 AH3
EDP_AUXN EDP_AUXP
1
AM7 +3VS
AC7 AC6 AD4 AD3 AG7 AG6 CN6 CM6 CP7 CP6 CM7
EC_SCI#
CPU_DP2_HPD EC_SCI#
CK11 CG11 CH11
RC1
1
2
10K_0402_5%
From HDMI
EC_SCI# EDP_HPD ENBKL PCH_ENVDD
INVPWM
From eDP
DISP_RCOMP GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE# GPP_E19/DPPB_CTRLDATA GPP_E20/DPPC_CTRLCLK GPP_E21/DPPC_CTRLDATA GPP_E22/DPPD_CTRLCLK GPP_E23/DPPD_CTRLDATA GPP_H16/DDPF_CTRLCLK GPP_H17/DDPF_CTRLDATA
2
WHL-U_BGA1528
Trace width=20 mils, Spacing=25mil, Max length=600mils
1 of 20
+1.05VS_VCCSTG
1
If routed MS, PECI requires 18 mils spacing to other signals
2
RC3 1K_0402_5%
+1.05V_VCCST
3
RC8
1
RC10 2
@
2 1K_0402_5%
H_THERMTRIP#
1 49.9_0402_1%
CATERR#
H_PROCHOT#
RC4
CATERR#
1
2
H_PECI
499_0402_1%
H_PROCHOT#_R H_THERMTRIP#
AA4 AR1 Y4 BJ1 U1 U2 U3 U4 CE9 CN3 CB34 CC35
RC11 2 RC12 2 RC14 2 RC15 2
@
1 49.9_0402_1% 1 49.9_0402_1% 1 49.9_0402_1%
CPU_POPIRCOMP PCH_OPIRCOMP EDRAM_OPIO_RCOMP
@
1 49.9_0402_1%
EOPIO_RCOMP
BP27 BW25 L5 N5
< PU/PD for CMC Debug >
UC1D
CATERR# PECI PROCHOT# THRMTRIP#
PROC_TCK PROC_TDI PROC_TDO PROC_TMS PROC_TRST#
BPM#_0 BPM#_1 BPM#_2 BPM#_3
PCH_TCK PCH_TDI PCH_TDO PCH_TMS GPP_E3/CPU_GP0 PCH_TRST# GPP_E7/CPU_GP1 PCH_JTAGX GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 PROC_PREQ# PROC_PRDY# PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP
T6 U6 Y5 T5 AB6
CPU_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST#
W6 U5 W5 P5 Y6 P6
PCH_JTAG_TCK1 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# CPU_XDP_TCK0
W2 W1
+1.05VS_VCCSTG
SOC_XDP_TMS
RC5
1 CMC@ 2
51_0402_5%
SOC_XDP_TDI
RC6
1 CMC@ 2
51_0402_5%
SOC_XDP_TDO
RC7
1 DCI@
2
51_0402_5%
CPU_XDP_TCK0
RC9
1 DCI@
2
51_0402_5%
PCH_JTAG_TCK1
RC13
1
@
2
51_0402_5%
SOC_XDP_TRST#
RC16
1
@
2
51_0402_5%
3
TP@ T1 TP@ T2
OPC_RCOMP WHL-U_BGA1528 4 of 20
4
4
Security Classification Issued Date
2018/09/21
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. WHL-U(1/12)DDI,EDP,MISC,CMC
Size Document Number Custom Date:
LA-H101P
Thursday, September 20, 2018 E
Sheet
R ev 0.A
6
of
51
5
4
3
2
1
Interleaved Memory D
DDR_A_D[0..15]
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_D[16..31]
DDR_A_D[32..47]
C
DDR_A_D[48..63]
A26 D26 D28 C28 B26 C26 B28 A28 B30 D30 B33 D32 A30 C30 B32 C32 H34 K34 K35 H36 H35 K36 K37 N36 N34 R37 R34 N37 N35 R36 R35 AN35 AN34 AR35 AR34 AN37 AN36 AR36 AR37 AU35 AU34 AW35 AW34 AU37 AU36 AW36 AW37 BA35 BA34 BC35 BC34 BA37 BA36 BC36 BC37 BE35 BE34 BG35 BG34 BE37 BE36 BG36 BG37
D
UC1B
DDR0_DQ_0/DDR0_DQ_0 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_0/DDR0_CKP_0 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR0_DQ_4/DDR0_DQ_4 DDR0_CKP_1/DDR0_CKP_1 DDR0_DQ_5/DDR0_DQ_5 DDR0_DQ_6/DDR0_DQ_6 DDR0_CKE_0/DDR0_CKE_0 DDR0_DQ_7/DDR0_DQ_7 DDR0_CKE_1/DDR0_CKE_1 DDR0_DQ_8/DDR0_DQ_8 DDR0_CKE_2/NC DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_3/NC DDR0_DQ_10/DDR0_DQ_10 DDR0_DQ_11/DDR0_DQ_11 DDR0_CS#_0/DDR0_CS#_0 DDR0_DQ_12/DDR0_DQ_12 DDR0_CS#_1/DDR0_CS#_1 DDR0_DQ_13/DDR0_DQ_13 DDR0_ODT_0/DDR0_ODT_0 DDR0_DQ_14/DDR0_DQ_14 NC/DDR0_ODT_1 DDR0_DQ_15/DDR0_DQ_15 H37 DDR0_DQ_16/DDR0_DQ_32 DDR0_CAB_9/DDR0_MA_0 DDR0_DQ_17/DDR0_DQ_33 DDR0_CAB_8/DDR0_MA_1 DDR0_DQ_18/DDR0_DQ_34 DDR0_CAB_5/DDR0_MA_2 DDR0_DQ_19/DDR0_DQ_35 NC/DDR0_MA_3 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_MA_4 DDR0_DQ_21/DDR0_DQ_37 DDR0_CAA_0/DDR0_MA_5 DDR0_DQ_22/DDR0_DQ_38 DDR0_CAA_2/DDR0_MA_6 DDR0_DQ_23/DDR0_DQ_39 DDR0_CAA_4/DDR0_MA_7 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAA_3/DDR0_MA_8 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAA_1/DDR0_MA_9 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAB_7/DDR0_MA_10 DDR0_DQ_27/DDR0_DQ_43 DDR0_CAA_7/DDR0_MA_11 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAA_6/DDR0_MA_12 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_0/DDR0_MA_13 DDR0_DQ_30/DDR0_DQ_46 DDR0_DQ_31/DDR0_DQ_47 DDR0_CAB_2/DDR0_MA_14 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_1/DDR0_MA_15 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_3/DDR0_MA_16 DDR0_DQ_34/DDR1_DQ_2 DDR0_DQ_35/DDR1_DQ_3 DDR0_CAB_4/DDR0_BA_0 DDR0_DQ_36/DDR1_DQ_4 DDR0_CAB_6/DDR0_BA_1 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_5/DDR0_BG_0 DDR0_DQ_38/DDR1_DQ_6 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_8/DDR0_ACT# DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_9/DDR0_BG_1 DDR0_DQ_41/DDR1_DQ_9 DDR0_DQ_42/DDR1_DQ_10 DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQ_43/DDR1_DQ_11 DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQ_44/DDR1_DQ_12 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQ_45/DDR1_DQ_13 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQ_46/DDR1_DQ_14 DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQ_47/DDR1_DQ_15 DDR0_DQSP_2/DDR0_DQSP_4 DDR0_DQ_48/DDR1_DQ_32 DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQ_49/DDR1_DQ_33 DDR0_DQSP_3/DDR0_DQSP_5 DDR0_DQ_50/DDR1_DQ_34 DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQ_51/DDR1_DQ_35 DDR0_DQSP_4/DDR1_DQSP_0 DDR0_DQ_52/DDR1_DQ_36 DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQ_53/DDR1_DQ_37 DDR0_DQSP_5/DDR1_DQSP_1 DDR0_DQ_54/DDR1_DQ_38 DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQ_55/DDR1_DQ_39 DDR0_DQSP_6/DDR1_DQSP_4 DDR0_DQ_56/DDR1_DQ_40 DDR0_DQSN_7/DDR1_DQSN_5 DDR0_DQ_57/DDR1_DQ_41 DDR0_DQSP_7/DDR1_DQSP_5 DDR0_DQ_58/DDR1_DQ_42 DDR0_DQ_59/DDR1_DQ_43 NC/DDR0_ALERT# DDR0_DQ_60/DDR1_DQ_44 NC/DDR0_PAR DDR0_DQ_61/DDR1_DQ_45 DDR_VREF_CA DDR0_DQ_62/DDR1_DQ_46 DDR0_VREF_DQ_0 DDR0_DQ_63/DDR1_DQ_47 DDR0_VREF_DQ_1 DDR1_VREF_DQ DDR_VTT_CNTL
V32 V31 T32 T31
DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1
U36 U37 U34 U35
DDR_A_CKE0
AE32 AF32 AE31 AF31
DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1
AC37 AC36 AC34 AC35 AA35 AB35 AA37 AA36 AB34 W36 Y31 W34 AA34 AC32
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13
AC31 AB32 Y32
DDR_A_MA14 DDR_A_MA15 DDR_A_MA16
W32 AB31 V34
DDR_A_BA0 DDR_A_BA1 DDR_A_BG0
V35 W35
DDR_A_ACT# DDR_A_BG1
C27 D27 D31 C31 J35 J34 P34 P35 AP35 AP34 AV34 AV35 BB35 BB34 BF34 BF35
DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7
W37 W31 F36 D35 D37 E36 C35
DDR_A_ALERT# DDR_A_PARITY +0.6V_A_VREFCA +0.6V_B_VREFDQ DDR_PG_CTRL
DDR_A_CLK#0 DDR_A_CLK0 TP@ T3 TP@ T4 DDR_A_CKE0
DDR_A_CS#0 TP@ T5 DDR_A_ODT0 TP@ T7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13
DDR_A_MA14 DDR_A_MA15 DDR_A_MA16
DDR_A_BA0 DDR_A_BA1 DDR_A_BG0
DDR_B_D[0..15]
DDR_B_D[16..31]
DDR_B_D[32..47]
DDR_A_ACT# DDR_A_BG1 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7
DDR_B_D[48..63]
DDR_A_ALERT# DDR_A_PARITY
+0.6V_A_VREFCA
Trace width/Spacing >= 20mils +0.6V_B_VREFDQ
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
UC1C
DDR1_DQ_0/DDR0_DQ_16DDR1_CKN_0/DDR1_CKN_0 DDR1_DQ_1/DDR0_DQ_17DDR1_CKP_0/DDR1_CKP_0 DDR1_DQ_2/DDR0_DQ_18DDR1_CKN_1/DDR1_CKN_1 DDR1_DQ_3/DDR0_DQ_19DDR1_CKP_1/DDR1_CKP_1 DDR1_DQ_4/DDR0_DQ_20 DDR1_DQ_5/DDR0_DQ_21DDR1_CKE_0/DDR1_CKE_0 DDR1_DQ_6/DDR0_DQ_22DDR1_CKE_1/DDR1_CKE_1 DDR1_DQ_7/DDR0_DQ_23 DDR1_CKE_2/NC DDR1_DQ_8/DDR0_DQ_24 DDR1_CKE_3/NC DDR1_DQ_9/DDR0_DQ_25 DDR1_DQ_10/DDR0_DQ_26DDR1_CS#_0/DDR1_CS#_0 DDR1_DQ_11/DDR0_DQ_27DDR1_CS#_1/DDR1_CS#_1 DDR1_DQ_12/DDR0_DQ_28 DDR1_ODT_0/DDR1_ODT_0 DDR1_DQ_13/DDR0_DQ_29 NC/DDR1_ODT_1 DDR1_DQ_14/DDR0_DQ_30DDR1_CAB_9/DDR1_MA_0 DDR1_DQ_15/DDR0_DQ_31DDR1_CAB_8/DDR1_MA_1 DDR1_DQ_16/DDR0_DQ_48DDR1_CAB_5/DDR1_MA_2 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_MA_3 DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4 DDR1_DQ_19/DDR0_DQ_51DDR1_CAA_0/DDR1_MA_5 DDR1_DQ_20/DDR0_DQ_52DDR1_CAA_2/DDR1_MA_6 DDR1_DQ_21/DDR0_DQ_53DDR1_CAA_4/DDR1_MA_7 DDR1_DQ_22/DDR0_DQ_54DDR1_CAA_3/DDR1_MA_8 DDR1_DQ_23/DDR0_DQ_55DDR1_CAA_1/DDR1_MA_9 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_7/DDR1_MA_10 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAA_7/DDR1_MA_11 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAA_6/DDR1_MA_12 DDR1_DQ_27/DDR0_DQ_59 DDR1_CAB_0/DDR1_MA_13 DDR1_DQ_28/DDR0_DQ_60 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_2/DDR1_MA_14 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAB_1/DDR1_MA_15 DDR1_DQ_31/DDR0_DQ_63 DDR1_CAB_3/DDR1_MA_16 DDR1_DQ_32/DDR1_DQ_16 DDR1_DQ_33/DDR1_DQ_17DDR1_CAB_4/DDR1_BA_0 DDR1_DQ_34/DDR1_DQ_18DDR1_CAB_6/DDR1_BA_1 DDR1_DQ_35/DDR1_DQ_19DDR1_CAA_5/DDR1_BG_0 DDR1_DQ_36/DDR1_DQ_20 DDR1_DQ_37/DDR1_DQ_21DDR1_CAA_9/DDR1_BG_1 DDR1_DQ_38/DDR1_DQ_22DDR1_CAA_8/DDR1_ACT# DDR1_DQ_39/DDR1_DQ_23 DDR1_DQ_40/DDR1_DQ_24 DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQ_41/DDR1_DQ_25 DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQ_42/DDR1_DQ_26 DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQ_43/DDR1_DQ_27 DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQ_44/DDR1_DQ_28 DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQ_45/DDR1_DQ_29 DDR1_DQSP_2/DDR0_DQSP_6 DDR1_DQ_46/DDR1_DQ_30 DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQ_47/DDR1_DQ_31 DDR1_DQSP_3/DDR0_DQSP_7 DDR1_DQ_48/DDR1_DQ_48 DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQ_49/DDR1_DQ_49 DDR1_DQSP_4/DDR1_DQSP_2 DDR1_DQ_50/DDR1_DQ_50 DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQ_51/DDR1_DQ_51 DDR1_DQSP_5/DDR1_DQSP_3 DDR1_DQ_52/DDR1_DQ_52 DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQ_53/DDR1_DQ_53 DDR1_DQSP_6/DDR1_DQSP_6 DDR1_DQ_54/DDR1_DQ_54 DDR1_DQSN_7/DDR1_DQSN_7 DDR1_DQ_55/DDR1_DQ_55 DDR1_DQSP_7/DDR1_DQSP_7 DDR1_DQ_56/DDR1_DQ_56 DDR1_DQ_57/DDR1_DQ_57 NC/DDR1_ALERT# DDR1_DQ_58/DDR1_DQ_58 NC/DDR1_PAR DDR1_DQ_59/DDR1_DQ_59 DRAM_RESET# DDR1_DQ_60/DDR1_DQ_60 DDR1_DQ_61/DDR1_DQ_61 DDR_COMP_0 DDR1_DQ_62/DDR1_DQ_62 DDR_COMP_1 DDR1_DQ_63/DDR1_DQ_63 DDR_COMP_2
AF28 AF29 AE28 AE29
DDR_B_CLK#0 DDR_B_CLK0 DDR_B_CLK#1 DDR_B_CLK1
T28 T29 V28 V29
DDR_B_CKE0 DDR_B_CKE1
AL37 AL35 AL36 AL34 AG36 AG35 AF34 AG37 AE35 AF35 AE37 AC29 AE36 AB29 AG34 AC28 AB28 AK35
DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13
AJ35 AK34 AJ34
DDR_B_MA14 DDR_B_MA15 DDR_B_MA16
AJ37 AJ36 W29
DDR_B_BA0 DDR_B_BA1 DDR_B_BG0
Y28 W28
DDR_B_BG1 DDR_B_ACT#
H24 G24 C23 D23 G30 H30 L30 N30 AL31 AL30 AU31 AU30 BC31 BC30 BH31 BH30
DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7
Y29 AE34 BU31
DDR_B_ALERT# DDR_B_PARITY DDR_DRAMRST#
BN28 BN27 BN29
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2
DDR_B_CLK#0 DDR_B_CLK0 DDR_B_CLK#1 DDR_B_CLK1 DDR_B_CKE0 DDR_B_CKE1
DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13
DDR_B_MA14 DDR_B_MA15 DDR_B_MA16
DDR_B_BA0 DDR_B_BA1 DDR_B_BG0
C
DDR_B_BG1 DDR_B_ACT# DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7
DDR_B_ALERT# DDR_B_PARITY
DDR_DRAMRST#
RC17 1 RC18 1 RC19 1
2 121_0402_1% 2 80.6_0402_1% 2 100_0402_1%
#543016 PDG1.5 P.168 W=12-15 Space= 20/25 L=500mil
WHL-U_BGA1528
WHL-U_BGA1528
B
J22 H25 G22 H22 F25 J25 G25 F22 D22 C22 C24 D24 A22 B22 A24 B24 G31 G32 H29 H28 G28 G29 H31 H32 L31 L32 N29 N28 L28 L29 N31 N32 AJ29 AJ30 AM32 AM31 AM30 AM29 AJ31 AJ32 AR31 AR32 AV30 AV29 AR30 AR29 AV32 AV31 BA32 BA31 BD31 BD32 BA30 BA29 BD29 BD30 BG31 BG32 BK32 BK31 BG29 BG30 BK30 BK29
3 of 20
B
2 of 20
2 3
2
UC11
NC A GND
VCC Y
CC1 0.1U_0201_10V6K @
1 RC21 100K_0402_5%
RC20 470_0402_5%
5
2
1
+1.2V
2
1 DDR_PG_CTRL
+3VS
1
+1.2V
< For ODT & VTT Power Control > DDR_VTT_CNTL to DDR VTT supplied ramped Default 1 = eSPI is selected for EC
D
SPI ROM
RC26
1
KB_RST#
2 10K_0402_5%
SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#
1
2 8.2K_0402_5%
KB_RST# SERIRQ
SERIRQ
GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_C5/SML0ALERT#
CL_CLK CL_DATA CL_RST#
BV29 BV28
SERIRQ
GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C2/SMBALERT#
GPP_D1/SPI1_CLK/BK1/SBK1 GPP_D2/SPI1_MISO_IO1/BK2/SBK2 GPP_D3/SPI1_MOSI_IO0/BK3/SBK3 GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS0#/BK0/SBK0
CH7 CH8 CH9
+3VS RC28
CH37 CF37 CF36 CF34 CG34 CG36 CG35 CH34 CF20 CG22 CF22 CG23 CH23 CG20
+3VS
C
D
UC1E SOC_SPI_0_CLK SOC_SPI_0_SO SOC_SPI_0_SI SOC_SPI_0_IO2 SOC_SPI_0_IO3 SOC_SPI_0_CS#0
GPP_C6/SML1CLK GPP_C7/SML1DATA GPP_B23/SML1ALERT#/PCHHOT# GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3 GPP_A5/LFRAME#/ESPI_CS# GPP_A14/SUS_STAT#/ESPI_RESET# GPP_A9/CLKOUT_LPC0/ESPI_CLK GPP_A10/CLKOUT_LPC1 GPP_A8/CLKRUN#
GPP_A0/RCIN#/TIME_SYNC1 GPP_A6/SERIRQ
CK14 CH15 CJ15
SOC_SMBCLK SOC_SMBDATA SOC_SMBALERT#
CH14 CF15 CG15
SOC_SML0CLK SOC_SML0DATA SOC_SML0ALERT#
CN15 CM15 CC34
SOC_SML1ALERT#
CA29 BY29 BY27 BV27 CA28 CA27
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME#
BV32 BV30 BY30
LPC_CLK0
SOC_SMBCLK SOC_SMBDATA TP@ T8
SMB (Link to DDR)
TP@ T9 EC_SMB_CK2 EC_SMB_DA2
SML1 (Link to EC, Thermal Sensor)
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME#
RC27
1 EMI@
2 22_0402_5%
CLK_LPC_EC
PM_CLKRUN#
PM_CLKRUN#
C
WHL-U_BGA1528 5 of 20
+3VS
close to SPI ROM SOC_SPI_0_SO SOC_SPI_0_CLK SOC_SPI_0_SI SOC_SPI_0_IO3
RC29 RC31 RC32 RC34
1 1 EMI@ 1 1
2 2 2 2
SOC_SPI_0_SO_R SOC_SPI_0_CLK_R SOC_SPI_0_SI_R SOC_SPI_0_IO3_R
33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5%
From SOC SOC_SPI_0_IO2
B
From EC
RC36 1
2 33_0402_5%
EC_SPI_CLK EC_SPI_MOSI EC_SPI_CS0# EC_SPI_MISO
EC_SPI_CLK EC_SPI_MOSI EC_SPI_CS0# EC_SPI_MISO
< SPI ROM - 16M > SOC_SPI_0_CS#0 SOC_SPI_0_SO_R SOC_SPI_0_IO2_R
1 2 3 4
UC12
CS# VCC DO(IO1) IO IO2 CLK GND DI(IO0)
SOC_SPI_0_IO2_R
RC41 RC42 RC43 RC44
1 EMI@ 1 1 1
2 2 2 2
33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5%
SOC_SPI_0_CLK_R SOC_SPI_0_SI_R SOC_SPI_0_CS#0 SOC_SPI_0_SO_R
EC_SMB_CK2 EC_SMB_DA2
RC30 RC33
1 1
SOC_SML1ALERT#
RC35
1
SOC_SMBCLK SOC_SMBDATA SOC_SML0CLK SOC_SML0DATA
RC37 RC38 RC39 RC40
1 1 1 1
2 2 2 2
PM_CLKRUN#
RC45
1
2 8.2K_0402_5%
2 1K_0402_5% 2 1K_0402_5%
@
2 150K_0402_5%
1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% B
+3VALW
8 7 6 5
XM25QH128AHIG SOP 8P
CC3
1
@
2 0.1U_0201_10V K X5R
SOC_SPI_0_IO3_R SOC_SPI_0_CLK_R SOC_SPI_0_SI_R
1 2
CC4 @EMI@ 10P_0402_50V8J
A
A
Security Classification
2018/09/21
Issued Date
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. WHL-U(3/12)SPI,SMB,LPC,ESPI
Size Document Number Custom Date:
Rev 0.A
LA-H101P
Thursday, September 20, 2018
Sheet
1
8
of
51
5
4
3
2
1
< HD AUDIO > D
D
HDA_BIT_CLK_R
RC46 1 EMI@
2 33_0402_5%
HDA_BIT_CLK
HDA_SYNC_R
RC48 1
2 33_0402_5%
HDA_SYNC
HDA_SDOUT_R
RC47 1
2 33_0402_5%
HDA_SDOUT
HDA_SYNC HDA_BIT_CLK HDA_SDOUT HDA_SDIN0
1
RC49 499_0402_1%
HDA_SYNC/I2S0_SFRM HDA_BCLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD/SNDW1_DATA HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_D23/I2S_MCLK
CLKREQ_CNV#
< To Enable ME Override >
GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET# GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7 GPP_A16/SD_1P8_SEL GPP_D19/DMIC_CLK0/SNDW4_CLK GPP_D20/DMIC_DATA0/SNDW4_DATA SD_1P8_RCOMP GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP GPP_D18/DMIC_DATA1/SNDW3_DATA
CP24 CN24 1
RC51
ME_EN
@
2
0_0402_5%
HDA_SDOUT
CK25 CJ25
HDA_SPKR
HDA_SPKR
CF35
+3VS
GPP_G0/SD_CMD GPP_G1/SD3_DATA0 GPP_G2/SD3_DATA1 GPP_G3/SD3_DATA2 GPP_G4/SD_DATA3 GPP_G5/SD_CD# GPP_G6/SD_CLK GPP_G7/SD_WP
I2S1_SFRM/SNDW2_CLK I2S1_TXD/SNDW2_DATA
CNV_RF_RESET# CJ32 CH32 CH29 CH30
CNV_RF_RESET#
UC1G
BL37 BL34
2
@
BN34 BN37 BN36 BN35 BL36 BL35 CK23
CH36 CL35 CL36 CM35 CN35 CH35 CK36 CK34
BW36 BY31 CK33 CM34
SOC_SD_RCOMP
RC50 1
2 200_0402_1%
GPP_B14/SPKR WHL-U_BGA1528
C
RC55
1
@
2
2.2K_0402_5%
C
HDA_SPKR
7 of 20
SPKR (Internal Pull Down): TOP Swap Override 0 = Disable TOP Swap mode. ==> Default
GPP_H21 XTAL frequency select. 0: 38.4 / 19.2 MHz 1: 24MHz XTAL select.
1 = Enable TOP Swap Mode. UC1I
75K_0402_5%
CNV_RF_RESET#
1 CNVi@ 2 RC52
CR30 CP30
CNV_CRX_DTX_N0 CNV_CRX_DTX_P0
CM30 CN30 CN32 CM32
CNV_CRX_DTX_N1 CNV_CRX_DTX_P1 CNV_CTX_DRX_N0 CNV_CTX_DRX_P0
Follow Jefferson Peak schematic check list.
CP33 CN33
CNV_CTX_DRX_N1 CNV_CTX_DRX_P1
CN31 CP31 CP34 CN34
CLK_CNV_CRX_DTX_N CLK_CNV_CRX_DTX_P CLK_CNV_CTX_DRX_N CLK_CNV_CTX_DRX_P
B
CNV_W T_RCOMP
1 CNVi@ 2
RC56
150_0402_1% For MX230
[11]
GC6_FB_EN1V8
GC6_FB_EN1V8 TP_INT#
W LBT_OFF#
W LBT_OFF#
CP32 CR32 CP20 CK19 CG17 CR14 CP14 CN14 CM14 CJ17 CH17
RC57
1
RC164
@
W LBT_OFF#
2 1K_0402_5%
1
2
SOC_A4W P_PRESENT
CF17
10K_0402_5%
CNV_WR_D0N CNV_WR_D0P
GPP_H18/CPU_C10_GATE# GPP_H19/TIMESYNC_0
CNV_WR_D1N CNV_WR_D1P CNV_WT_D0N CNV_WT_D0P
GPP_H21 GPP_H22 GPP_H23 GPP_F10
CNV_WT_D1N CNV_WT_D1P
GPD7 GPP_F3
CNV_WR_CLKN CNV_WR_CLKP CNV_WT_CLKN CNV_WT_CLKP
GPP_D4/IMGCLKOUT0/BK4/SBK4 GPP_H20/IMGCLKOUT_1
CNV_WT_RCOMP_0 CNV_WT_RCOMP_1 GPP_F0/CNV_PA_BLANKING GPP_F1 GPP_F2 GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS# GPP_F8/CNV_MFUART2_RXD GPP_F9/CNV_MFUART2_TXD
GPP_F12/EMMC_DATA0 GPP_F13/EMMC_DATA1 GPP_F14/EMMC_DATA2 GPP_F15/EMMC_DATA3 GPP_F16/EMMC_DATA4 GPP_F17/EMMC_DATA5 GPP_F18/EMMC_DATA6 GPP_F19/EMMC_DATA7 GPP_F20/EMMC_RCLK GPP_F21/EMMC_CLK GPP_F11/EMMC_CMD GPP_F22/EMMC_RESET#
GPP_F23/A4WP_PRESENT
EMMC_RCOMP
CN27
+3VALW
SOC_C10_GATE#
TP@ T10
CM27 CF25 CN26 CM26 CK17
SOC_GPP_H21
RC53
1
2 4.7K_0201_5%
BV35 CN20
SOC_GPD7
RC54
1
2 100K_0201_5%
CG25 CH25
XTAL INPUT MODE (HVM ONLY) LOW: XTAL INPUT IS SINGLE ENDED HIGH: XTAL IS ATTACHED
CR20 CM20 CN19 CM19 CN18 CR18 CP18 CM18
B
CM16 CP16 CR16 CN16 CK15
SOC_SD_RCOMP
WHL-U_BGA1528 9 of 20
A
A
SOC_GPIO_C10
TO DGPU
RC59
1
@
2 0_0402_5% GPU_EVENT#
GPU_EVENT#
[24]
Security Classification
2018/09/21
Issued Date
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. WHL-U(4/12)HDA,EMMC,SDIO,CSI2
Size Document Number Custom Date:
Rev 0.A
LA-H101P
Thursday, September 20, 2018
Sheet
1
9
of
51
5
4
3
2
1
+3VS UC1J
5/9 Naming Rule
1
RC61
D
RC63 RC64
1 1
RC68
1
10K_0402_5%
CLKREQ_PCIE#1
2 2
10K_0402_5% 10K_0402_5%
CLKREQ_PCIE#3 CLKREQ_PCIE#4
2
10K_0402_5%
2
@
SSD
Card Reader 2 20K_0402_5% 1
CLK_PCIE_N1 CLK_PCIE_P1 CLKREQ_PCIE#1
CLKREQ_PCIE#1
AW2 AY3 CF32
CLKOUT_PCIE_N_0 CLKOUT_PCIE_P_0 GPP_B5/SRCCLKREQ0#
BC1 BC2 CE32
CLK_PCIE_N3 CLK_PCIE_P3 CLKREQ_PCIE#3
CLKREQ_PCIE#3
BH3 BH4 CE31
CLK_PCIE_N4 CLK_PCIE_P4 CLKREQ_PCIE#4
CLKREQ_PCIE#4
BA1 BA2 CE30
GPD8/SUSCLK XTAL_IN XTAL_OUT
CLKOUT_PCIE_N_2 CLKOUT_PCIE_P_2 GPP_B7/SRCCLKREQ2#
CLK_BIASREF CLKIN_XTAL RTCX1 RTCX2
CLKOUT_PCIE_N_3 CLKOUT_PCIE_P_3 GPP_B8/SRCCLKREQ3#
SRTCRST# RTCRST#
CLKOUT_PCIE_N_4 CLKOUT_PCIE_P_4 GPP_B9/SRCCLKREQ4#
BE1 BE2 CF31
SOC_SRTCRST#
2 1U_0201_6.3V6M SE00000UC00
CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P
CLKOUT_PCIE_N_1 CLKOUT_PCIE_P_1 GPP_B6/SRCCLKREQ1#
BD3 BC3 CF30
+3VL_RTC
CC5
CLKREQ_PEG#0
DGPU
WLAN
RC70 1
[21] CLK_PEG_N0 [21] CLK_PEG_P0 [21] CLKREQ_PEG#0
AU1 AU2 BT32
SUSCLK
CK3 CK2
33E_SOC_XTAL24_IN_R 33E_SOC_XTAL24_OUT_R
CJ1 CM3
XCLK_BIASREF CLKIN_XTAL
BN31 BN32
SOC_RTCX1 SOC_RTCX2
BR37 BR34
SOC_SRTCRST# SOC_RTCRST#
XCLK_BIASREF
RC60
1
2 60.4_0402_1%
CLKIN_XTAL
RC65
1
2 10K_0402_5%
D
CLKIN_XTAL
Follow CFL-U PDG_Rev_0.7 Stuff 60.4 ohm(RC110) PD for CNL-U/ WHL-U and CFL-U 33E_SOC_XTAL24_IN_R RC69
CLKOUT_PCIE_N_5 CLKOUT_PCIE_P_5 GPP_B10/SRCCLKREQ5#
1
10 of 20
RC71 1
2 20K_0402_5%
CC6
1
CLRP1
1
2 1U_0201_6.3V6M SE00000UC00 2 SHORT PADS
RC75 1
2 1M_0402_5%
SOC_RTCRST#
RC72 1
@
2 0_0402_5%
EC_CLEAR_CMOS#
LC1
4
WHL-U_BGA1528
1
EMI@
33E_SOC_XTAL24_IN 33_0201_5%
2
@EMI@
1
2
4
3
2 3
DLM0NSN900HY2D_4P 33E_SOC_XTAL24_OUT_R
RC73
1
EMI@
33E_SOC_XTAL24_OUT 33_0201_5%
2
1 RC74
CLR CMOS
< PCH PLTRST Buffer >
SM_INTRUDER#
YC1 24MHZ_18PF_XRCGB24M000F2P51R0 SJ10000UJ00
3
3
C
SOC_PLTRST#
2 2 2
10K_0402_5% 10K_0402_5% 10K_0402_5%
RC76 1
2 0_0402_5%
PCI_RST#
SYS_RESET# PCH_PWROK EC_RSMRST#
2
1
CC9 ESD@ 100P_0402_50V8J SOC_RTCX1
2
2
RC80 100K_0402_5%
RC81
ESD@ 1 CC10 ESD@ 1 CC11 ESD@ 1 CC12
SYS_RESET# 100P_0402_50V8J EC_RSMRST#
2 2
1
100P_0402_50V8J SYS_PWROK 2 100P_0402_50V8J
+3VALW
EC_RSMRST# T11 TP@
WAKE# SYS_PWROK PCH_PWROK
SOC_PLTRST# SYS_RESET# EC_RSMRST#
BJ35 CN10 BR36
H_CPUPWRGD EC_VCCST_PG
AR2 BJ2
SYS_PWROK PCH_PWROK EC_RSMRST#
CR10 BP30 BV34 BY32
WAKE#
2
BU30 BU32 BU34
GPP_B12/SLP_S0# GPD4/SLP_S3# GPD5/SLP_S4# GPD10/SLP_S5#
GPP_B13/PLTRST# SYS_RESET# RSMRST# PROCPWRGD VCCST_PWRGOOD
SLP_SUS# SLP_LAN# GPD9/SLP_WLAN# GPD6/SLP_A#
BP31 SYS_PWROK PCH_PWROK DSW_PWROK
GPD3/PWRBTN# GPD1/ACPRESENT GPD0/BATLOW#
GPP_A13/SUSWARN#/SUSPWRDACK GPP_A15/SUSACK# WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC
INTRUDER# GPP_B11/EXT_PWR_GATE# GPP_B2/VRALERT# INPUT3VSEL
+1.05V_VCCST
1
From EC (Open-Drain)
2 10M_0402_5%
YC2
2
1
B
2 1K_0402_5%
1
32.768KHZ_9PF_X1A000141000200 SJ10000PW00
UC1K
RC82 1
2
SOC_RTCX2
1
1 1 1
C
1
2
CC8 27P_0402_50V8J
+3VALW
4
1
1
NC NC
CC7 27P_0402_50V8J
1
RC77 RC78 RC79
2 200K_0402_1%
BJ37 BU36 BU27 BT29
PM_SLP_S0# PM_SLP_S3# PM_SLP_S4# PM_SLP_S5#
BU29 BT31 BT30 BU37
SLP_WLAN# PM_SLP_A#
BU28 BU35 BV36
PBTN_OUT# AC_PRESENT_R PM_BATLOW#
BR35
SM_INTRUDER#
CC37 CC36
SOC_VRALERT#
BT27
SOC_INPUT3VSEL
TP@T12 PM_SLP_S3# PM_SLP_S4# TP@T13
1 CC13 8.2P_0402_50V8B
2
CC14 8.2P_0402_50V8B
B
TP@T14 TP@T15 RC83
1
+3VALW @
2 0_0402_5%
PBTN_OUT# AC_PRESENT
PM_BATLOW#
RC84 1
AC_PRESENT
RC85 1
@
2 10K_0402_5%
SOC_VRALERT#
RC86 1
@
2 10K_0402_5%
SOC_INPUT3VSEL
RC87 1
@
2 4.7K_0402_5%
2 8.2K_0402_5%
RC88 1
2 4.7K_0402_5%
WHL-U_BGA1528
RC89 1K_0402_5%
2
11 of 20
RC90 1
VCCST_PWRGD
1 2
2 60.4_0402_1%
EC_VCCST_PG
CC15 100P_0402_50V8J ESD@
A
A
Security Classification Issued Date
2018/09/21
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. WHL-U(5/12)CLK,PM,GPIO
Size Document Number Custom Date:
R ev 0.A
LA-H101P
Thursday, September 20, 2018 1
Sheet
10
of
51
5
4
3
2
1
GSPI0_MOSI (Internal Pull Down): No Reboot
+3VS
SA0000B6F00
+3VS
WITHOUT ON-BOARD RAM GSPI0_MOSI
RC97
1
@
2 4.7K_0402_5%
RC98
1
@
2 150K_0402_5% GSPI1_MOSI
4GB
SAMSUNG 2666MHz (K4A8G165WC-BCTD) HYNIX 2666MHz (H5AN8G6NCJR-VKC) MICRON 2666MHz (MT40A512M16LY-075:E) N/A N/A N/A N/A
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
D
OBRAM_ID0 RC94 10K_0402_5% @
RC168 RC169
RC93 10K_0402_5% @
OBRAM_ID1 RC95 10K_0402_5% @
Arrary_MIC@ 2 10K_0402_5% 2 10K_0402_5%
MODEL_SETTING2
Single_MIC@
RC96 10K_0402_5% @
MODEL_SETTING1 (GPP_D12)
Function C340-15
RC94 NO_MD@ 10K_0402_5%
1 1
OBRAM_ID2
2
RC92 10K_0402_5% @
1
N/A
1
1 RC91 10K_0402_5% @
GPP_B19 GPP_B20 GPP_B21 OBRAM_ID0 OBRAM_ID1 OBRAM_ID2
Description
+3VS
2
Capacity +3VS
1 0
Single MIC +3VS
2
1 = LPC Mode
C
SA0000ARD20
1
0 = SPI Mode ==> Default
Arrary MIC
2
Boot BIOS Strap Bit
MODEL_SETTING2 (GPP_D10)
Function
SA0000BMN00
2
4GB GSPI1_MOSI (Internal Pull Down):
N/A
X7680438L81 HYNIX 2666MHz (H5AN8G6NCJR-VKC)S340 HYNIX 2666MHz (H5AN8G6NCJR-VKC)C340 X7680538LA1 MICRON 2666MHz (MT40A512M16LY-075:E)S340X7680438L82 MICRON 2666MHz (MT40A512M16LY-075:E)C340X7680538LA2 SAMSUNG 2666MHz (K4A8G165WC-BCTD)S340 X7680438L83 SAMSUNG 2666MHz (K4A8G165WC-BCTD)C340 X7680538LA3 N/A N/A
1
D
PART NUMBER(R1)
X76
NO_MD@
1
Description
WITHOUT ON-BOARD RAM
1 = Enable No Reboot Mode. (PCH will disable the TCO Timer system reboot feature). This funct i oni s us ef ul when running ITP/XDP.
2
Capacity
0 = Disable No Reboot mode. ==> Default
RC95 NO_MD@ 10K_0402_5%
RC96 NO_MD@ 10K_0402_5%
MODEL_SETTING0 (GPP_D11)
0 0 1
S340-15 S340-14
0 1 0
+3VS RC99 RC100
MODEL_SETTING1
1 2 10K_0402_5% @ 1 C340@ 2 10K_0402_5% RC100 S340_15@ 10K_0402_5%
RC99 S340_14@ 10K_0402_5%
+3VS
+3VS RC166 1 RC167 1
2 2.2K_0402_5% 2 2.2K_0402_5%
I2C1_SDA_TS I2C1_SCL_TS
RC102 1 RC163 1
2 10K_0402_5% 2 4.7K_0402_5%
SOC_GPIO_A7 TS_INT#
RC103 1 RC108 1 RC109 1 RC105 1
2 2 2 2
UART0_RX UART0_TX I2C_0_SDA I2C_0_SCL
49.9K_0402_1% 49.9K_0402_1% 2.2K_0402_5% 2.2K_0402_5%
RC107 RC104
RC107 S340_15@ 10K_0402_5%
SENSOR_EC_INT
GSPI0_MOSI OBRAM_ID0 OBRAM_ID1 OBRAM_ID2 GSPI1_MOSI
+1.8VALW
1 1
2 20K_0201_5% 2 20K_0201_5%
@ @
C
MODEL_SETTING0 RC104 S340_14@ 10K_0402_5%
UC1F SOC_GPIO_A7
RC113 RC114
@ 1 2 10K_0402_5% 1 C340@ 2 10K_0402_5%
CNV_RGI_CRX_DTX CNV_BRI_CRX_DTX
CNV_BRI_CRX_DTX CNV_RGI_CTX_DRX
CNV_BRI_CRX_DTX CNV_RGI_CTX_DRX CNV_BRI_CTX_DRX CNV_RGI_CRX_DTX
CNV_RGI_CRX_DTX UART0_RX UART0_TX
UART0_RX UART0_TX
Place close to PCH Touch Pad
B
I2C1_SDA_TS I2C1_SCL_TS
EC sensor Hub
I2C_2_SDA I2C_2_SCL
GPP_B15/GSPI0_CS0# GPP_A7/PIRQA#/GSPI0_CS1# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI
CA31 CA32 CC29 CC30 CA30 CK20 CG19 CJ20 CH19
GPP_F5/CNV_BRI_RSP GPP_F6/CNV_RGI_DT GPP_F4/CNV_BRI_DT GPP_F7/CNV_RGI_RSP
CR12 CP12 CN12 CM12
GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL
CF27
GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5 GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
CF29 GPP_H4/I2C2_SDA GPP_H5/I2C2_SCL
CH27
CH28 GPP_H6/I2C3_SDA GPP_H7/I2C3_SCL
CJ30
for RMT test
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#
DGPU_PRSNT (GPP_C15)
Function DIS
0 1
UMA Only
CH22 CJ22
GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL
+3VS RC115 1
CJ27 CJ29
DGPU_PRSNT
2 10K_0402_5%
CM24 CN23 CM23 CR24
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL GPP_D15/ISH_UART0_RTS#/GSPI2_CS1# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL
MODEL_SETTING3 MODEL_SETTING2 MODEL_SETTING0 MODEL_SETTING1
CK22 CH20
GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL
GPP_H10/I2C5_SDA/ISH_I2C2_SDA GPP_H11/I2C5_SCL/ISH_I2C2_SCL
GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#
CK12 CJ12
CN22 CR22 CM22 CP22
GPP_D9/ISH_SPI_CS#/GSPI2_CS0# GPP_D10/ISH_SPI_CLK/GSPI2_CLK GPP_D11/ISH_SPI_MISO/GSPI2_MISO GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
GPP_B19/GSPI1_CS0# GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI
CM11 CN11
I2C_0_SDA I2C_0_SCL
Touch Panel
CC27 CC32 CE28 CE27 CE29
CG12 CH12 CF12 CG14
DGPU_PWR_EN DGPU_HOLD_RST# GPU_ALL_PGOOD DGPU_PRSNT
DGPU_PWR_EN [26] DGPU_HOLD_RST# [21] GPU_ALL_PGOOD [26]
BW35 BW34 CA37 CA36 CA35 CA34 BW37
TS_INT# DGPU_SEL0 DGPU_SEL1
TS_INT#
B
[28]
GPP_H8/I2C4_SDA CJ31 GPP_H9/I2C4_SCL WHL-U_BGA1528
+1.8VALW
6 of 20
RC162
2
1
@
20K_0201_5%
CNV_RGI_CTX_DRX
6 Layer / 8 Layer PCB +3VS
RC171 1 RC172 1
@ @
2 10K_0402_5% 2 10K_0402_5%
MODEL_SETTING3
A
A
[9]
GC6_FB_EN1V8
SOC_GPIO_B16
RC121
1
GC6_FB_EN1V8
RC122
1
N16S@ N17S@
2 0_0201_5%
GC6_FB_EN
GC6_FB_EN
[24,25]
TO DGPU
2 0_0201_5%
Security Classification Issued Date
2018/09/21
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. WHL-U(6/12)GPIO,I2C,GSPI
Size Document Number Custom Date:
1
Sheet
R ev 0.A
LA-H101P
Thursday, September 20, 2018
11
of
51
5
4
3
UC1H
D
[21] PCIE_CRX_DTX_N5 [21] PCIE_CRX_DTX_P5 [21] PCIE_CTX_C_DRX_N5 [21] PCIE_CTX_C_DRX_P5
dGPU
CC17 DIS@ 1 CC18 DIS@ 1
PCIE_CTX_DRX_N5 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_P5 2 0.22U_0201_6.3V6M
BW9 BW8 BW4 BW3
PCIE_CTX_DRX_N6 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_P6 2 0.22U_0201_6.3V6M
BU6 BU5 BU4 BU3
[21] PCIE_CRX_DTX_N6 [21] PCIE_CRX_DTX_P6 [21] PCIE_CTX_C_DRX_N6 [21] PCIE_CTX_C_DRX_P6
CC19 DIS@ 1 CC20 DIS@ 1
[21] PCIE_CRX_DTX_N7 [21] PCIE_CRX_DTX_P7 [21] PCIE_CTX_C_DRX_N7 [21] PCIE_CTX_C_DRX_P7
CC16 DIS@ 1 CC21 DIS@ 1
PCIE_CTX_DRX_N7 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_P7 2 0.22U_0201_6.3V6M
BU1
[21] PCIE_CRX_DTX_N8 [21] PCIE_CRX_DTX_P8 [21] PCIE_CTX_C_DRX_N8 [21] PCIE_CTX_C_DRX_P8
CC22 DIS@ 1 CC23 DIS@ 1
PCIE_CTX_DRX_N8 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_P8 2 0.22U_0201_6.3V6M
BU9 BU8 BT4 BT3
BT7 BT6
C
PCIE8_RXN PCIE8_RXP PCIE8_TXN PCIE8_TXP
PCIE4_RXN/USB31_4_RXN PCIE4_RXP/USB31_4_RXP PCIE4_TXN/USB31_4_TXN PCIE4_TXP/USB31_4_TXP
PCIE9_RXN
USB2_1N USB2_1P
BR1
BR2 PCIE9_RXP PCIE9_TXN PCIE9_TXP
USB2_2N USB2_2P
BN6 BN5
PCIE10_RXN
BN10 BN8 BN4 BN3
PCIE_CRX_DTX_N11 PCIE_CRX_DTX_P11 PCIE_CTX_DRX_N11 PCIE_CTX_DRX_P11
BL6 BL5 BN2 BN1
SATA_CRX_DTX_N1 SATA_CRX_DTX_P1 SATA_CTX_DRX_N1 SATA_CTX_DRX_P1
HDD
BK6 BK5 BM4 BM3
PCIE_CRX_DTX_N13 PCIE_CRX_DTX_P13 PCIE_CTX_DRX_N13 PCIE_CTX_DRX_P13
BJ6 BJ5
PCIE_CRX_DTX_N14 PCIE_CRX_DTX_P14 PCIE_CTX_DRX_N14 PCIE_CTX_DRX_P14
SSD1
BL1 BG5 BG6 BL4 BL3
PCIE_CRX_DTX_N15 PCIE_CRX_DTX_P15 PCIE_CTX_DRX_N15 PCIE_CTX_DRX_P15
BE5 BE6 BJ4 BJ3
SATA_CRX_DTX_N2 SATA_CRX_DTX_P2 SATA_CTX_DRX_N2 SATA_CTX_DRX_P2
Colay SATA
RC126 1
PCIE_RCOMPN PCIE_RCOMPP
2 100_0402_1%
PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP
PCIE6_RXN/USB31_6_RXN PCIE6_RXP/USB31_6_RXP PCIE6_TXN/USB31_6_TXN PCIE6_TXP/USB31_6_TXP
PCIE3_RXN/USB31_3_RXN PCIE3_RXP/USB31_3_RXP PCIE3_TXN/USB31_3_TXN PCIE3_TXP/USB31_3_TXP
BR3
NGFF WLAN+BT
PCIE1_RXN/USB31_1_RXN PCIE1_RXP/USB31_1_RXP PCIE1_TXN/USB31_1_TXN PCIE1_TXP/USB31_1_TXP
PCIE5_RXN/USB31_5_RXN PCIE5_RXP/USB31_5_RXP PCIE5_TXN/USB31_5_TXN PCIE5_TXP/USB31_5_TXP
BU2 PCIE7_RXP PCIE7_TXN PCIE7_TXP
BP5 BP6
PCIE_CRX_DTX_N9 PCIE_CRX_DTX_P9 PCIE_CTX_DRX_N9 PCIE_CTX_DRX_P9
Card Reader
B
2
CE6 CE5 CR28 CP28 CN28 CM28
PCIE7_RXN
USB2_3N USB2_3P
PCIE10_RXP BR4 PCIE10_TXN PCIE10_TXP
USB2_4N USB2_4P
PCIE11_RXN/SATA0_RXN PCIE11_RXP/SATA0_RXP PCIE11_TXN/SATA0_TXN PCIE11_TXP/SATA0_TXP
USB2_5N USB2_5P USB2_6N USB2_6P
PCIE12_RXN/SATA1A_RXN PCIE12_RXP/SATA1A_RXP PCIE12_TXN/SATA1A_TXN PCIE12_TXP/SATA1A_TXP
USB2_7N USB2_7P
PCIE13_RXN PCIE13_RXP PCIE13_TXN PCIE13_TXP
USB2_8N USB2_8P USB2_9N USB2_9P
PCIE14_RXN
USB2_10N USB2_10P
BL2 PCIE14_RXP PCIE14_TXN PCIE14_TXP
USB2_COMP USB2_ID USB2_VBUSSENSE
PCIE15_RXN/SATA1B_RXN PCIE15_RXP/SATA1B_RXP PCIE15_TXN/SATA1B_TXN PCIE15_TXP/SATA1B_TXP
GPP_E9/USB2_OC0#/GP_BSSB_CLK GPP_E10/USB2_OC1#/GP_BSSB_DI GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#
PCIE16_RXN/SATA2_RXN PCIE16_RXP/SATA2_RXP PCIE16_TXN/SATA2_TXN PCIE16_TXP/SATA2_TXP
GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2
PCIE_RCOMP_N PCIE_RCOMP_P
GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2
GPP_H12/M2_SKT2/CFG_0 GPP_H13/M2_SKT2/CFG_1 GPP_H14/M2_SKT2/CFG_2 GPP_H15/M2_SKT2/CFG_3
GPP_E8/SATALED#/SPI1_CS1# UFS_RESET#
1
D
CB5 CB6 CA4 CA3 BY8 BY9 CA2 CA1 BY7 BY6 BY4 BY3
USB3_CRX_DTX_N1 USB3_CRX_DTX_P1 USB3_CTX_DRX_N1 USB3_CTX_DRX_P1
USB2.0 / 3.0 Port (IO - 1)
USB3_CRX_DTX_N2 USB3_CRX_DTX_P2 USB3_CTX_DRX_N2 USB3_CTX_DRX_P2
USB2.0 / 3.0 Port (IO - 2)
USB3_CRX_MTX_N3 USB3_CRX_MTX_P3 USB3_CTX_MRX_N3 USB3_CTX_MRX_P3
USB2.0 / 3.0 Port (Type-C)
BW6 BW5 BW2 BW1 CE3 CE4 CE1 CE2 CG3 CG4 CD3 CD4
USB20_N1 USB20_P1
USB2.0 / 3.0 Port (MB - 1)
USB20_N2 USB20_P2
USB2.0 / 3.0 Port (MB - 2)
USB20_N3 USB20_P3
USB2.0 / 3.0 Port (Type-C)
USB20_N4 USB20_P4
Touch Screen
USB20_N6 USB20_P6
Camera
USB20_N7 USB20_P7
FP
C
CG5 CG6 CC1 CC2 CG8 CG9 CB8 CB9 CH5 CH6 CC3 CC4
USB20_N10 USB20_P10
CC5 CE8 CC6
USB2_COMP USB2_ID USB2_SENSE
CK6 CK5 CK8 CK9
USB_OC0# USB_OC1# USB_OC2# USB_OC3#
CP8 CR8 CM8
WL_OFF#
CN8 CM10 CP10
RC123 RC124 RC125
1 1 1
@ @
NGFF WLAN+BT
2 113_0402_1% 2 1K_0402_5% 2 1K_0402_5% USB_OC0# USB_OC1#
Trace length max: 450mils
B
WL_OFF# DEVSLP2
NGFF_SSD_PEDET
WL_OFF#
NGFF_SSD_PEDET
1
RC165
2 1K_0402_5%
@
CN7
+3VALW
AR3 USB_OC0# USB_OC1# USB_OC2# USB_OC3#
WHL-U_BGA1528 8 of 20
RC127 RC128 RC129 RC130
2 2 2 2
1 1 1 1
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
When PCIE16/SATA2 is used as SATA Port 1 (ODD), then PCIE15/SATA1B (M.2 SSD) cannot be used as SATA Port 1.
+3VS
NGFF_SSD_PEDET
A
Security Classification
2018/09/21
Issued Date
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
RC131
1
2 10K_0402_5%
A
Compal Electronics, Inc. WHL-U(7/12)PCIE,USB,SATA
Size Document Number Custom Date:
Rev 0.A
LA-H101P
Thursday, September 20, 2018
Sheet
1
12
of
51
5
4
+1.05VALW TO +1.05V_VCCST
D
RC134
SYSON
1
+1.05V_VCCST
I(Max) : 0.16 A(+1.05V_VCCST) RON(Max) : 25 mohm V drop : 0.004 V 1 2
+1.05VALW EN_1.05V_VCCSTU
3 4
RC135
SUSP#
1
EN_1.8VS
2 0_0402_5%
@
5 6 7
+1.8VALW
@
2
2
ON1
CT1
VBIAS
GND
ON2
CT2 VOUT2 VOUT2
12 11 10 9 8
2 1 2 CC26 8200P_0402_25V7K
+VCCPLL_OC
7
BG1 BG2
0.02A RC136 1
2 0_0402_5% 1 2
BL27 BM26
0.12A
BR11 BT11
0.19A
VOUT
6
+1.05VS_VCCIO_STG
RC137 1
2 0_0805_5%
VCCSTG1 VCCSTG2 VCCPLL_OC1 VCCPLL_OC2 VCCPLL1 VCCPLL2
+1.05VS_VCCIO
2
BP28 BP29
Trace Length Match < 25 mils
BE7 BG7
VSSSA_SENSE VCCSA_SENSE
C
1 2
1 2
1 2
Close to BP11 & BP2
+1.05VS_VCCSTG
PSC Side 1 2
+1.05VS_VCCSTG
RC139 1
+VCC_SA
Close to BR11 & BT11
PSC Side 1 2
Close to BM26
CC38 1U_0201_6.3V6M
2
6A
CC37 1U_0201_6.3V6M
2
EM5201V_DFN8_3X3 SA00008R600
1
BG8 BG10 BH9 BJ8 BJ9 BJ10 BK8 BK25 BK27 BL8 BL9 BL10 BL24 BL26 BM24 BN25
D
+VCCPLL_OC CC36 10U_0402_6.3V6M
1
CC35 10U_0402_6.3V6M
5
CC31 @ 0.1U_0201_10V K X5R
3.679A
14 of 20
PSC Side 1
@ CC34 10U_0402_6.3V6M
GND
VCCSA2 VCCSA1 VCCSA3 VCCSA5 VCCSA6 VCCSA4 VCCSA9 VCCSA7 VCCSA8 VCCSA13 VCCSA14 VCCSA10 VCCSA11 VCCSA12 VCCSA15 VCCSA16
AK24 AK26 AL24 AL25 AL26 AL27 AM25 AM27 BH24 BH25 BH26 BH27 BJ24 BJ26 BP16 BP18
WHL-U_BGA1528
+1.05V_VCCST
VBIAS ON
VCCST1 VCCST2
VSSSA_SENSE VCCSA_SENSE
1uF X1 0.1uF X1
VIN thermal
RSVD1
VCCIO_SENSE VSSIO_SENSE
UC15
VIN1 VIN2
VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11
+1.05VS_VCCIO
CC33 10U_0402_6.3V6M
4
SUSP#
BC28
+1.8VS
@ CC32 10U_0402_6.3V6M
3
+1.05VS_VCCSTG
BP11 BP2
15
I(Max) : 3.675 A(+1.05VS_VCCIO) RON(Max) : 6.2 mohm V drop : 0.019 V 1 2
+1.05V_VCCST
1 2 CC27 1000P_0402_50V7K
+1.05VALW TO +1.05VS_VCCIO
CC30 1U_0201_6.3V6M
C
1
2 0_0402_5%
14 13
AOZ1331 DFN 14P SA0000BKC00
I(Max) : 0.2 A(+1.8VS) RON(Max) : 25 mohm V drop : 0.005 V
+1.05VALW
0.1U_0201_10V K X5R CC29
1
VOUT1 VOUT1
AD36 AH32 AH36 AM36 AN32 AW32 AY36 BE32 BH36 R32 Y36
3.3A
CC28 @ 0.1U_0201_10V6K
+VL
VIN1 VIN1
VIN2 VIN2
RC133 1
1
UC14
GPAD
+1.8VALW TO +1.8VS
+1.05VS_VCCIO
UC1N
2 0_0402_5%
@
1
+1.2V
CC25 @ 0.1U_0201_10V6K
2
2
+VL
CC24 1U_0201_6.3V6M
1
3
Close to BG1 & BG2
2 0_0402_5% +1.2V
PSC Side
BSC Side
+1.05VS_VCCIO
CPU
2
2
1 2
1 2
CC57 1U_0201_6.3V6M
CPU
2
1
CC56 1U_0201_6.3V6M
Underneath
2
1
@ CC55 1U_0201_6.3V6M
2
1
CC54 1U_0201_6.3V6M
2
2
1
@ CC53 1U_0201_6.3V6M
2
1
CC48 10U_0402_6.3V6M
Underneath
2
1
CC47 10U_0402_6.3V6M
2
1
@ CC46 10U_0402_6.3V6M
2
1
@ CC45 10U_0402_6.3V6M
2
1
CC44 10U_0402_6.3V6M
Close to CPU
2
1
CC43 10U_0402_6.3V6M
2
1
CC42 1U_0201_6.3V6M
1
CC41 1U_0201_6.3V6M
2
CC40 1U_0201_6.3V6M
CC39 1U_0201_6.3V6M
2
1
1
CC52 10U_0402_6.3V6M
2 1
1
CC51 10U_0402_6.3V6M
1
@ CC50 10U_0402_6.3V6M
PSC Side
@ CC49 4.7U_0402_6.3V6M
BSC Side B
B
Close to CPU
+1.2V TO +VCCPLL_OC +1.2V
+VCCPLL_OC
I(Max) : 120m A(+VCCPLL_OC) RON(Max) : 6.2 mohm V drop : 0.019 V
A
Security Classification
2018/09/21
Issued Date
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
A
Compal Electronics, Inc. WHL-U(8/12)Power
Size Document Number Custom Date:
Rev 0.A
LA-H101P
Thursday, September 20, 2018
Sheet
1
13
of
51
5
+1.05VALW
1 2
4
3
2
1
+1.05VALW
@ CC61 1U_0201_6.3V6M
1 2
Close to BV18
CC62 1U_0201_6.3V6M
Close to BP20
Imax : 4.982A D
+1.05VALW
1 2
+1.05VALW
+1.05VALW
1 CC63 1U_0201_6.3V6M
2
BP20 BW16 BW18
1 CC64 4.7U_0402_6.3V6M
2
CC65 10U_0402_6.3V6M
BY16 CA14
+1.8VALW
Imax : 0.702A
Close to BV12 +3VALW
Close to BV2
Imax : 0.21A +1.8VALW
1 2
CC68 1U_0201_6.3V6M
Close to CP17 C
+3VALW
1 2
1
@ CC71 1U_0201_6.3V6M
2
@ CC72 0.1U_0201_10V K X5R
D
Close to BT24 CC73 1
Internal LDO DCPDSW
2 1U_0201_6.3V6M
CC15 CD15 CD16 CP17 CB22 CB23 CC22 CC23 CD22 CD23 CP29 BU15 BU22 BV15 BV16 BV18 BV19 BV20 BV22 BW20 BW22 CA12 CA16 CA18 CA19 CA20 CB12 CB14 CB15 BT24 BU14 BV12 BW12 BW14
Close to CP29
+3VALW
BV2 BR15 +3VALW
1 2
@ CC74 0.1U_0201_10V K X5R
+3V_1.8V_HDA
+3VALW
BR24 BT20 BV23 BT18 BT19 BU18 BU19
Close to BR24
B
CC12
RF@
BT22 BP22
+3V_1.8V_HDA
BV14
LC2
1 2 BLM15BB221SN1D_2P SM01000BV00
+1.05VALW
UC1P
VCCPRIM_1P05_1 VCCPRIM_1P05_9 VCCPRIM_1P05_10 BW19 VCCPRIM_1P05_11 VCCPRIM_1P05_12 VCCPRIM_1P05_14
VCCPRIM_3P3_3
+3VALW
RTC Bat t er y
CB16
+3VL_RTC
+3VL_RTC
VCCRTC
VCCPRIM_1P8_1 VCCPRIM_1P8_4 VCCPRIM_1P8_5 VCCPRIM_1P8_8
VCCPRIM_1P05_13 DCPRTC VCCPRIM_1P05_3
VCCPRIM_3P3_4 VCCPRIM_3P3_5 VCCPRIM_3P3_6 VCCPRIM_3P3_7 VCCPRIM_3P3_8 VCCPRIM_3P3_9 VCCPRIM_3P3_10
VCCAPLL_1P05_3 VCCA_BCLK_1P05 VCCAPLL_1P05_1
VCCPRIM_CORE1 VCCPRIM_CORE2 VCCPRIM_CORE3 VCCPRIM_CORE4 VCCPRIM_CORE5 VCCPRIM_CORE6 VCCPRIM_CORE7 VCCPRIM_CORE8 VCCPRIM_CORE9 VCCPRIM_CORE10 VCCPRIM_CORE11 VCCPRIM_CORE12 VCCPRIM_CORE13 VCCPRIM_CORE14 VCCPRIM_CORE15 VCCPRIM_CORE16 VCCPRIM_CORE17 VCCPRIM_CORE18
VCCA_SRC_1P05 VCCA_XTAL_1P05 VCCDPHY_1P24_2 VCCDPHY_1P24_4 VCCDPHY_1P24_1 VCCDPHY_1P24_3 VCCDPHY_EC_1P24 VCCDSW_3P3_2 VCCA_19P2_1P05
BY20 BP24
DCPRTC
CC66 1
@
RC141 1
2 1U_0201_6.3V6M
Close to BP24
BR20
VCCDSW_1P05 VCCAPLL_1P05_4 VCCPRIM_MPHY_1P05_1 VCCPRIM_MPHY_1P05_3
VCCPRIM_3P3_2
BY12 VCCPRIM_MPHY_1P05_4 VCCPRIM_MPHY_1P05_5 BY14 VCCPRIM_MPHY_1P05_6 VCCAMPHYPLL_1P05
VCCPRIM_3P3_1 GPP_B0/CORE_VID0 GPP_B1/CORE_VID1
VCCAPLL_1P05_2
2 0_0402_5%
1 2
CC67 1U_0201_6.3V6M
Close to BR23
BT12 BP14
Saf t ys ugges t i on r emove EEs i de , Keep PW Rs i de
BR14 BU12
+1.05VALW
CP5 BY24 CA24 BY23 CA23 CP25
+VCCDPHY_1.24V Intenal LDO VCCDPHY_EC_1P24 CC69
BT23
1
Close to CP25 1
2 4.7U_0402_6.3V6M
CC70 1U_0201_6.3V6M
2
+1.05VALW
C
BR12 +1.8VALW
VCCPRIM_1P8_2 VCCPRIM_1P8_3 VCCPRIM_1P8_6 VCCPRIM_1P8_7 VCCPRIM_1P8_9
+RTCBATT
W=20mils
BR23
CC18 CC19 CD18 CD19 CP23
Close to CP5
Imax : 0.702A
BW23 +VCCDPHY_1.24V
BP23
+1.8VALW
CB36 CB35
VCCDPHY_EC_1P24
1
VCCDUSB_1P05 VCCDSW_3P3_1
2
VCCHDA VCCSPI VCCPRIM_1P05_4 VCCPRIM_1P05_5 VCCPRIM_1P05_7 VCCPRIM_1P05_8
@ CC75 1U_0201_6.3V6M
R1
1 CNVi@ 2 0_0201_5%
When CNVi is not used in the design: VCCDPHY_1P24 pin shall be disconnected from the VCCLDOSRAM_IN_1P24 pin. The decoupling capacitor shall remain connected to the VCCDPHY_1P24 pin.
Close to CP23
VCCPRIM_1P05_6 VCCPRIM_1P05_2
B
VCCPRIM_MPHY_1P05_2 WHL-U_BGA1528 16 of 20
1 2
CC76 0.1U_0402_25V6 RF@
UC1O
RF request
K12 K14 K15 K17 K18 K20 L25 M24 M26 P24 P26 R24 R25 R26 W25 V24 Y25 Y24
A
VCCOPC1 VCCOPC2 VCCOPC3 VCCOPC4 VCCOPC5 VCCOPC6 VCCOPC7 VCCOPC8 VCCOPC9 VCCOPC10 VCCOPC11 VCCOPC12 VCCOPC13 VCCOPC14
VCCEOPIO1 VCCEOPIO2 VCCEOPIO3 VCCEOPIO4 VCCEOPIO5 VCCEOPIO6 VCCEOPIO7 VCCEOPIO8 VCCEOPIO_SENSE VSSEOPIO_SENSE
AA24 AA26 AB25 AC24 AC25 AC26 AD24 AD26 V25 T25
VCC_OPC_1P8_2 VCC_OPC_1P8_1 VCC_OPC_1P8_4 VCC_OPC_1P8_3 A
WHL-U_BGA1528 15 of 20
VCCOPC and VCCEOPIO for CFL U43e only
Security Classification Issued Date
2018/09/21
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. WHL-U(9/12)Power
Size Document Number Custom
R ev 0.A
LA-H101P
Date:
Thursday, September 20, 2018 1
Sheet
14
of
51
5
4
+VCC_CORE
3
2
+VCC_GT
+VCC_CORE
D
C
BB9 BC24 AY9 BB24
VCCCORE5 VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE6 VCCCORE9 VCCCORE7 VCCCORE8 VCCCORE13 VCCCORE14 VCCCORE15 VCCCORE16 VCCCORE10 VCCCORE11 VCCCORE12 VCCCORE19 VCCCORE17 VCCCORE18 VCCCORE24 VCCCORE25 VCCCORE26 VCCCORE27 VCCCORE28 VCCCORE20 VCCCORE21 VCCCORE22 VCCCORE23 VCCCORE30 VCCCORE32 VCCCORE33 VCCCORE29 VCCCORE31 VCCCORE39 VCCCORE40 VCCCORE41 VCCCORE42 VCCCORE43 VCCCORE34
VCCCORE35 VCCCORE36 VCCCORE37 VCCCORE38 VCCCORE44 VCCCORE45 VCCCORE48 VCCCORE49 VCCCORE50 VCCCORE46 VCCCORE47 VCCCORE51 VCCCORE52 VCCCORE56 VCCCORE57 VCCCORE58 VCCCORE59 VCCCORE53 VCCCORE54 VCCCORE55 VCCCORE63 VCCCORE64 VCCCORE60 VCCCORE61 VCCCORE62 VCCCORE69 VCCCORE65 VCCCORE66 VCCCORE67 VCCCORE68 VCCCORE70 VCCCORE73 VCCCORE71 VCCCORE72 VCCCORE74 VCC_SENSE VSS_SENSE VIDALERT#
RSVD3 RSVD4 RSVD1 RSVD2
VIDSCK VIDSOUT RSVD5 VCCSTG1
AW24 AW25 AW26 AW27 AY24 AY26 BA5 BA7 BA8 BA25 BA27 BB2 BB26 BC5 BC6 BC7 BC9 BC10 BC26 BC27 BD5 BD8 BD10 BD25 BD27 BE9 BE24 BE25 BE26 BE27 BF2 BF9 BF24 BF26 BG27
+VCC_CORE
AN6 AN5
VCCCORE_SENSE VSSCORE_SENSE
AA3
SOC_SVID_ALERT#
AA1
VR_SVID_CLK
AA2
VR_SVID_DATA
VR_SVID_CLK
Y3
Trace Length Match < 25 mils
+1.05VS_VCCSTG
BG3
WHL-U_BGA1528 12 of 20
SVID ALERT
+VCC_GT UC1M
UC1L
AN9 AN10 AN24 AN26 AN27 AP2 AP9 AP24 AP26 AR5 AR6 AR7 AR8 AR10 AR25 AR27 AT9 AT24 AT26 AU5 AU6 AU7 AU8 AU9 AU24 AU25 AU26 AU27 AV2 AV5 AV7 AV10 AV27 AW5 AW6 AW7 AW8 AW9 AW10
1
+1.05V_VCCST
VCCGT8 VCCGT9 VCCGT10 VCCGT1 VCCGT2 VCCGT3 VCCGT4 VCCGT5 VCCGT6 VCCGT7 VCCGT11 VCCGT13 VCCGT14 VCCGT15 VCCGT12 VCCGT16 VCCGT17 VCCGT19 VCCGT20 VCCGT18 VCCGT22 VCCGT23 VCCGT21 VCCGT24 VCCGT25 VCCGT26 VCCGT28 VCCGT27 VCCGT29 VCCGT30 VCCGT32 VCCGT33 VCCGT31 VCCGT34 VCCGT39 VCCGT40 VCCGT41 VCCGT42 VCCGT35 VCCGT36 VCCGT37 VCCGT38 VCCGT49 VCCGT51 VCCGT52 VCCGT53 VCCGT54 VCCGT43 VCCGT44 VCCGT45 VCCGT46 VCCGT47 VCCGT48 VCCGT50 VCCGT62 VCCGT63 VCCGT55 VCCGT56 VCCGT57 VCCGT119
VCCGT58 VCCGT59 VCCGT60 VCCGT61 VCCGT64 VCCGT69 VCCGT70 VCCGT71 VCCGT72 VCCGT65 VCCGT66 VCCGT67 VCCGT68 VCCGT73 VCCGT74 VCCGT75 VCCGT76 VCCGT77 VCCGT78 VCCGT79 VCCGT87 VCCGT88 VCCGT89 VCCGT90 VCCGT80 VCCGT81 VCCGT82 VCCGT83 VCCGT84 VCCGT85 VCCGT86 VCCGT95 VCCGT96 VCCGT91 VCCGT92 VCCGT93 VCCGT94 VCCGT98 VCCGT97 VCCGT100 VCCGT101 VCCGT99 VCCGT102 VCCGT104 VCCGT105 VCCGT106 VCCGT103 VCCGT107 VCCGT108 VCCGT109 VCCGT111 VCCGT112 VCCGT110 VCCGT114 VCCGT113 VCCGT115 VCCGT116 VCCGT117 VCCGT118 VCCGT120
1
B
Place the PU resistors close to CPU
A5 A6 A8 A11 A12 A14 A15 A17 A18 A20 AA9 AB2 AB8 AB9 AB10 AC8 AD9 AE8 AE9 AE10 AF2 AF8 AF10 AG8 AG9 AH9 AJ8 AJ10 AK2 AK9 AL8 AL9 AL10 AM8 B3 B4 B6 B8 B11 B14 B17 B20 C2 C3 C6 C7 C8 C11 C12 C14 C15 C17 C18 C20 D4 D7 D11 D12 D14 Y10
VCCGT_SENSE VSSGT_SENSE
RC147 56_0402_5%
RC148
1
D
C
E3 D2
VCCGT_SENSE VSSGT_SENSE
WHL-U_BGA1528
2 220_0402_5%
VR_ALERT#
B
Trace Length Match < 25 mils
13 of 20
2 SOC_SVID_ALERT#
D15 D17 D18 D20 E4 F5 F6 F7 F8 F11 F14 F17 F20 G11 G12 G14 G15 G17 G18 G20 H5 H6 H7 H8 H11 H12 H14 H15 H17 H18 H20 J7 J8 J11 J14 J17 J20 K2 K11 L7 L8 L10 M9 N7 N8 N9 N10 P2 P8 R9 T8 T9 T10 U8 U10 V2 V9 W8 W9 Y8
(To VR)
+1.05V_VCCST
Place the PU resistors close to CPU 1
SVID DATA
2
RC149 100_0402_1%
VR_SVID_DATA A
VR_SVID_DATA
(To VR)
A
Security Classification
2018/09/21
Issued Date
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. WHL-U(10/12)Power,SVID
Size Document Number Custom Date:
Rev 0.A
LA-H101P
Thursday, September 20, 2018
Sheet
1
15
of
51
5
4
3
2
1
D
D
UC1R
CR34 BT5 BY5 CP35 CM37 CK37 AW1 CM1 BD6 AY4 B34 E35 A4 AE24 AE26 AF25 AG24 AG26 AH24 AH25 B2 B36 C36 C37 CN1 CN2 CN37 CP2 D1 A32 F33 A3 BJ7 CJ36 A36 BK10 CJ4 AB27 BK2 CK1 AB3 BK28 AB30 BK3 CK4 AB33 BK33 CK7 AB36 BK4 CL2 AB4 BK7 CM13 AB7 BL25 CM17 AC10 BL28 CM21 AC27 BL29 CM25 AC30 BL30 CM29 BL31 CM31 AD33 BL32 CM33 AD35
C
B
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72
VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144
UC1S
BT35 D6 AL32 BT36 D8 AL7 D9 AM10 BU11 E23 AM28 E27 AM33 BU23 E29 AM35 BU24 E31 BU25 E33 AN25 BU7 E9 AN28 BV11 F12 AN29 F15 AN30 F18 AN31 BV3 F2 AN7 BV31 F21 AN8 BV33 F24 BV4 F3 AP3 BW11 F4 AP33 BW15 G21 AP36 G27 AP4 G33 AR28 G35 G36 AT33 BW24 G9 AT35 H21 AT36 BW7 H27 AT4 BY11 AU10 BY15 H9 AU28 BY22 J12 AU29 J15
BL7 AE25 BM33 CM5 AE27 BM35 CM9 AE30 BM36 CN13 AE7 BM9 CN17 AF27 BN30 CN21 AF3 BN7 CN25 AF30 CN29 AF33 BP15 AF36 AF4 CN5 AF7 BP25 CN9 AG10 BP3 CP1 BP32 CP11 AH27 BP33 CP13 AH28 BP4 CP15 AH29 BP7 CP19 AH30 CP21 AH31 BR19 CP27 AH33 BR25 AH35 CP37 AJ25 BT15 AJ28 BT16 CP9 AJ7 CR2 AK3 CR36 AK33 D21 AK36 BT25 D25 AK4 BT28 AL28 BT33 D5 AL29
WHL-U_BGA1528
VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216
VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289
UC1T
BY25 J18 AU32 BY28 J21 AV25 BY33 J24 AV28 BY35 J33 AV3 BY36 J36 AV33 J6 AV36 C1 K21 AV4 C21 K22 AV6 C25 K24 AV8 C29 K25 AW28 C33 K27 AW29 C4 K28 AW3 C9 K29 AW30 CA11 K3 AW31 CA15 K30 AY33 CA22 K31 AY35 K32 B12 K4 B15 CA25 K9 B18 CB11 L27 B21 L33 B23 L35 B25 CB18 L36 B27 CB19 L6 B29 CB2 N25 B31 CB20 N27 CB25
N6 B37 CB3 P10 B5 CB33 P3 B7 CB4 P33 B9 CB7 P36 BA10 CC11 P4 BA28 P7 BA3 CC20 R27 BB3 CC25 R28 BB33 CC28 R29 BB36 CC31 R30 BB4 CC7 R31 BC25 CD11 T27 CD12 T30 BC29 CD14 T33 T35 BC32 CD24 T36 CD25 T7 BC8 CE33 U26 BD28 CE35 U7 BD33 CE36 V26 BD35 CE7 V27 BD36 CF11 V3 BE10 CF14 V30 BE28 CF19 V33 BE29 CF2 V36 BE3
WHL-U_BGA1528
17 of 20
VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361
VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395 VSS_396 VSS_397 VSS_398 VSS_399 VSS_400 VSS_401 VSS_402 VSS_403 VSS_404 VSS_405 VSS_406 VSS_407 VSS_408 VSS_409 VSS_410 VSS_411 VSS_412 VSS_413 VSS_414 VSS_415 VSS_416 VSS_417 VSS_418 VSS_419 VSS_420 VSS_421 VSS_422 VSS_423 VSS_424 VSS_425 VSS_426 VSS_427 VSS_428 VSS_429 VSS_430 VSS_431 VSS_432 VSS_433
CF23 V4 BE30 CF28 W10 BE31 CF3 W27 CF4 W30 BF3 CG33 W7 BF33 CG7 BF36 Y26 BF4 CH31 Y27 BG25 Y30 BG28 CJ11 Y33 CJ14 Y35 BH28 CJ19 Y7 BH29 CJ23 BH32 CJ28 BH33 CJ33 BH35 CJ35 BP19 BR16 BY18 BY19 CC16 BU16 CC14 BR22 BU20 CD20 BT14 BP12 CB24 CC24 J5 U24 BD7 AR4 AU4 AW4 BA6 BC4 BE4 BE8 BA4 BD4 BG4 CJ2 CJ3 AM5 CM4 AC5 AG5 CR6
C
B
WHL-U_BGA1528
18 of 20
19 of 20
A
A
Security Classification
2018/09/21
Issued Date
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. WHL-U(11/12)GND
Size Document Number Custom Date:
Rev 0.A
LA-H101P
Thursday, September 20, 2018
Sheet
1
16
of
51
5
4
3
2
1
D
D
UC1Q
T4
CFG0
R4 T3 R3 J4 M4 J3 M3 R2 N2 R1 N1 J2 L2 J1 L1
CFG3 CFG4
+1.05VS_VCCIO
RC150
1
@
2 10K_0402_5%
CFG0
RC151
1
@
2 1K_0402_5%
CFG3
L3 N3 L4 N4 C
CFG_RCOMP
AB5 W4 CG2 CG1
CFG_0
RSVD_TP5 RSVD_TP4
CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15
IST_TRIG RSVD_TP3 RSVD15 RSVD14 TP_1 TP_3
RSVD21 RSVD20 RSVD18 RSVD19
CFG_16 CFG_18 CFG_17 CFG_19
RSVD29 RSVD26 RSVD27
CFG_RCOMP
BV24 BV25
RC152
1
2 49.9_0402_1%
CFG_RCOMP
RC153
1
2 1K_0402_5%
CFG4
G3 G4
BK36 BK35 W3 AM4
B
AM3
CFG3
A35 D34 G2 G1
0 : Enabled; Set DFX enable bit in debug interface MSR
BJ36 BJ34 BK34 BR18
BT9 BT8 BP8 BP9 CR4 CP3 CR3
C
RSVD25 RSVD24
RSVD34 RSVD33
RSVD8 RSVD9
RSVD22 RSVD23
RSVD11 RSVD10 RSVD3 RSVD2
VSS_436 VSS_437
RSVD5 RSVD4
RSVD17 RSVD16
TP1 TP_2 TP_4
RSVD35 RSVD7
VSS_435
RSVD6
RSVD_TP1 RSVD_TP2
DFX Privacy Strap 1 : Disabled; Set DFX disable bit in debug interface MSR
CP36 CN36
ITP_PMODE
RSVD12 RSVD13 H4 H3
F37 F34
RSVD28
RSVD1 RSVD30
ZVM# MSM#
RSVD32 RSVD31
SKTOCC#
AT3 AU3
AN1 AN2 AN4 AN3 AL2 AL1 AL4 AL3 BP34 BP36 BP35
B
C34 A34 B35 CR35 AH26 AJ27
RSVD28
TP@ T2407
Follow Intel suggetion reserve TP
E1
WHL-U_BGA1528
Display Port Presence Strap
CFG4
20 of 20
1 : Disabled; No Physical Display Port at t ac hedt o E mbedded Dis pl ay port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port
A
A
Security Classification
2018/09/21
Issued Date
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. WHL-U(12/12)CFG,RSVD
Size Document Number Custom Date:
Rev 0.A
LA-H101P
Thursday, September 20, 2018
Sheet
1
17
of
51
5
4
3
2
1
Interleaved Memory +DDR_VREF_CA
+DDR_VREF_CA
+DDR_VREF_CA
U1 M1
CD2
MD@
1
.047U_0402_16V7K 2 D
DDR_A_BA0 DDR_A_BA1
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8 L2
DDR_A_BA0 DDR_A_BA1
N2 N8
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0
DDR_A_ODT0 DDR_A_CS#0
A7 B7 F3 G3
MEMRST#
P1
DDR_A_ACT# DDR_A_BG0 DDR_A_ALERT# DDR_A_PARITY
2 240_0402_1%
CK_t CK_c CKE
VSS VSS VSS VSS VSS VSS VSS VSS VSS
DQSU_c DQSU_t DQSL_c DQSL_t RESET
G2 F7 H3 H7 H2 H8 J3 J7
DDR_A_D4 DDR_A_D2 DDR_A_D3 DDR_A_D5 DDR_A_D7 DDR_A_D0 DDR_A_D6 DDR_A_D1
A3 B8 C3 C7 C2 C8 D3 D7
DDR_A_D13 DDR_A_D9 DDR_A_D12 DDR_A_D15 DDR_A_D10 DDR_A_D14 DDR_A_D8 DDR_A_D11
B3 B9 D1 G7 J1 J9 L1 L9 R1 T9
M1
CD3
1
MD@
.047U_0402_16V7K 2
+1.2V
DDR_A_BA0 DDR_A_BA1
N2 N8
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0
DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
NC VPP VPP
96-BALL SDRAM DDR4 K4AAG165WB-MCRC C38 @
DDR_A_MA[0..16]
DDR_A_DQS#[0..7]
K7 K8 K2
K3 L7 L8 M8
U3
VREFCA
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14/WE
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
BA0 BA1
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
DMU/DBIU DML/DBIL
CK_t CK_c CKE
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
ODT CS RAS CAS
Replace with 240 Ohm to Support DDP@
RD1
1 DDP@
VSS VSS VSS VSS VSS VSS VSS VSS VSS
2 240_0402_1%
DDR_A_BG1_R
DDR_A_BG1_R
DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#2 DDR_A_DQS2
A7 B7 F3 G3
MEMRST#
P1
RU2 1 MD@
ACT BG0 TEN ALERT PAR
P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8 L2
E2 E7
A1 A9 C1 D9 F2 F8 G1 G9 J2 J8 B2 E1 E9 G8 K1 K9 M9 N1 T1
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
+1.2V
ZQ
T7 B1 R9
+2.5V
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
ODT CS RAS CAS
L3 M2 N9 P9 T3
DDR_A_ALERT# DDR_A_PARITY
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
DMU/DBIU DML/DBIL
F9
DDR_A_ACT# DDR_A_BG0
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
BA0 BA1
K3 L7 L8 M8
DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#0 DDR_A_DQS0
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14/WE
K7 K8 K2
DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15
RU1 1 MD@
C
VREFCA
E2 E7
+1.2V
+DDR_VREF_CA
U2
2 240_0402_1%
DDR_A_ACT# DDR_A_BG0
A2 A8 C9 D2 D8 E3 E8 F1 H1 H9
DDR_A_ALERT# DDR_A_PARITY
F9 L3 M2 N9 P9 T3 T7 B1 R9
+2.5V
DQSU_c DQSU_t DQSL_c DQSL_t RESET
G2 F7 H3 H7 H2 H8 J3 J7
DDR_A_D18 DDR_A_D19 DDR_A_D21 DDR_A_D22 DDR_A_D16 DDR_A_D23 DDR_A_D20 DDR_A_D17
A3 B8 C3 C7 C2 C8 D3 D7
DDR_A_D24 DDR_A_D26 DDR_A_D25 DDR_A_D27 DDR_A_D29 DDR_A_D30 DDR_A_D28 DDR_A_D31
B3 B9 D1 G7 J1 J9 L1 L9 R1 T9
M1
CD1
MD@
1
.047U_0402_16V7K 2
+1.2V
NC VPP VPP
96-BALL SDRAM DDR4 K4AAG165WB-MCRC C38 @
DDR_A_BA0 DDR_A_BA1
N2 N8 E2 E7
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0
A1 A9 C1 D9 F2 F8 G1 G9 J2 J8
DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15
B2 E1 E9 G8 K1 K9 M9 N1 T1
K7 K8 K2
K3 L7 L8 M8
VREFCA A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14/WE BA0 BA1 DMU/DBIU DML/DBIL
CK_t CK_c CKE
ODT CS RAS CAS
Replace with 240 Ohm to Support DDP@
RD2
1 DDP@
2 240_0402_1%
DDR_A_BG1_R
RU3
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8 L2
+1.2V
ZQ ACT BG0 TEN ALERT PAR
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#4 DDR_A_DQS4
A7 B7 F3 G3
MEMRST#
P1
1 MD@
2 240_0402_1% F9
DDR_A_ACT# DDR_A_BG0
A2 A8 C9 D2 D8 E3 E8 F1 H1 H9
DDR_A_ALERT# DDR_A_PARITY
L3 M2 N9 P9 T3 T7 B1 R9
+2.5V
DQSU_c DQSU_t DQSL_c DQSL_t RESET
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSS VSS VSS VSS
G2 F7 H3 H7 H2 H8 J3 J7
DDR_A_D35 DDR_A_D33 DDR_A_D34 DDR_A_D39 DDR_A_D37 DDR_A_D38 DDR_A_D36 DDR_A_D32
A3 B8 C3 C7 C2 C8 D3 D7
DDR_A_D40 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D47
B3 B9 D1 G7 J1 J9 L1 L9 R1 T9
B2 E1 E9 G8 K1 K9 M9 N1 T1
ACT BG0 TEN ALERT PAR NC VPP VPP
K7 K8 K2
DDR_A_ODT0 DDR_A_CS#0 DDR_A_MA16 DDR_A_MA15
K3 L7 L8 M8
DDR_A_DQS#7 DDR_A_DQS7 DDR_A_DQS#6 DDR_A_DQS6
A7 B7 F3 G3
MEMRST#
P1
Replace with 240 Ohm to Support DDP@
RD3
1 DDP@
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14/WE BA0 BA1 DMU/DBIU DML/DBIL
CK_t CK_c CKE
ODT CS RAS CAS
2 240_0402_1%
DDR_A_BG1_R
A2 A8 C9 D2 D8 E3 E8 F1 H1 H9
1 MD@
2 240_0402_1% F9
DDR_A_ACT# DDR_A_BG0 DDR_A_ALERT# DDR_A_PARITY
L3 M2 N9 P9 T3 T7 B1 R9
+2.5V
DQSU_c DQSU_t DQSL_c DQSL_t RESET
1 MD@ 1 MD@
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSS VSS VSS VSS
G2 F7 H3 H7 H2 H8 J3 J7
DDR_A_D50 DDR_A_D51 DDR_A_D48 DDR_A_D55 DDR_A_D53 DDR_A_D54 DDR_A_D49 DDR_A_D52
A3 B8 C3 C7 C2 C8 D3 D7
DDR_A_D56 DDR_A_D63 DDR_A_D60 DDR_A_D62 DDR_A_D57 DDR_A_D58 DDR_A_D61 DDR_A_D59
D
B3 B9 D1 G7 J1 J9 L1 L9 R1 T9
+1.2V
A1 A9 C1 D9 F2 F8 G1 G9 J2 J8 B2 E1 E9 G8 K1 K9 M9 N1 T1
Replace with 240 Ohm to Support DDP@
RD4
1 DDP@
2 240_0402_1%
DDR_A_BG1_R
C
ZQ ACT BG0 TEN ALERT PAR NC VPP VPP
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
96-BALL SDRAM DDR4 K4AAG165WB-MCRC C38 @
A2 A8 C9 D2 D8 E3 E8 F1 H1 H9
RD7
1 DDP@
2 0_0402_5%
On B o a r d R A M - D a t a M a p p i n g
RD9
1 SDP@
2 0_0402_5%
RD2 SDP@ 0_0402_5% DDR_A_BG1
RD3 SDP@ 0_0402_5%
For SDP@
RD4 SDP@ 0_0402_5%
2 2
CU25 MD@ 1 2
33_0402_1% 33_0402_1%
0.01U_0402_16V7K
RD11 2 MD@
2
+1.2V
RD12 MD@ 1.8K_0402_1%
1 49.9_0402_1%
RD14 1
@
2 0_0402_5%
2
+0.6V_A_VREFCA
+DDR_VREF_CA
DQ
U2
DQ
U3
DQ
U1
DQ
DQL0
D13
DQL0
D29
DQL0
D43
DQL0
D60
DQL1
D12
DQL1
D25
DQL1
D40
DQL1
D61
DQL2
D11
DQL2
D27
DQL2
D42
DQL2
D62
DQL3
D8
DQL3
D24
DQL3
D41
DQL3
D57
DQL4
D10
DQL4
D30
DQL4
D47
DQL4
D58
DQL5
D9
DQL5
D28
DQL5
D45
DQL5
D56
DQL6
D14
DQL6
D31
DQL6
D46
DQL6
D59
DQL7
D15
DQL7
D26
DQL7
D44
DQL7
D63
DQU0
D6
DQU0
D22
DQU0
D38
DQU0
D50
DQU1
D1
DQU1
D17
DQU1
D37
DQU1
D52
DQU2
D7
DQU2
D23
DQU2
D35
DQU2
D51
DQU3
D5
DQU3
D20
DQU3
D32
DQU3
D48
DQU4
D3
DQU4
D19
DQU4
D33
DQU4
D54
DQU5
D4
DQU5
D16
DQU5
D36
DQU5
D53
DQU6
D2
DQU6
D18
DQU6
D39
DQU6
D55
DQU7
D0
DQU7
D21
DQU7
D34
DQU7
D49
1
MEMRST#
2
CD6 MD@ 0.022U_0402_16V7K A
1
1 CD7 @ 100P_0402_50V8J
RD15 MD@ 24.9_0402_1% 2
2
RD13 MD@ 2.7_0402_1% 1
1
2
+1.2V
@ CD5 3300P_0402_50V7K
B
U4
2
1
RD16 MD@ 1.8K_0402_1%
Security Classification Issued Date
2018/09/21
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
1
RU5 RU6
DDR_A_CLK0
DDR_DRAMRST#
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CKE0
VREFCA
RD1 SDP@ 0_0402_5%
DDR_A_D[0..63]
+0.6VS
N2 N8 E2 E7
RU4 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
DDR_A_BA0 DDR_A_BA1 +1.2V
ZQ
96-BALL SDRAM DDR4 K4AAG165WB-MCRC C38 @
CLOCK TERMINATION
A
+1.2V
P3 P7 R3 N7 N3 P8 P2 R8 R2 R7 M3 T2 M7 T8 L2
Co-lay for SDP / DDP Memory DIE
DDR_A_BG1_R
DDR_A_ALERT#
@
.047U_0402_16V7K 2
A1 A9 C1 D9 F2 F8 G1 G9 J2 J8
B
DDR_A_CLK#0
CD4
1
DDR_A_DQS[0..7]
DDR_A_CLK0 DDR_A_CLK#0
U4 M1 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
4
3
2
Title
DDR4 ON BOARD CHIPS
Document Number Size Custom LA-H101P Date:
Thursday, September 20, 2018 1
Re v
0.A Sheet
18
of
51
5
3
2
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
2
1 2
1 2
1 2
1 2
1 2
1 2
2
DDR_A_MA[0..16]
CD42 MD@ 1U_0201_6.3V6M
CD41 MD@ 1U_0201_6.3V6M
CD40 MD@ 1U_0201_6.3V6M
CD39 MD@ 1U_0201_6.3V6M
CD38 MD@ 1U_0201_6.3V6M
CD37 MD@ 1U_0201_6.3V6M
CD36 MD@ 1U_0201_6.3V6M
CD35 @ 1U_0201_6.3V6M
CD34 MD@ 1U_0201_6.3V6M
CU7 MD@ 1U_0201_6.3V6M
CU6 MD@ 1U_0201_6.3V6M
CU5 MD@ 1U_0201_6.3V6M
CU4 MD@ 1U_0201_6.3V6M
CU3 MD@ 1U_0201_6.3V6M
CU2 MD@ 1U_0201_6.3V6M
CU1 @ 1U_0201_6.3V6M
1
1
+1.2V
1
D
4
D
+0.6VS
DDR_A_BA1
DDR_A_MA9 DDR_A_MA2 DDR_A_MA4 DDR_A_BA1
RD29 RD30 RD31 RD32
1 1 1 1
MD@ MD@ MD@ MD@
2 2 2 2
36_0201_5% 36_0201_5% 36_0201_5% 36_0201_5%
DDR_A_MA10 DDR_A_MA3 DDR_A_MA12 DDR_A_BG0
RD33 RD34 RD35 RD36
1 1 1 1
MD@ MD@ MD@ MD@
2 2 2 2
36_0201_5% 36_0201_5% 36_0201_5% 36_0201_5%
DDR_A_MA16 DDR_A_ACT# DDR_A_CS#0 DDR_A_MA15
RD37 RD38 RD39 RD40
1 1 1 1
MD@ MD@ MD@ MD@
2 2 2 2
36_0201_5% 36_0201_5% 36_0201_5% 36_0201_5%
DDR_A_CKE0 DDR_A_ODT0 DDR_A_MA14
RD41 RD42 RD43
1 MD@ 1 MD@ 1 MD@
2 36_0201_5% 2 36_0201_5% 2 36_0201_5%
DDR_A_MA13 DDR_A_MA8 DDR_A_PARITY DDR_A_MA11
RD44 RD45 RD46 RD47
1 1 1 1
2 2 2 2
DDR_A_MA1 DDR_A_BA0 DDR_A_MA7
RD48 RD49 RD50
1 MD@ 1 MD@ 1 MD@
2 36_0201_5% 2 36_0201_5% 2 36_0201_5%
DDR_A_MA5 DDR_A_MA6 DDR_A_MA0
RD51 RD52 RD53
1 MD@ 1 MD@ 1 MD@
2 36_0201_5% 2 36_0201_5% 2 36_0201_5%
DDR_A_BG1_R
RD54
1 DDP@
2 36_0201_5%
4 as near each on board RAM device as possible
2
MD@
MD@
1 2
CD47 10U_0402_6.3V6M
MD@
2
1
CD46 10U_0402_6.3V6M
2
1
CD45 10U_0402_6.3V6M
MD@
C
1
CD44 10U_0402_6.3V6M
2
CD43 10U_0402_6.3V6M
1
DDR_A_BG0
DDR_A_ACT# DDR_A_CS#0
MD@
DDR_A_CKE0 DDR_A_ODT0
MD@ MD@ MD@ MD@
36_0201_5% 36_0201_5% 36_0201_5% 36_0201_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
2
1 2
CU24 @ 1U_0201_6.3V6M
CU23 MD@ 1U_0201_6.3V6M
CU22 MD@ 1U_0201_6.3V6M
CU21 MD@ 1U_0201_6.3V6M
CU20 MD@ 1U_0201_6.3V6M
DDR_A_BA0
2
1 2
B
CD54 @ 10U_0402_6.3V6M
2
1
CD53 MD@ 10U_0402_6.3V6M
2
1
CD52 MD@ 10U_0402_6.3V6M
2
1
CD51 MD@ 10U_0402_6.3V6M
1
CD50 @ 10U_0402_6.3V6M
2
CD49 @ 10U_0402_6.3V6M
CD48 @ 10U_0402_6.3V6M
2
1
2 as near each on board RAM device as possible
B
1
CU19 @ 1U_0201_6.3V6M
2 as near each on board RAM device as possible
CU18 @ 1U_0201_6.3V6M
CU17 MD@ 1U_0201_6.3V6M
CU16 MD@ 1U_0201_6.3V6M
CU15 MD@ 1U_0201_6.3V6M
CU14 @ 1U_0201_6.3V6M
CU13 MD@ 1U_0201_6.3V6M
CU12 MD@ 1U_0201_6.3V6M
CU11 MD@ 1U_0201_6.3V6M
CU10 MD@ 1U_0201_6.3V6M
CU9 @ 1U_0201_6.3V6M
1
+0.6VS
1
+2.5V
DDR_A_PARITY
C
DDR_A_BG1_R
A
A
LA-H101P
Security Classification Issued Date
2018/09/21
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
DDR4 MISC
Size Document Number Custom Date:
R ev 0.A
LA-H101P
Thursday, September 20, 2018 1
Sheet
19
of
51
A
C
D
Standard Type
DDR_B_DQS#[0..7] DDR_B_D[0..63] +1.2V
DDR_B_CKE0 DDR_B_CKE1 DDR_B_CS#0 DDR_B_CS#1
DDR_B_D7
SOC_SMBDATA SOC_SMBCLK
DDR_B_D4
DDR_B_ODT0 DDR_B_ODT1
DDR_B_D17
DDR_B_D6
DDR_B_D21
DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D23
Note: Check voltage tolerance of VREF_DQ at the DIMM socket
Layout Note: Place near JDIMM1
DDR_B_D22 DDR_B_D29 DDR_B_D24
+1.2V
DDR_B_D30
1 2
1 2
1 2
1 2
1 2
1 2
2
1 2
CD16 1U_0201_6.3V6M
CD15 1U_0201_6.3V6M
CD14 1U_0201_6.3V6M
CD13 1U_0201_6.3V6M
CD12 1U_0201_6.3V6M
CD11 1U_0201_6.3V6M
CD10 1U_0201_6.3V6M
CD9 1U_0201_6.3V6M
1
DDR_B_D26
2
4 as near side of the DIMM close to VDD pins DDR_B_CKE0
+1.2V
DDR_B_BG1 DDR_B_BG0
2
1 2
1 2
1 2
1 2
CD25 10U_0402_6.3V6M
1
@ CD24 10U_0402_6.3V6M
2
CD23 10U_0402_6.3V6M
1
@ CD22 10U_0402_6.3V6M
2
CD21 10U_0402_6.3V6M
1
CD20 10U_0402_6.3V6M
2
CD19 10U_0402_6.3V6M
CD18 10U_0402_6.3V6M
@
1
DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA6 DDR_B_MA3 DDR_B_MA1 DDR_B_CLK0 DDR_B_CLK#0
DDR_B_PARITY DDR_B_BA1
Place these caps on the VTT plane close to DIMM
DDR_B_CS#0 DDR_B_MA14
+0.6VS
DDR_B_ODT0 DDR_B_CS#1 DDR_B_ODT1
1 2
1 2
2
1 2
1
CD31
1
@
CD30
2
10U_0402_6.3V6M
10U_0402_6.3V6M
CD29 @ 1U_0201_6.3V6M
CD28 1U_0201_6.3V6M
CD27 1U_0201_6.3V6M
CD26 1U_0201_6.3V6M
1
DDR_B_D33
2
DDR_B_D32 DDR_B_DQS#4 DDR_B_DQS4
3
DDR_B_D36 DDR_B_D35 DDR_B_D45 DDR_B_D44
DDR_B_D47 +3VS
DDR_B_D46
+2.5V
DDR_B_D52 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6
2
1
CD32 0.1U_0201_10V6K
2
@ C2 10U_0402_6.3V6M
1 2
DDR_B_D55
1
C1 2.2U_0402_6.3V6M
CD33 1U_0201_6.3V6M
DDR_B_D50 DDR_B_D61
2
1
+2.5V
DDR_B_D56
close to DIMM DDR_B_D59 DDR_B_D58 SOC_SMBCLK +3VS
145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 253 255 257 259 261
BA1 VDD13 CS0_n WE_n/A14 VDD15 ODT0 CS1_n VDD17 ODT1 VDD19 C1, CS3_n,NC VSS53 DQ37 VSS55 DQ33 VSS57 DQS4_c DQS4_t VSS60 DQ38 VSS62 DQ34 VSS64 DQ44 VSS66 DQ40 VSS68 DM5_n/DBI5_n VSS69 DQ46 VSS71 DQ42 VSS73 DQ52 VSS75 DQ49 VSS77 DQS6_c DQS6_t VSS80 DQ55 VSS82 DQ51 VSS84 DQ61 VSS86 DQ56 VSS88 DM7_n/DBI7_n VSS89 DQ62 VSS91 DQ58 VSS93 SCL VDDSPD VPP1 VPP2 GND1
A10/AP VDD14 BA0 RAS_n/A16 VDD16 CAS_n/A15 A13 VDD18 C0/CS2_n/NC VREFCA SA2 VSS54 DQ36 VSS56 DQ32 VSS58 DM4_n/DBI4_n VSS59 DQ39 VSS61 DQ35 VSS63 DQ45 VSS65 DQ41 VSS67 DQS5_c DQS5_t VSS70 DQ47 VSS72 DQ43 VSS74 DQ53 VSS76 DQ48 VSS78 DM6_n/DBI6_n VSS79 DQ54 VSS81 DQ50 VSS83 DQ60 VSS85 DQ57 VSS87 DQS7_c DQS7_t VSS90 DQ63 VSS92 DQ59 VSS94 SDA SA0 VTT SA1 GND2
146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256 258 260 262
+DIMM_VREF_DQ
2
DDR_B_D9 DDR_B_D12 DDR_B_D2
RD18 2_0402_1% 2 1
20mil
DDR_B_D3
DDR_B_DQS#0 DDR_B_DQS0
+0.6V_B_VREFDQ
1
RD17 1K_0402_1%
1
DDR_B_D5
CD8 0.022U_0402_16V7K
DDR_B_D1 DDR_B_D20
2 RD19 24.9_0402_1%
DDR_B_D16
RD20 1K_0402_1%
DDR_B_D19 DDR_B_D18 DDR_B_D28 DDR_B_D25 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D31 DDR_B_D27
2
DDR_DRAMRST#_R DDR_B_CKE1
1 DDR_B_MA11 DDR_B_MA7
DDR_B_ACT#
DDR_B_ALERT#
2
CD17 100P_0402_50V8J ESD@
DDR_B_MA5 DDR_B_MA4 DDR_B_MA2 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_MA0
+1.2V
DDR_B_MA10 DDR_B_BA0 DDR_B_MA16
+DIMM_VREF_DQ
DDR_B_MA15 DDR_B_MA13
RD23 470_0402_1% @
DDR_B_SA2
DDR_DRAMRST#_R
RD24 1
2 0_0402_5%
@
DDR_DRAMRST#
DDR_B_D38
DDR_B_D39
DDR_B_D37
3
DDR_B_D34 DDR_B_D41 DDR_B_D40
JDIMM1 ADDRESS (PLACE CLOSE TO DIMM)
DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D43
+3VS
DDR_B_D42 DDR_B_D53 DDR_B_D48
@ DDR_B_D54
RD25 0_0402_5%
DDR_B_D51
DDR_B_SA2
DDR_B_SA1
DDR_B_SA0
DDR_B_D60 DDR_B_D57
1
DDR_B_ODT0 DDR_B_ODT1
DDR_B_D0
+1.2V
DDR_B_D10
DDR_B_DQS#7 DDR_B_DQS7
+0.6VS
RD28 @ 0_0402_5%
DDR_B_D63
2
SOC_SMBDATA SOC_SMBCLK
DDR_B_D8
DDR_B_D15
1
DDR_B_CKE0 DDR_B_CKE1 DDR_B_CS#0 DDR_B_CS#1
DDR_B_D13
VSS2 DQ4 VSS4 DQ0 VSS6 DM0_n/DBI0_n DQS0_t VSS7 VSS8 DQ6 DQ7 VSS9 VSS10 DQ2 DQ3 VSS11 VSS12 DQ12 DQ13 VSS13 VSS14 DQ8 DQ9 VSS15 VSS16 DQS1_c DM1_n/DBI_n DQS1_t VSS17 VSS18 DQ15 DQ14 VSS19 VSS20 DQ10 DQ11 VSS21 VSS22 DQ21 DQ20 VSS23 VSS24 DQ17 DQ16 VSS25 VSS26 DQS2_c DM2_n/DBI2_n DQS2_t VSS27 VSS28 DQ22 DQ23 VSS29 VSS30 DQ18 DQ19 VSS31 VSS32 DQ28 DQ29 VSS33 VSS34 DQ24 DQ25 VSS35 VSS36 DQS3_c DM3_n/DBI3_n DQS3_t VSS37 VSS38 DQ30 DQ31 VSS39 VSS40 DQ26 DQ27 VSS41 VSS42 CB5/NC CB4/NC VSS43 VSS44 CB1/NC CB0/NC VSS45 VSS46 DQS8_c DM8_n/DBI_n/NC DQS8_t VSS47 VSS48 CB6/NC CB2/NC VSS49 VSS50 CB7/NC CB3/NC VSS51 VSS52 RESET_n CKE0 CKE1 VDD1 VDD2 BG1 ACT_n BG0 ALERT_n VDD3 VDD4 A12 A11 A9 A7 VDD5 VDD6 A8 A5 A6 A4 VDD7 VDD8 A3 A2 A1 EVENT_n/NF VDD9 VDD10 CK0_t CK1_t/NF CK0_c CK1_c/NF VDD11 VDD12 PARITY A0
2
DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1
VSS1 DQ5 VSS3 DQ1 1 VSS5DQS0_c
2
DDR_B_DQS#1 DDR_B_DQS1
1
DDR_B_D11
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
1
DDR_B_D14
1 3 5 7 9 1 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
2
DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 DDR_B_BG1
DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1
+1.2V JDIMM1
DDR_B_MA[0..16] DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 DDR_B_BG1
1
2-3A to 1 DIMMs/channel
DDR_B_DQS[0..7]
1
2
E
1
B
DDR_B_D62 SOC_SMBDATA DDR_B_SA0 DDR_B_SA1
4
4
LOTES_ADDR0205-P002A ME@ SP07001HW00
Compal Secret Data
Security Classification Issued Date
2018/09/21
Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Compal Electronics, Inc.
Title Size Custom
Date:
DDR4_DIMM
Document Number
Rev 0.A
LA-H101P
Thursday, September 20, 2018 E
Sheet
20
of
51
1
2
3
4
5
UV1A COMMON 1/14 PCI_EXPRESS
PCIE_CRX_DTX_P6 PCIE_CRX_DTX_N6
PCIE_CRX_C_DTX_P7 PCIE_CRX_C_DTX_N7
PCIE_CRX_DTX_P8 PCIE_CRX_DTX_N8
CV21 DIS@ 1 CV22 DIS@ 1
2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K
PCIE_CRX_C_DTX_P8 PCIE_CRX_C_DTX_N8
PCIE_CTX_C_DRX_P8 PCIE_CTX_C_DRX_N8
PCIE_CTX_C_DRX_P8 PCIE_CTX_C_DRX_N8
Near UV1
[10,30,31,33,36]
PCI_RST#
IN1
2
DGPU_HOLD_RST#
IN2
3
[11]
GND
(From PCH)
1
VCC
5
UV6 MC74VHC1G08DFT2G_SC70-5
4
OUT
PLT_RST_VGA_MON#
DIS@ +1.8VGS_+3VGS_AON
2
PLT_RST_VGA_HOLD#
IN2
OUT
4
PLT_RST_VGA#
1
[24]
3
(From GPU)
IN1
GND
1
VCC
5
UV7 MC74VHC1G08DFT2G_SC70-5
RV2 10K_0201_5% DIS@
N16S@
2
C
CLK_REQ
2 1
@
2 0_0402_5%
1
1
2
2
2
G
RV7 10K_0201_5% DIS@
CV29 @ 1U_0402_6.3V6K
+1.8VGS_+3VGS_AON
CLKREQ_PEG#0_R
3
QV150 DIS@ BSS138W-7-F_SOT323-3
1 D
2 0_0402_5%
PEX_TX5 PEX_TX5#
AE12 AF12
PEX_RX5 PEX_RX5#
AC15 AB15
PEX_TX6 PEX_TX6#
NC FOR GF119
PEX_PLL_HVDD PEX_PLL_HVDD
AA8 AA9
PEX_SVDD_3V3
AB8
1 2 0_0402_5% RV460 N16S@
Place near BGA 1
AB16 AC16
PEX_TX7 PEX_TX7#
AF13 AE13
PEX_RX7 PEX_RX7#
AD17 AC17
PEX_TX8 PEX_TX8#
AE15 AF15
PEX_RX8 PEX_RX8#
AC18 AB18
PEX_TX9 PEX_TX9#
VDD_SENSE
F2
VDD_SENSE_GPU
AG15 AG16
PEX_RX9 PEX_RX9#
GND_SENSE
F1
GND_SENSE_GPU
AB19 AC19
PEX_TX10 PEX_TX10#
AF16 AE16
PEX_RX10 PEX_RX10#
AD20 AC20
PEX_TX11 PEX_TX11#
AE18 AF18
PEX_RX11 PEX_RX11#
AC21 AB21
PEX_TX12 PEX_TX12#
AG18 AG19
PEX_RX12 PEX_RX12#
PEX_TSTCLK_OUT PEX_TSTCLK_OUT#
AF22 AE22
PEX_PLL_CLK_OUT PEX_PLL_CLK_OUT#
AD23 AE23
PEX_TX13 PEX_TX13#
AF19 AE19
PEX_RX13 PEX_RX13#
PEX_PLLVDD PEX_PLLVDD
AA14 AA15
PEX_PLLVDD_GPU
AF24 AE24
PEX_TX14 PEX_TX14#
AE21 AF21
PEX_RX14 PEX_RX14# PEX_TX15 PEX_TX15# PEX_RX15 PEX_RX15#
2
1
2
RV445 N17S@
2
1 2
1 2
1
RV446 N16S@
2 B
0_0805_5%
VDD_SENSE_GPU
[50]
GND_SENSE_GPU
[50]
To POWER trace width: 16mils differential voltage sensing. differential signal routing.
C
RV3
2
@
1200_0402_1%
1.0V
Place near BALL
TESTMODE
AD9
GPU_TESTMODE
PEX_TERMP
AF25
PEX_TERMP
[10]
1 2
GPU_TESTMODE
N16S-GT-S-A2_BGA595 @
[24]
1 2
1
1
+1.0VS_DGPU
RV4 N16S@
2
0_0805_5%
Place near BGA
2
RV8 2.49K_0402_1% DIS@
D
Security Classification Issued Date
2017/10/27
Com pal Secre cret Data Deci cip phered red Date Date
2019/04/09
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1
+1.8VGS_+3VGS RV458 N17S@
0_0805_5% +1.8VGS_+3VGS_AON
PEX_RX6 PEX_RX6#
AG21 AG22
2
2
0_0805_5%
+1.8VGS_+3VGS
1
AG12 AG13
AG24 AG25
2
1
2
@
AD14 AC14
2
1
RV9 10K_0201_5% @
VGS(Max) : 1.5 V
1
PEX_RX4 PEX_RX4#
2
1
0_0805_5%
(To SOC)
1
S
CLKREQ_PEG#0
D
RV10
PEX_TX4 PEX_TX4#
AF10 AE10
2
1
1
RV6
DGPU_PWROK
PEX_RX3 PEX_RX3#
AB13 AC13
2
1
RV447 N16S@
CV28 N16S@ 4.7U_0402_6.3V6M
[25,26,50]
AG9 AG10
2
1
1
CV27 N16S@ 1U_0402_6.3V6K
RV5 10K_0201_5% DIS@
PEX_TX3 PEX_TX3#
2
1
CV26 N16S@ 0.1U_0201_10V6K
1
+1.8VGS_+3VGS
[24]
AC12 AB12
2
1
1.0V
CV25 DIS@ 4.7U_0402_6.3V6M
+1.8VGS_+3VGS_AON
PEX_RX2 PEX_RX2#
1
+1.0VS_DGPU
Place near BGA
CV24 DIS@ 4.7U_0402_6.3V6M
Reset Control
PEX_TX2 PEX_TX2#
AE9 AF9
2
A
Place under GPU
CV23 DIS@ 0.1U_0201_10V6K
B
AD11 AC11
2
CV10 DIS@ 22U_0603_6.3V6M
2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K
PEX_RX1 PEX_RX1#
2
1
CV20 DIS@ 10U_0402_6.3V6M
PCIE_CRX_DTX_P8 PCIE_CRX_DTX_N8
CV9 DIS@ 1 CV11 DIS@ 1
PCIE_CTX_C_DRX_P7 PCIE_CTX_C_DRX_N7
PEX_TX1 PEX_TX1#
AF7 AE7
AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27
2
1
CV19 N17S@ 10U_0402_6.3V6M
[12] [12]
PCIE_CRX_DTX_P7 PCIE_CRX_DTX_N7
AB10 AC10
PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ
2
1
CV18 N17S@ 4.7U_0402_6.3V6M
PCIE_CTX_C_DRX_P7 PCIE_CTX_C_DRX_N7
PCIE_CRX_C_DTX_P6 PCIE_CRX_C_DTX_N6
PEX_RX0 PEX_RX0#
2
1
CV17 DIS@ 4.7U_0402_6.3V6M
[12] [12]
2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K
AG6 AG7
2
CV734 N17S@ 1U_0402_6.3V6K
PCIE_CRX_DTX_P7 PCIE_CRX_DTX_N7
DIS@ 1 DIS@ 1
PEX_TX0 PEX_TX0#
1
CV733 N17S@ 1U_0402_6.3V6K
[12] [12]
CV7 CV8
PCIE_CTX_C_DRX_P6 PCIE_CTX_C_DRX_N6
AC9 AB9
CV16 N17S@ 1U_0402_6.3V6K
PCIE_CTX_C_DRX_P6 PCIE_CTX_C_DRX_N6
[12] [12]
PCIE_CTX_C_DRX_P5 PCIE_CTX_C_DRX_N5 PCIE_CRX_DTX_P6 PCIE_CRX_DTX_N6
[12] [12]
PCIE_CRX_C_DTX_P5 PCIE_CRX_C_DTX_N5
1
2
[12] [12]
2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K
NC FOR GF117/GK208/GM108
PCIE_CTX_C_DRX_P5 PCIE_CTX_C_DRX_N5
CV14 DIS@ 1 CV6 DIS@ 1
1
CV13 N17S@ 22U_0603_6.3V6M
[12] [12]
PCIE_CRX_DTX_P5 PCIE_CRX_DTX_N5
PEX_REFCLK PEX_REFCLK#
CV5 N17S@ 10U_0402_6.3V6M
PCIE_CRX_DTX_P5 PCIE_CRX_DTX_N5
PEX_CLKREQ#
AE8 AD8
CV15 DIS@ 1U_0402_6.3V6K
PCIE X4 Bus
CLK_PEG_P0 CLK_PEG_N0
[12] [12]
AC6
+1.0VS_DGPU
1.0V CV4 N17S@ 10U_0402_6.3V6M
A
[10] [10]
PEX_RST#
CV3 N17S@ 4.7U_0402_6.3V6M
PCIE CLK
N17S@
AC7
Place near BGA CV12 DIS@ 4.7U_0402_6.3V6M
CLKREQ_PEG#0_R
PLT_RST_VGA#
2 0_0402_5%
AA22 AB23 AC24 AD25 AE26 AE27
CV2 N17S@ 4.7U_0402_6.3V6M
1
RV1
PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD
CV1 DIS@ 1U_0402_6.3V6K
PLT_RST_VGA_MON#
Place under GPU
PEX_WAKE#
NC FOR GM108
AB6
2
3
4
Titl e Size D ate:
Comp mpa al Electronics, Inc. NV(1/5)-PC PCIIE
Docume cume men nt Numb mbe er
R ev
LA-H101P
Monday, Oc Octtober 22, 2018
5
0.A
S h ee t
21
of
53
2
3
W6
IFPA_IOVDD
Y6
IFPB_IOVDD
Y3 Y4
IFPA_TXD1# IFPA_TXD1
AA2 AA3
IFPA_TXD2# IFPA_TXD2
AA1 AB1
IFPA_TXD3# IFPA_TXD3
AA5 AA4
IFPB_TXC# IFPB_TXC
AB4 AB5
IFPB_TXD4# IFPB_TXD4
AB2 AB3
IFPB_TXD5# IFPB_TXD5
AD2 AD3
IFPB_TXD6# IFPB_TXD6
AD1 AE1
IFPB_TXD7# IFPB_TXD7
B
AE2
DACA_VREF
AF2
DACA_RSET
NC NC
DACA_HSYNC DACA_VSYNC
NC
DACA_RED
AG3
NC
DACA_GREEN
AF4
DACA_BLUE
AF3
TSEN_VREF
NC
NC GM108 GF117
Note: IFPC/D/E/F interface are XVDDs pin for N17S GPU, and connect them to NVVDD power for improving NVVDD power rail routing
AE3 AE4
AD5 AD4
1
RV448 N17S@
1
1
NC FOR GF117/GM108
NC FOR GF117/GK208/GM108
TXC TXC
TXC TXC
TXD0 TXD0
TXD0 TXD0
TXD1 TXD1
TXD1 TXD1
TXD2 TXD2
TXD2 TXD2
J3 J2
IFPE_L3# IFPE_L3
J1 K1
IFPE_L2# IFPE_L2
K3 K2
IFPE_L1# IFPE_L1
M3 M2
IFPE_L0# IFPE_L0
M1 N1
GPIO18
C2
PLLVDD
1
IFPD_PLLVDD
R7
IFPD_PLLVDD
HPD_E
RV457 N17S@
T3 T2
GPIO15
C3
1
Place near BGA
VID_PLLVDD
IFPF_L3# IFPF_L3
J5 J4
TXD3 TXD3
TXD0 TXD0
IFPF_L2# IFPF_L2
K5 K4
TXD4 TXD4
TXD1 TXD1
IFPF_L1# IFPF_L1
L4 L3
IFPF_L0# IFPF_L0
M5 M4
1 2
1 2
1 2
1 2
CV36 DIS@ 0.1U_0201_10V K X5R
DP
Place near balls
2
2
TXC TXC
TXD2 TXD2
RV456 N16S@
1
H4 H3
RV12 DIS@ 10K_0402_1% 2 1
HPD_F
IFPD_L3# IFPD_L3
R5 R4
TXD0 TXD0
IFPD_L2# IFPD_L2
T5 T4
TXD1 TXD1
IFPD_L1# IFPD_L1
U4 U3
TXD2 TXD2
IFPD_L0# IFPD_L0
V4 V3
GPIO17
D4
B
PLLVDD SP_PLLVDD
N6
VID_PLLVDD
NC
GF119/GK208
GF117/GM108
A10
C
XTAL_OUTBUFF
XTALOUTBUFF
XTALSSIN
XTALOUT
XTALIN
C10 XTAL_OUTBUFF
+1.8VGS_+3VGS_AON RV11 @ 10K_0402_1% 1 2 RV13 DIS@ 10K_0402_1% 1 2
B10
N16S-GT-S-A2_BGA595 @
90-OHM DIFF Impedance for XTALIN & XTALOUT. YV1 27MHZ_10PF_XRCGB27M000F2P18R0 SJ10000UI00
1 1 2
GPIO19
TXC TXC
NC
L6 M6
C11
NC FOR GK208 D
P4 P3
X'TAL
UV1M COMMON
0_0805_5%
IFPF_AUX# IFPF_AUX
DP IFPD_AUX# IFPD_AUX
I2CX_SDA I2CX_SCL
2
CV35 DIS@ 0.1U_0201_10V K X5R
DVI-SL/HDMI I2CZ_SDA I2CZ_SCL
NC FOR GF117/GM108
TXD2 TXD2
IFPD_IOVDD
9/14 XTAL_PLL
+1.0VS_DGPU
TXD5 TXD5
R1 T1
IFPC_L0# IFPC_L0
GF117
R6
0_0805_5%
GF119/GK208
IFPF
2
NC FOR GK208
DVI-DL
R3 R2
IFPC_L1# IFPC_L1
N16S-GT-S-A2_BGA595 @
CV34 N16S@ 10U_0402_6.3V6M
IFPF_IOVDD
IFPC_L2# IFPC_L2
TXD1 TXD1
GF119/GK208
T7
DP IFPE_AUX# IFPE_AUX
CV33 N16S@ 22U_0603_6.3V6M
J6
1
CV31 DIS@ 0.1U_0201_10V K X5R
I2CY_SDA I2CY_SCL
CV32 N16S@ 22U_0603_6.3V6M
IFPE_IOVDD
TXD0 TXD0
A
IFPD_RSET
GPU_PLLVDD
2 HCB1005KF-300T25_2P
CV30 N16S@ 22U_0603_6.3V6M
DVI-SL/HDMI
NC FOR GF117
H6
N3 N2
IFPD
IFPD N16S@
2
I2CY_SDA I2CY_SCL
HPD_E
IFPC_L3# IFPC_L3
NC
2
GF119/GK208
IFPE
TXC TXC
DVI/HDMI
IFPE/F
C
N5 N4
GF117
+1.0VS_DGPU
IFPEF_RSET
IFPC_AUX# IFPC_AUX
IFPC_IOVDD
U6
+1.8VGS_+3VGS
DVI-DL
DP
I2CW_SDA I2CW_SCL
6/14 IFPD
7/14 IFPEF
K6
DVI/HDMI
0_0805_5%
UV1J COMMON
IFPEF_PLLVDD
IFPC_PLLVDD IFPC_PLLVDD
N16S-GT-S-A2_BGA595 @
Place near balls
IFPEF_PLLVDD
M7 N7
GF119/GK208
UV1I COMMON
LV1
K7
IFPC_RSET
P6
N16S-GT-S-A2_BGA595 @
J7
IFPC
T6
GK208
B3
GPIO14
NC
5/14 IFPC
B7 A7
N16S-GT-S-A2_BGA595 @
GF117
IFPAB
I2CA_SCL I2CA_SDA
2
IFPAB_PLLVDD
NC FOR GF117/GM108
W7
IFPAB_PLLVDD
NC FOR GF117/GM108
V7
IFPA_TXD0# IFPA_TXD0
NC NC
1 DIS@
CV37 DIS@ 18P_0402_50V8J
NC NC 2
3
RV14 DIS@ 1.5K_0402_1%
1
A
AC4 AC3
NC
DACA_VDD
GM108/GK208
NC FOR GF117/GM108
IFPAB_RSET
GF117
NC FOR GF117/GM108
IFPA_TXC# IFPA_TXC
AA6
GF117/GM108
NC FOR GF117/GM108
W5
4/14 IFPAB
IFPC
UV1H COMMON
3/14 DACA
IFPA/B
5
DAC_A
UV1K COMMON UV1G COMMON
4
NC FOR GF117/GM108
1
3
1
4 2
CV38 DIS@ 18P_0402_50V8J D
F7
NC FOR GF117
N16S-GT-S-A2_BGA595 @
Security Classification Issued Date
2017/10/27
Com pal Secre cret Data Deci cip phered red Date Date
2019/04/09
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1
2
3
4
Titl e Size
Comp mpa al Electronics, Inc. NV(2/5)-IFP_ P_A ABCDEF_DAC_XTA TAL L
Docume cume men nt Numb mbe er
R ev 0.A
LA-H101P D ate:
Monday, Oc Octtober 22, 2018
5
S h ee t
22
of
53
1
2
3
Place under GPU B26 C25 E23 E26 F14 F21 G13 G14 G15 G16 G18 G19 G20 G21 L22 L24 L26 M21 N21 R21 T21 V21 W21
2
CV725 N17S@ 10U_0402_6.3V6M
1
UV1F COMMON
12/14 FBVDDQ
CV44 0.1U_0201_10V6K
2
2
CV726 N17S@ 10U_0402_6.3V6M
1
1
N16S@
2
N16S@
DIS@
2
1
CV42 0.1U_0201_10V6K
1
CV41 1U_0402_6.3V6K
2
DIS@
2
1
CV40 1U_0402_6.3V6K
2
1
CV39 N16S@ 4.7U_0402_6.3V6M
1
CV43 N16S@ 4.7U_0402_6.3V6M
2
N17S@
2
1
CV720 1U_0402_6.3V6K
1
CV719 1U_0402_6.3V6K
2
N17S@
2
1
N17S@ CV722 1U_0402_6.3V6K
N17S@
2
1
CV721 1U_0402_6.3V6K
1
N17S@ CV724 1U_0402_6.3V6K
N17S@
2
CV723 1U_0402_6.3V6K
1
GPU_Decoupling CAPs @ Power Page
FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ
+VGA_CORE
DIS@
2
1 2
CV46 DIS@ 10U_0402_6.3V6M
1
CV45 22U_0603_6.3V6M
N17S@
2
CV727 22U_0603_6.3V6M
N17S@
CV728 22U_0603_6.3V6M
2
1
H24 H26 J21 K21
FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON
FBVDDQ FBVDDQ FBVDDQ FBVDDQ
B
Place near GPU CIZ00 22uF x1 change to 10uF x2
+1.35VS_VRAM
Near
Ball
FB_CAL_PD_VDDQ
D22
RV15
1 DIS@
2 40.2_0402_1%
FB_CAL_PU_GND
C24
RV16
2 DIS@
1 40.2_0402_1%
FB_CALTERM_GND
B25
RV17
2 DIS@
1 60.4_0402_1%
A2 AB17 AB20 AB24 AC2 AC22 AC26 AC5 AC8 AD12 AD13 A26 AD15 AD16 AD18 AD19 AD21 AD22 AE11 AE14 AE17 AE20 AB11 AF1 AF11 AF14 AF17 AF20 AF23 AF5 AF8 AG2 AG26 AB14 B1 B11 B14 B17 B20 B23 B27 B5 B8 E11 E14 E17 E2 E20 E22 E25 E5 E8 H2 H23 H25 H5 K11 K13 K15 K17 L10 L12 L14 L16 L18 L2 L23 L25 L5 M11
UV1E COMMON
Voltage by GPU SKU
GF117 GF119 GK208
1
5
UV1D COMMON
+1.35VS_VRAM
A
4
K10 K12 K14 K16 K18 L11 L13 L15 L17 M10 M12 M14 M16 M18 N11 N13 N15 N17 P10 P12 P14 P16 P18 R11 R13 R15 R17 T10 T12 T14 T16 T18 U11 U13 U15 U17 V10 V12 V14 V16 V18
11/14 NVVDD
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
N16S-GT-S-A2_BGA595 @
N16S-GT-S-A2_BGA595 @
AA7 AB7
B
1
3V3AUX_NC FERMI_RSVD1_NC FERMI_RSVD2_NC
C
2
Near GPU
1 2
1 2
DIS@
V5 V6
GND GND
A
1 2
CV50 DIS@ 4.7U_0402_6.3V6M
F11
GPU
DIS@
2
GM108
3V3_AON 3V3_AON
GPU
DIS@
2
1
+1.8VGS_+3VGS_AON
Under
GPU
Near GPU
CONFIGURABLE
1 2
DIS@
2
1 2
CV53 DIS@ 4.7U_0402_6.3V6M
1
CV52 1U_0402_6.3V6K
XPWR_V1 XPWR_V2
2
DIS@
V1 V2
1
N17S@
XPWR_G1 XPWR_G2 XPWR_G3 XPWR_G4 XPWR_G5 XPWR_G6 XPWR_G7
CV51 0.1U_0201_10V6K
POWER CHANNELS * nc on substrate
G1 G2 G3 G4 G5 G6 G7
CV740 0.1U_0201_10V6K
CV394 N17S@ 0.1U_0201_10V6K
2
1
CV395 N17S@ 4.7U_0402_6.3V6M
1
CV396 N17S@ 22U_0603_6.3V6M
1 2 LV10 N17S@ HCB1005KF-300T25_2P
Under F11
Under
CV49 1U_0402_6.3V6K
Near GPU
G8 G9 G10 G12
CV48 0.1U_0201_10V6K
PLLVDD
VDD33 VDD33 VDD33 VDD33
CV47 0.1U_0201_10V6K
+1.8VGS_+3VGS
NC NC
M13 M15 M17 N10 N12 N14 N16 N18 P11 P13 P15 P17 P2 P23 P26 P5 R10 R12 R14 R16 R18 T11 T13 T15 T17 U10 U12 U14 U16 U18 U2 U23 U26 U5 V11 V13 V15 V17 Y2 Y23 Y26 Y5
+1.8VGS_+3VGS
14/14 XVDD/VDD33
AD10 AD7
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
N16S-GT-S-A2_BGA595 @
UV1C COMMON
C
13/14 GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
** XPWR pins are configurable. These pins are not connected on the substrate.
W1 W2 W3 W4
D
XPWR_W1 XPWR_W2 XPWR_W3 XPWR_W4
Therefore, XPWR pins can be assigned as needed,
D
to improve Top layer routing, power delivery.
N16S-GT-S-A2_BGA595 @
Security Classification Issued Date
2017/10/27
Com pal Secre cret Data Deci cip phered red Date Date
2019/04/09
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1
2
3
4
Titl e Size
Comp mpa al Electronics, Inc. NV(3/5)-PO POW WER
Docume cume men nt Numb mbe er
R ev
LA-H101P D ate:
Monday, Oc Octtober 22, 2018
5
0.A
S h ee t
23
of
53
1
2
3
4
5
+1.8VGS_+3VGS_AON UV1N COMMON 8/14 MISC1
T231 T232 T242 T243
TP@ TP@ TP@ TP@
GPU_JTAG_TCK GPU_JTAG_TMS GPU_JTAG_TDI GPU_JTAG_TDO GPU_JTAG_TRST#
GPIO
+1.8VGS_+3VGS_AON
I2CS_SCL I2CS_SDA
D9 D8
I2CC_SCL I2CC_SDA
A9 B9
I2CB_SCL I2CB_SDA
C9 C8
I2CS_SCL I2CS_SDA
1 DIS@ 1 DIS@
RV19 RV21
2 2.2K_0402_5% 2 2.2K_0402_5%
PLT_RST_VGA_HOLD# RV18 DGPU_MAIN_EN RV20 PSI RV22 VGA_AC_DET RV23
I2CS SMBUS: 0x96 and 0x9E(Default)
GPU_EVENT#_D
GF117
E12
THERMDN
F12
THERMDP
AE5 AD6 AE6 AF6 AG4
JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST#
NC NC
GPIO8_OVERT#
GPIO9_ALERT# GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13
GK208
GM108 OVERT
A
GM108 GPIO16 GPIO20 GPIO21
GK208
GF117
GPIO16 GPIO20 GPIO8
GPIO8
NC
C6 B2 D6 C7 F9 A3 A4 B6 A6 F8 C5 E7 D7 B4
GPU_VID0 GPIO0_GC6_FB_EN GPU_EVENT#_D
DV1
RV29 1 DIS@ 2
GPU_VID0 [50] GC6_FB_EN [11,25] GPU_EVENT# [9]
2 0_0402_5% 1 RB751V-40_SOD323-2
DGPU_MAIN_EN
DGPU_MAIN_EN PSI GPIO8_OVERT# GPIO9_ALERT# MEM_VREF
PSI
2
DV2 DIS@
1 RB751V-40_SOD323-2
GPU_JTAG_TRST#
To DGPU VR
RV26
1 GC6@
RV27
1 DIS@
GPIO16 GPIO20 GPIO21
D5 E6 C4
NC
E9
RV2466 1
N16S@
2 10K_0201_5% DIS@
RV30
1
2 10K_0201_5% DIS@
[50]
2 0_0402_5%
PLT_RST_VGA_MON#
A
[21]
PLT_RST_VGA_HOLD# RV2467 1
@
2 100K_0201_5%
1
GPU_PROHOT# [33,42] MEM_VREF [27]
VGA_AC_DET
PLT_RST_VGA_HOLD#
2 10K_0201_5%
RV28
GPU_BUFRST
NC
2 10K_0201_5% DIS@ 2 10K_0201_5% DIS@ 2 10K_0201_5% DIS@ 2 10K_0201_5% DIS@
[26]
GF119
NC NC NC
1 1 1 1
[21]
[21]
GPU_TESTMODE
RV36 1
RV37 1 DIS@
2 10K_0201_5%
MEM_VREF
RV38 1 DIS@
2 100K_0201_5%
PLT_RST_VGA_MON#
RV39 1
2 10K_0201_5%
GC6_FB_EN
RV40 1 GC6@
2 0_0402_5%
N16S-GT-S-A2_BGA595 @
2 10K_0201_5%
@
@
2 10K_0201_5%
+1.8VGS_+3VGS_AON UV1L COMMON
Internal
Thermal
Sensor Link to PCH SML1
G
2
10/14 MISC2
PU @ PCH SIDE VMON_IN0_NC VMON_IN1_NC
ROM_CS#
STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
STRAP5
C1
STRAP5_NC
STRAPREF0
F6
MULTISTRAP_REF0_GND
1
[8,33,35]
EC_SMB_DA2
[8,33,35]
S TR PJT138KA 2N SOT363-6 DIS@
G
VGS(Max) : 0.8~1.1 V
1
GM108 NC
MULTISTRAP_REF2_GND
NC
D11
PGOOD
D10
GPU_BUFRST
4
3
QV147B S TR PJT138KA 2N SOT363-6 DIS@
GF119
GM108
2
MULTISTRAP_REF1_GND
GF117 GK208
BUFRST#
D
GF117 GK208
NC
S
F4 RV58 40.2K_0402_1% F5 N16S@
EC_SMB_CK2
QV147A
NC FOR GM108
I2CS_SDA +1.8VGS_+3VGS_AON RV49 0_0402_5% 1 2 @
6
D
D1 D2 E4 E3 D3
I2CS_SCL
ROM_SI ROM_SO ROM_SCLK
S
STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
D12 B12 A12 C12
ROM_SI ROM_SO ROM_SCLK
5
E 10 F10
N16S-GT-S-A2_BGA595 @
+3VS B
2
B
@ 10K_0201_5% RV60
10/13 - Strap Pin Modify for MX110/130 (Pop RV81, Un-Pop RV64)
RV474 0_0402_5%
1
1
1
1
1 2 1 2
2 1 2
2 1 2
2 1
1 2
1 2
2
1 1 2
1
1 2
2 1
1 2
2
@
RV383 4.99K_0402_1%
RV390 4.99K_0402_1%
@
N16S@
@
RV384 49.9K_0402_1%
@
RV388 4.99K_0402_1%
RV387 4.99K_0402_1%
@
@
RV51 4.99K_0402_1%
@
RV382 4.99K_0402_1%
@
RV385 45.3K_0402_1%
RV443 100K_0402_5%
N16S@
RV381 4.99K_0402_1%
@
RV64 4.99K_0402_1%
@
RV65 4.99K_0402_1%
@
@
RV2470 10K_0402_1%
@
STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5
RV389 45.3K_0402_1%
@
RV2471 4.99K_0402_1%
RV2468 4.99K_0402_1%
N16S@
ROM_SI ROM_SO ROM_SCLK
RV2469 14.7K_0402_1%
@
N17S@ RV444 100K_0402_5%
1
N16S@
NV Suggest
STRAP0 : PU 49.9K (50K) STRAP[1:5] : Reserved
+1.8VGS_+3VGS_AON
2
2 RV473 0_0402_5%
STRAP
+1.8VGS_+3VGS_AON
+1.8VGS_+3VGS
1
[10,33]
2
AC_PRESENT
2 0_0402_5%
2
1
AC_PRESENT
1
@
1
2
RV61 1
STRAP
2
VGA_AC_DET
DV3 @ RB751V-40_SOD323-2
N16S VRAM Res.
N17S-G0/G2 VRAM Strap
RAM_CFG
RV388 N17_M2G@ 100K_0402_5%
0xA(LMH)H2G
RV388 N17_H2G@ 100K_0402_5%
STRAP0
STRAP1
STRAP2
0x9(LML) M2G
RV51 N17_M2G@ 100K_0402_5% RV390 N17_M2G@
NOTE
N17S Strap
RV383 N17_M2G@
ROM_SI
100K_0402_5%
100K_0402_5%
C
RV51 N17_H2G@ 100K_0402_5% RV390 N17_H2G@ 100K_0402_5%
RV384 N17_H2G@ 100K_0402_5%
Strap
RV2469 N17S@ S RES 1/16W 100K +-5% 0402
ROM_SO
ROM_SCLK
RV2468 N17S@ S RES 1/16W 100K +-5% 0402
RV2471 N17S@ S RES 1/16W 100K +-5% 0402 RV381 N17S@
STRAP3 RV387 N17S@ S RES 1/16W 100K +-5% 0402
STRAP4
STRAP5
RV385 N17S@ S RES 1/16W 100K +-5% 0402
RV443 N17S@ S RES 1/16W 100K +-5% 0402 C
S RES 1/16W 100K +-5% 0402
N17S-G1 VRAM Strap
RAM_CFG 0x00(LLL)
STRAP2
STRAP1
STRAP0
S2G
RV388 @
RV390 @
RV383 @
M2G
RV382 @
RV390 @
RV383 @
H2G
RV382 @
RV390 @
RV384 @
0x01(LLH) 0x02(LHL) D
D
0x03(LHH) 0x04(HLL) 0x05(HLH) 0x06(HHL) 0x07(HHH) 0x08(LLM)
Compal Secret Data
Security Class siification Is ssu sued Date
2017/10/27
Deciphered Date
2019/04/09
T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONF IDENT IAL AND T RADE SECRET INF ORMAT ION. T HIS SHEET MAY NOT BE T RANSF ERED F ROM T HE CUST ODY OF T HE COMPET ENT DIVISION OF R&D DEPART MENT EXCEPT AS AUT HORIZED BY COMPAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INF ORMAT ION IT CONTAINS MAY BE USED BY OR DISCLOSED T O ANY T HIRD PART Y WIT HOUT PRIOR WRIT T EN CONSENT OF COMPAL ELECT RONICS, INC. 1
2
3
4
C o m p a l E l e c t r o ni c s , I nc .
Ti t le Size D a te :
N V ( 4 / 5 ) - G P I O / St r a p Number LA-H101P
Docum cument
Monday, October 22, 2018 5
S he e t
Rev
0.A 24
of
53
1
2
3
4
5
For GC6 +1.8VGS_+3VGS_AON
[27]
FB_A_D[32..63]
B
[27]
FB_A_DBI[3..0]
[27]
FB_A_DBI[7..4]
[27]
FB_A_EDC[3..0]
[27]
FB_A_EDC[7..4]
C
E18 F18 E16 F17 D20 D21 F20 E21 E15 D15 F15 F13 C13 B13 E13 D13 B15 C16 A13 A15 B18 A18 A19 C19 B24 C23 A25 A24 A21 B21 C20 C21 R22 R24 T22 R23 N25 N26 N23 N24 V23 V22 T23 U22 Y24 AA24 Y22 AA23 AD27 AB25 AD26 AC25 AA27 AA26 W26 Y25 R26 T25 N27 R27 V26 V27 W27 W25
FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63
FB_A_DBI0 FB_A_DBI1 FB_A_DBI2 FB_A_DBI3 FB_A_DBI4 FB_A_DBI5 FB_A_DBI6 FB_A_DBI7
D19 D14 C17 C22 P24 W24 AA25 U25
FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7
FB_A_EDC0 FB_A_EDC1 FB_A_EDC2 FB_A_EDC3 FB_A_EDC4 FB_A_EDC5 FB_A_EDC6 FB_A_EDC7
E19 C15 B16 B22 R25 W23 AB26 T26
FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7
F19 C14 A16 A22 P25 W22 AB27 T27
FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7
NC
FB_CLAMP
F3
RV2456 1
2 1
DGPU_PWROK
A B
UV20 @ 74AUP1G32GW_TSSOP5 SA000054300 4 Y
1.35V_PWR_EN
[51]
GC6_FB_EN DGPU_PWROK
2
A
DV6 GC6@ 1.35V_PWR_EN
1
3
BAV70W_SOT323-3
RV2462 16.5K_0402_5% GC6@ 2
RV68 1
Stuff
2 0_0402_5% NOGC6@
RV201 if not support GC6
From DG-07158-001_v05_secured(NVDIA Spec) FB_A_CMD[0..31]
FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31
FB_A_CMD0 FB_A_CMD1 FB_A_CMD2 FB_A_CMD3 FB_A_CMD4 FB_A_CMD5 FB_A_CMD6 FB_A_CMD7 FB_A_CMD8 FB_A_CMD9 FB_A_CMD10 FB_A_CMD11 FB_A_CMD12 FB_A_CMD13 FB_A_CMD14 FB_A_CMD15 FB_A_CMD16 FB_A_CMD17 FB_A_CMD18 FB_A_CMD19 FB_A_CMD20 FB_A_CMD21 FB_A_CMD22 FB_A_CMD23 FB_A_CMD24 FB_A_CMD25 FB_A_CMD26 FB_A_CMD27 FB_A_CMD28 FB_A_CMD29 FB_A_CMD30 FB_A_CMD31
C27 C26 E24 F24 D27 D26 F25 F26 F23 G22 G23 G24 F27 G25 G27 G26 M24 M23 K24 K23 M27 M26 M25 K26 K22 J23 J25 J24 K27 K25 J27 J26
B
FBA_RST_L FBA_RST_H
FB_A_CMD13 FB_A_CMD29
RV69 RV70
1 DIS@ 1 DIS@
2 10K_0201_1% 2 10K_0201_1%
RV71 RV72
1 DIS@ 1 DIS@
2 10K_0201_1% 2 10K_0201_1%
GDDR5 design
+1.35VS_VRAM
NC FBA_DEBUG0 FBA_DEBUG1
FBA_CMD32
B19
FBA_CMD34 FBA_CMD35
F22 J22
RV73 1 RV74 1
FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1#
D24 D25 N22 M22
FB_A_CLK0 FB_A_CLK#0 FB_A_CLK1 FB_A_CLK#1
FBA_WCK01 FBA_WCK01# FBA_WCK23 FBA_WCK23# FBA_WCK45 FBA_WCK45# FBA_WCK67 FBA_WCK67#
D18 C18 D17 D16 T24 U24 V24 V25
FB_A_WCK0 FB_A_WCK#0 FB_A_WCK1 FB_A_WCK#1 FB_A_WCK2 FB_A_WCK#2 FB_A_WCK3 FB_A_WCK#3
FB_PLLAVDD
F16
FB_PLLAVDD
P22
FB_DLLAVDD
H22
1.35V 2 2
@ @
60.4_0402_1% 60.4_0402_1%
FB_A_CLK0 FB_A_CLK#0 FB_A_CLK1 FB_A_CLK#1
FB_A_WCK0 FB_A_WCK#0 FB_A_WCK1 FB_A_WCK#1 FB_A_WCK2 FB_A_WCK#2 FB_A_WCK3 FB_A_WCK#3
PLLAVDD
Close to P22
1 2
Close to H22
2
1
DIS@
+1.0VS_DGPU RV2464 N16S@ 2 HCB10015KF-300T252_2P
LV3 SM01000NV00
0_0805_5%
1 +1.8VGS_+3VGS
2 1
RV2465 N17S@
2
0_0805_5%
Near GPU
CV794 N17S@ 0.1U_0201_10V K X5R
CV793 N17S@ 0.1U_0201_10V K X5R
1
CV58 DIS@ 22U_0603_6.3V6M
1
CV57 DIS@ 0.1U_0201_10V K X5R
2
2
1.0V
Close to F16
CV56 DIS@ 0.1U_0201_10V K X5R
CV55 DIS@ 0.1U_0201_10V K X5R
1
FB_VREF_PROBE
C
[27] [27] [27] [27]
[27] [27] [27] [27] [27] [27] [27] [27]
PLLAVDD
For VRAM DEBUG using
D
FBA_CKE_L FBA_CKE_H
FB_A_CMD14 FB_A_CMD30
FBVDDQ_GPU
GF117
N16S-GT-S-A2_BGA595 @
[27]
+1.35VS_VRAM
GF117/GF119 GK208
FB_PLLAVDD
D23
2 GC6_FB_EN
[21,26,50]
NC
T2402 @
2 10K_0402_5% [11,24]
GF119
FB_VREF
N17S@
GF119
1
2/14 FBA
FB_A_D0 FB_A_D1 FB_A_D2 FB_A_D3 FB_A_D4 FB_A_D5 FB_A_D6 FB_A_D7 FB_A_D8 FB_A_D9 FB_A_D10 FB_A_D11 FB_A_D12 FB_A_D13 FB_A_D14 FB_A_D15 FB_A_D16 FB_A_D17 FB_A_D18 FB_A_D19 FB_A_D20 FB_A_D21 FB_A_D22 FB_A_D23 FB_A_D24 FB_A_D25 FB_A_D26 FB_A_D27 FB_A_D28 FB_A_D29 FB_A_D30 FB_A_D31 FB_A_D32 FB_A_D33 FB_A_D34 FB_A_D35 FB_A_D36 FB_A_D37 FB_A_D38 FB_A_D39 FB_A_D40 FB_A_D41 FB_A_D42 FB_A_D43 FB_A_D44 FB_A_D45 FB_A_D46 FB_A_D47 FB_A_D48 FB_A_D49 FB_A_D50 FB_A_D51 FB_A_D52 FB_A_D53 FB_A_D54 FB_A_D55 FB_A_D56 FB_A_D57 FB_A_D58 FB_A_D59 FB_A_D60 FB_A_D61 FB_A_D62 FB_A_D63
Normal:1.8V GC6:1.3V SA000099200 (Main) : VIH(min) = 0.8V SA00008I400 (2nd) : VIH(min) = 0.8V
1.8V OR GATE 5
FB_A_D[0..31]
1
3
[27] A
CV54 @ 0.1U_0201_10V6K
G Vcc
UV1B COMMON
D
2 1
Close to H22 Security Classification Issued Date
2017/10/27
Compal Secre crett Data Deciphered Date
2019/04/09
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1
2
3
4
Tit l e Siz e
Date :
C o m p a l E l ect r o n i cs , I n c. NV(5/5)-MEMORY FBA
Document Number
Monday, October 22, 2018
Rev
LA-H101P 5
Sheet
0.A
25
of
53
5
4
3
2
1
+1.8VS RV66 1
+5VALW
2 N17S@ 0_0603_5%
+1.8VGS_+3VGS QV3 DIS@ ME2301DC-G_SOT23-3
2
+3VS
3
1 2
1
3
2 2
1
1
1
2
2
CV737 DIS@ 0.1U_0201_10V K X5R
2
2
CV736 DIS@ 0.1U_0201_10V K X5R
CV62 @ 1U_0402_6.3V6K
2
S
1
CV61 DIS@ 1U_0402_6.3V6K
G
1
1
DIS@ QV148 BSS138W-7-F_SOT323-3
6
1
D
2
CV60 DIS@ 4.7U_0402_6.3V6M
DGPU_MAIN_EN
2
CV59 DIS@ 0.1U_0201_10V K X5R
[24]
1
DGPU_MAIN_EN#_GATE 1 DIS@ 2 RV77 4.7K_0201_5%
D
RV81 0_0402_5% DGPU_MAIN_EN
RV76 22_0603_1% DIS@
G
DGPU_MAIN_EN# D
1
D
2 N16S@ 0_0402_5%
S
RV67 1
RV75 47K_0402_5% DIS@
+1.8VGS_+3VSGS_S
D
G S
1
+3VS to +3VS_DGPU
2
DGPU_MAIN_EN#
QV6A 2N7002KDW_SOT363-6 DIS@
+5VALW
+1.0VS_DGPU
2
2
G S
DGPU_PWR_EN#
4
5
QV6B 2N7002KDW_SOT363-6 DIS@ +3VALW
+3VS +3VS
UV10 DIS@ NL17SZ08DFT2G_SC70-5
2
5
+3VS
RV108 DIS@ 10K_0402_5%
2
+1.8VGS_+3VGS_AON
3
2 1
4 1
QV152B DIS@ 2N7002KDW_SOT363-6
DGPU_PWROK
DG1
1
DIS@
[51]
+1.35VGS_PGOOD
GPUCORE_EN
QV152A DIS@ 2N7002KDW_SOT363-6
Output 3.3V SA00009WE00 (Main) : VIH(min) = 1.2V
DV4 DIS@ RB751S-40_SOD523-2 1 2 RV105 DIS@ 40.2K_0402_1% 1 2
VGA_CORE_EN
CV197 DIS@ 2 0.1U_0201_10V6K
Output 2.6V SA0000ACG00(Main) : VIH(min) = 1.6V
DV5 DIS@ RB751S-40 SOD-523 1 2
0_0402_5% 2
RV103 DIS@ 56K_0402_1% 1
GPU_ALL_PGOOD
[11]
RV256 @ 100K_0402_5%
2
[50]
1
1.0VS_DGPU_EN
DGPU_PWR_EN
2
1
4
[26,46]
1
B
CV196 DIS@ 2 0.1U_0201_10V6K
1
B
RG2
IN A
OUT Y
2 RB751V-40_SOD323-2 [11,26,33]
+1.35VGS_PGOOD
IN B
3
6
5
S
1
G
2
D
DGPU_MAIN_EN
G
RG82 10K_0201_5% N17S@
2 S
RG1 10K_0201_5% N16S@
1
D
2
1.8VSDGPU_MAIN
DGPU_PWROK
C
1
3
3 D
QV5A 2N7002KDW_SOT363-6 DIS@
S
S
RV106 DIS@ 100K_0402_5%
[21,25,50]
2
1
6 1
G
VCC
2
5
1.0VS_DGPU_EN
1
2
2
CV66 @ 1U_0402_6.3V6K
1
DIS@ QV149 BSS138W-7-F_SOT323-3
[26,46]
QV5B 2N7002KDW_SOT363-6 DIS@
GND
G
D
2
G
D
1
S
2
4
1
D
3
2
1 CV738 DIS@ 0.1U_0201_10V K X5R
1
1
CV739 N17S@ 0.1U_0201_10V K X5R
DGPU_PWR_EN
2 CV65 DIS@ 1U_0402_6.3V6K
DGPU_PWR_EN
1 CV63 DIS@ 0.1U_0201_10V K X5R
[11,26,33]
1
CV64 DIS@ 4.7U_0402_6.3V6M
RV86 0_0402_5%
1.0VS_DGPU_EN#
1 2
DGPU_PWR_EN#_GATE
RV84 @ 470_0603_5%
2
G
1
1
D
RV85 DIS@ 10K_0201_5% 1 2
DGPU_PWR_EN#
C
3
S
RV83 47K_0402_5% DIS@
2
2
QV7 DIS@ ME2301DC-G_SOT23-3 +1.8VGS_+3VSGS_S
RV79 DIS@ 22_0603_1%
+1.8VGS_+3VGS_AON
RV78 DIS@ 100K_0402_1%
+5VALW
1
+3VS to +3VS_DGPU_AON
A
A
Compal Secret Data
Security Classification Issued Date
2017/10/27
Deciphered Date
2019/04/09
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Tit l e Size
Dat e :
Compal Electronics, Inc. DGPU_DC/DC Interface LA-H101P
Docum ent Num ber
Monday, October 22, 2018 1
Sh e e t
Rev 0.A 26
of
53
5
4
3
2
1
VRAM Memory Partition A MF=0
FB_A_EDC0 FB_A_EDC1 FB_A_EDC2 FB_A_EDC3
D
C2 C13 R13 R2 D2 D13 P13 P2
[25] [25] [25] [25]
FB_A_DBI0 FB_A_DBI1 FB_A_DBI2 FB_A_DBI3
[25] [25]
FB_A_CLK0 FB_A_CLK#0
FB_A_CLK0 FB_A_CLK#0 FB_A_CMD14
J12 J11 J3
FB_A_CMD2 FB_A_CMD4 FB_A_CMD3 FB_A_CMD1
H11 K10 K11 H10
FB_A_CMD6 FB_A_CMD11 FB_A_CMD10 FB_A_CMD7 FB_A_CMD9
C
[25]
FB_A_CMD[0..15]
[25]
FB_A_CMD[16..31]
[25]
FB_A_D[0..63]
[25]
FB_A_EDC[7..0]
FB_A_CLK0
FB_A_CMD[0..15]
DIS@ DIS@ DIS@
[25] [25]
FB_A_WCK#0 FB_A_WCK0
[25] [25]
FB_A_WCK#1 FB_A_WCK1
2 2 2
K4 H5 H4 K5 J5
1 1K_0402_1% 1 1K_0402_1% 1 121_0402_1%
J4 G3 G12 L3 L12
FB_A_WCK#0 FB_A_WCK0
D5 D4
FB_A_WCK#1 FB_A_WCK1
P5 P4
FB_A_CMD[16..31]
FB_A_EDC[7..0]
RV93 DIS@ 40.2_0402_1% 1 2
FB_A_CMD13
RV94 DIS@ 40.2_0402_1% 1 2 1
Near to UV6
2
+1.35VS_VRAM
FB_A_CLK1
RV95 DIS@ 40.2_0402_1% 1 2
RV96 DIS@ 40.2_0402_1% 1 2 1
Near to UV7
CV68 DIS@ 0.01U_0402_16V7K
2
A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC
A10/A0 A11/A6 A8/A7 A9/A1
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
CAS# WE# RAS# CS#
WCK01# WCK01
WCK23# WCK23
WCK23# WCK23
WCK01# WCK01
RESET#
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14
FB_A_CLK#1
BA2/A4 BA3/A3 BA0/A2 BA1/A5
VREFD VREFD VREFC
H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14
FB_A_CLK#0
BA0/A2 BA1/A5 BA2/A4 BA3/A3
ABI# RAS# CS# CAS# WE#
J2
CV67 DIS@ 0.01U_0402_16V7K
DBI3# DBI2# DBI1# DBI0#
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
MF SEN ZQ
A10 U10 J14
+FBA_VREFC0
FB_A_D[0..63]
DBI0# DBI1# DBI2# DBI3#
MF=0
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
VPP/NC VPP/NC
J1 J10 J13
FB_A_CMD8 FB_A_CMD12 FB_A_CMD0 FB_A_CMD15 FB_A_CMD5
EDC3 EDC2 EDC1 EDC0
MF=1
CK CK# CKE#
A5 U5 RV87 RV89 RV91
MF=0
MF=1
EDC0 EDC1 EDC2 EDC3
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
B
170-BALL
+1.35VS_VRAM 1
SGRAM GDDR5
2
RV97 DIS@ 549_0402_1%
RV98 1 DIS@
+FBA_VREFC0
2 931_0402_1%
MF=0
UV22
MF=0
UV21
@
FB_A_D0 FB_A_D1 FB_A_D2 FB_A_D3 FB_A_D4 FB_A_D5 FB_A_D6 FB_A_D7 FB_A_D8 FB_A_D9 FB_A_D10 FB_A_D11 FB_A_D12 FB_A_D13 FB_A_D14 FB_A_D15 FB_A_D16 FB_A_D17 FB_A_D18 FB_A_D19 FB_A_D20 FB_A_D21 FB_A_D22 FB_A_D23 FB_A_D24 FB_A_D25 FB_A_D26 FB_A_D27 FB_A_D28 FB_A_D29 FB_A_D30 FB_A_D31
A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2
FB_A_EDC4 FB_A_EDC5 FB_A_EDC6 FB_A_EDC7
C2 C13 R13 R2
BYTE0
BYTE1
D2 D13 P13 P2
[25] [25] [25] [25]
FB_A_DBI4 FB_A_DBI5 FB_A_DBI6 FB_A_DBI7
[25] [25]
FB_A_CLK1 FB_A_CLK#1
FB_A_CLK1 FB_A_CLK#1 FB_A_CMD30
J12 J11 J3
FB_A_CMD18 FB_A_CMD20 FB_A_CMD19 FB_A_CMD17
H11 K10 K11 H10
FB_A_CMD22 FB_A_CMD27 FB_A_CMD26 FB_A_CMD23 FB_A_CMD25
K4 H5 H4 K5 J5 A5 U5
RV88 RV90 RV92
+1.35VS_VRAM B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14
DIS@ DIS@ DIS@
[25] [25]
FB_A_WCK#2 FB_A_WCK2
[25] [25]
FB_A_WCK#3 FB_A_WCK3
2 2 2
1 1K_0402_1% 1 1K_0402_1% 1 121_0402_1%
J4 G3 G12 L3 L12
FB_A_WCK#2 FB_A_WCK2
D5 D4
FB_A_WCK#3 FB_A_WCK3
P5 P4
+FBA_VREFC0
A10 U10 J14
FB_A_CMD29
A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14
DBI0# DBI1# DBI2# DBI3#
DBI3# DBI2# DBI1# DBI0#
BA0/A2 BA1/A5 BA2/A4 BA3/A3
BA2/A4 BA3/A3 BA0/A2 BA1/A5
A8/A7 A9/A1 A10/A0 A11/A6 A12/RFU/NC
A10/A0 A11/A6 A8/A7 A9/A1
MF=0
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
ABI# RAS# CS# CAS# WE#
WCK23# WCK23
WCK23# WCK23
WCK01# WCK01
VREFD VREFD VREFC
RESET#
H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14
170-BALL SGRAM GDDR5
@
BYTE4
D
BYTE5
BYTE6
BYTE7
+1.35VS_VRAM
C
A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
FB_A_D32 FB_A_D33 FB_A_D34 FB_A_D35 FB_A_D36 FB_A_D37 FB_A_D38 FB_A_D39 FB_A_D40 FB_A_D41 FB_A_D42 FB_A_D43 FB_A_D44 FB_A_D45 FB_A_D46 FB_A_D47 FB_A_D48 FB_A_D49 FB_A_D50 FB_A_D51 FB_A_D52 FB_A_D53 FB_A_D54 FB_A_D55 FB_A_D56 FB_A_D57 FB_A_D58 FB_A_D59 FB_A_D60 FB_A_D61 FB_A_D62 FB_A_D63
B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
CAS# WE# RAS# CS#
WCK01# WCK01
A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
MF SEN ZQ
J2
+1.35VS_VRAM
EDC3 EDC2 EDC1 EDC0
VPP/NC VPP/NC
J1 J10 J13
FB_A_CMD24 FB_A_CMD28 FB_A_CMD16 FB_A_CMD31 FB_A_CMD21
MF=1
EDC0 EDC1 EDC2 EDC3
CK CK# CKE#
BYTE2
BYTE3
MF=1
B
K4G80325FB-HC03_FBGA170~D
K4G80325FB-HC03_FBGA170~D
Issu ssue ed Date
2018/04/09
Compal Secret Data Deci cip phered Date
4
3
2
2
1 2
1 2
DIS@ CV84 10U_0402_6.3V6M
1
DIS@ CV83 10U_0402_6.3V6M
2
2019/04/09
Da Datt e :
CV106 DIS@ 1U_0201_6.3V6M
1 2
CV105 DIS@ 1U_0201_6.3V6M
1 2
CV104 DIS@ 1U_0201_6.3V6M
1 2
1 2 Titl e Size
CV103 DIS@ 1U_0201_6.3V6M
CV102 DIS@ 1U_0201_6.3V6M
1 2
CV101 DIS@ 1U_0201_6.3V6M
2
1
ball
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
1
DIS@ CV82 10U_0402_6.3V6M
2
ball
DIS@ CV81 10U_0402_6.3V6M
1
DIS@ CV80 10U_0402_6.3V6M
DIS@ CV79 10U_0402_6.3V6M
2
1
Near
1
2
1
CV100 DIS@ 1U_0201_6.3V6M
2
1
CV96 DIS@ 1U_0201_6.3V6M
1 2
CV95 DIS@ 1U_0201_6.3V6M
1 2
CV94 DIS@ 1U_0201_6.3V6M
1 2
1 2
CV93 DIS@ 1U_0201_6.3V6M
CV92 DIS@ 1U_0201_6.3V6M
1 2
CV91 DIS@ 1U_0201_6.3V6M
1
Security Classification
CV97 DIS@ 1U_0201_6.3V6M
+1.35VS_VRAM
ball
2
CV99 DIS@ 1U_0201_6.3V6M
1
Near
CV78 DIS@ 22U_0603_6.3V6M
2
1
2
VRAM
2
1
CV98 DIS@ 1U_0201_6.3V6M
2
CV77 DIS@ 22U_0603_6.3V6M
1
1
2
Near
2
1
DIS@ CV76 10U_0402_6.3V6M
2
DIS@ CV75 10U_0402_6.3V6M
1
DIS@ CV74 10U_0402_6.3V6M
2
+1.35VS_VRAM
ball
DIS@ CV73 10U_0402_6.3V6M
1
DIS@ CV72 10U_0402_6.3V6M
DIS@ CV71 10U_0402_6.3V6M
2
2
Near
1
1
1 2
A
CV87 DIS@ 1U_0201_6.3V6M
+1.35VS_VRAM
1
2
Place near pin J14 of each vram
2
Near
CV90 DIS@ 1U_0201_6.3V6M
1
VRAM
CV89 DIS@ 1U_0201_6.3V6M
2
Near
CV70 DIS@ 22U_0603_6.3V6M
+1.35VS_VRAM
1
2
2
1
CV88 DIS@ 1U_0201_6.3V6M
2
CV69 DIS@ 22U_0603_6.3V6M
2
1
1
QV8 DIS@ L2N7002WT1G_SC-70-3
2
1
1
S
G
CV86 DIS@ 820P_0402_25V7
D
2
CV85 DIS@ 820P_0402_25V7
MEM_VREF
RV99 DIS@ 1.33K_0402_1%
[24]
3
W=16mils
A
Compal Ele Electronics, Inc. N16P_GDDR5 R5__A
Document Number
Re v
LA-H101P
Monday, October 22, 2018 1
0.A Sheet
27
of
53
5
4
3
LCD POWER SWITCH +LCDVDD_CONN
W=60mils
5
U5
IN
1
OUT
4
C4 1U_0201_6.3V6M SE00000UC00
R2
1
D
1
3
OC
+3VS
W=60mils
2 0_0805_5%
2
EM5203AJ-20 SOT23 5P SA00008R900
C3 4.7U_0402_6.3V6M
W=20mils
near JEDP1.32 1
PCH_ENVDD
1
EN
+LCDVDD
2
GND 1
1
CAMERA POWER CIRCUIT
+3VS D
2
2
2
C5 0.1U_0201_10V K X5R
2
R4 100K_0402_5%
DISPLAY OFF
HOT PLUG DETECT
C
C
1
R5
BKOFF#
2 0_0402_5%
DISPOFF#
R6
EDP_HPD
1
2 0_0402_5%
2
1
Through EC
EDP_HPD_R
R8 100K_0402_5%
1
2
R7 100K_0402_5%
eDP CONNECTOR B+
Touch Screen POWER CIRCUIT
+LEDVDD
R9
1
2 0_0805_5% 1
B
2
C7 @ 4.7U_0805_25V6-K
+LCDVDD_CONN
eDP
G-Sensor
A
DMIC
EDP_TXP0 EDP_TXN0
EDP_TXP1 EDP_TXN1
USB20_N4 USB20_P4 TS_I2C_RST# TS_INT# I2C1_SDA_TS I2C1_SCL_TS +3VS_TS TS_DISABLE#
+3VS_CMOS
+3VS EC_SMB_DA4 EC_SMB_CK4 TAB_SW# +3VALW +3VS DMIC_CLK DMIC_DAT
INVPWM
DISPOFF# EDP_HPD_R
C8 C9
1 1
2 0.1U_0201_10V K X5R 2 0.1U_0201_10V K X5R
EDP_AUXN_C EDP_AUXP_C
C10 C11
1 1
2 0.1U_0201_10V K X5R 2 0.1U_0201_10V K X5R
EDP_TXP0_C EDP_TXN0_C
C12 C13
1 1
2 0.1U_0201_10V K X5R 2 0.1U_0201_10V K X5R
EDP_TXP1_C EDP_TXN1_C
R330 1 S340@ 2 0_0201_5% R331 1 S340@ 2 0_0201_5%
Touch Screen
Camera
EDP_AUXN EDP_AUXP
W=60mils
USB20_N4_R USB20_P4_R
R332 1 C340@ 2 0_0201_5% R333 1 C340@ 2 0_0201_5%
W=20mils
USB20_N6 USB20_P6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
JEDP1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
B
+3VS
+3VS_TS
W=20mils
R264 1
W=20mils
2 0_0603_5% 1 2
GND GND GND GND GND
TS@ C230 0.1U_0201_10V K X5R
1 2
C231 @ 10U_0402_6.3V6M SE00000UD00
41 42 43 44 45
A
CVILU_CVS3402M1RM-NH ME@ SP01002FV00
Security Classification Issued Date
2018/09/21
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. eDP / Camera / MIC
Size Document Number Custom Date:
R ev
LA-H101P
Thursday, September 20, 2018 1
Sheet
0.A
28
of
51
5
+3VS
4
Near Pin12
Near Pin40
Near Pin31
+1.2V
2 1
1
1
2 1
2 1
1 EQ
1
2
From CPU
RLS5 4.7K_0402_5%
@
CPU_DP2_P1 CPU_DP2_N1
CPU_DP2_P0 CPU_DP2_N0
CPU_DP2_P3 CPU_DP2_N3
LS@ 1 LS@ 1
2 0.1U_0201_10V6K 2 0.1U_0201_10V6K
HDMI_TX0+_C HDMI_TX0-_C
1 2
CLS11 CLS12
LS@ 1 LS@ 1
2 0.1U_0201_10V6K 2 0.1U_0201_10V6K
HDMI_TX1+_C HDMI_TX1-_C
4 5
CLS7 CLS10
LS@ 1 LS@ 1
2 0.1U_0201_10V6K 2 0.1U_0201_10V6K
HDMI_TX2+_C HDMI_TX2-_C
6 7
CLS15 CLS16
LS@ 1 LS@ 1
2 0.1U_0201_10V6K 2 0.1U_0201_10V6K
HDMI_CLK+_C HDMI_CLK-_C
9 10
2
+3VS RLS6
1
LS@ 2 4.7K_0402_5%
C
RLS7
1
LS@ 2 4.99K_0402_1%
RLS8
1
@
2 4.7K_0402_5%
1
+3VS
14 13 17 EQ I2C_CTL_EN_LS 8 DDCBUF
18 36 23 16
PRE
RLS9 4.7K_0402_5%
IN_D2p IN_D2n IN_D1p IN_D1n
VDD33 VDD33 OUT_D2p OUT_D2n OUT_D1p OUT_D1n OUT_D0p OUT_D0n
IN_D0p IN_D0n
OUT_CKp OUT_CKn
IN_CKp IN_CKn
SDA_SRC SCL_SRC SDA_SNK SCL_SNK
DDCBUF/SDA_CTL DCIN_EN/SCL_CTL EQ/I2C_ADDR0 I2C_CTL_EN REXT PD# CFG / I2C_ADDR1 PRE
HPD_SRC ISET HPD_SNK
GND GND EPAD
11 37 30 29
HDMI_LS_TX_P0 HDMI_LS_TX_N0
27 26
HDMI_LS_TX_P1 HDMI_LS_TX_N1
25 24
HDMI_LS_TX_P2 HDMI_LS_TX_N2
22 21
HDMI_LS_CLKP HDMI_LS_CLKN
39 38 33 32
CPU_DP2_CTRL_DATA CPU_DP2_CTRL_CLK DDC_SDA_HDMI_R DDC_SCL_HDMI_R
3 34 28
CPU_DP2_HPD ISET HDMI_HPD
HDMI_LS_TX_P0 HDMI_LS_TX_N0
HDMI_LS_TX_P1 HDMI_LS_TX_N1
HDMI_LS_TX_P2 HDMI_LS_TX_N2
HDMI_LS_CLKP HDMI_LS_CLKN
2 1
To HDMI
CPU_DP2_CTRL_DATA CPU_DP2_CTRL_CLK
2 0_0201_5% RLS15 1 LS@ 2 0_0201_5% RLS16 1 LS@
CPU_DP2_HPD HDMI_HPD
2 1
From CPU HDMI_CTRL_DAT HDMI_CTRL_CLK
To HDMI
To CPU C
From HDMI
15 35 41
PS8407ATQFN40GTR2A1_TQFN40_5X5
I2C_CTL_EN_LS
1
2
@
VDDTA VDDTX VDDTX VDDRX VDDRX
Near Pin37
CLS9 LS@ 0.1U_0201_10V6K
RLS4 4.7K_0402_5%
@
CLS13 CLS14
Near Pin11
ULS1 LS@
CLS8 LS@ 0.01U_0201_6.3V7K
CPU_DP2_P2 CPU_DP2_N2
+3VS D
Near ULS1
+1.2V_HDMI
2 1 0_0603_5% LS@
19 20 31 12 40
+3VS
1
WRLS2 = 40mils
2
1
2
CLS6 LS@ 0.1U_0201_10V6K
1
2
CLS5 LS@ 0.1U_0201_10V6K
RLS3 4.7K_0402_5%
@
2
CLS4 LS@ 0.1U_0201_10V6K
D
2
CLS3 LS@ 0.1U_0201_10V6K
DDCBUF
CLS2 LS@ 0.01U_0201_6.3V7K
CLS1 LS@ 0.01U_0201_6.3V7K
RLS1 4.7K_0402_5%
LS@
2
+1.2V_HDMI
Near Pin19
1
Near Pin20
3
RLS10 4.7K_0402_5%
2
@
For NoLS only +3VS B
1
For NoLS Near CLS9 ~ CLS16
RLS33 4.7K_0402_5% PRE
1
2
@
B
For NoLS Near ULS1 pin21~30
CPU_DP2_P0 CPU_DP2_N0 CPU_DP2_P1 CPU_DP2_N1
RLS17 1 RLS18 1 RLS19 1 RLS20 1
NOLS@ NOLS@ NOLS@ NOLS@
2 2 2 2
0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5%
HDMI_TX2+_R HDMI_TX2-_R HDMI_TX1+_R HDMI_TX1-_R
RLS21 1 RLS22 1 RLS23 1 RLS24 1
NOLS@ NOLS@ NOLS@ NOLS@
2 2 2 2
0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5%
HDMI_LS_TX_P2 HDMI_LS_TX_N2 HDMI_LS_TX_P1 HDMI_LS_TX_N1
CPU_DP2_P2 CPU_DP2_N2 CPU_DP2_P3 CPU_DP2_N3
RLS25 1 RLS26 1 RLS27 1 RLS28 1
NOLS@ NOLS@ NOLS@ NOLS@
2 2 2 2
0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5%
HDMI_TX0+_R HDMI_TX0-_R HDMI_CLK+_R HDMI_CLK-_R
RLS29 1 RLS30 1 RLS31 1 RLS32 1
NOLS@ NOLS@ NOLS@ NOLS@
2 2 2 2
0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5%
HDMI_LS_TX_P0 HDMI_LS_TX_N0 HDMI_LS_CLKP HDMI_LS_CLKN
RLS34 4.7K_0402_5%
2
@
1
+3VS
RLS35 4.7K_0402_5% A
1
ISET
@
RLS36 4.7K_0402_5%
Security Classification
2
A
2
@
2018/09/21
Issued Date
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title Size Date:
Compal Electronics, Inc. HDMI Level shifter_PS8407A
Document Number
LA-H101P
Thursday, September 20, 2018
Rev 0.A
Sheet
1
29
of
51
5
4
HDMI
3
2
1
EMI EMI
D
CH1
HDMI_LS_CLKP
CH2
HDMI_LS_CLKN
1 1
2 0.1U_0201_10V K X5R NOLS@
HDMI_CLKP
2 0.1U_0201_10V K X5R NOLS@
HDMI_CLKN
RH1 RH3
1 EMI@ 1 EMI@
2 8.2_0402_1%
HDMI_L_CLKP
HDMI_L_CLKP
RH2
1 EMI@
2 150_0402_5%
HDMI_L_CLKN
2 8.2_0402_1%
HDMI_L_CLKN
HDMI_L_TX_P0
RH4
1 EMI@
2 150_0402_5%
HDMI_L_TX_N0
HDMI_L_TX_P1
RH5
1 EMI@
2 150_0402_5%
HDMI_L_TX_N1
HDMI_L_TX_P2
RH6
1 EMI@
2 150_0402_5%
HDMI_L_TX_N2
D
For HDMI
HDMI_LS_TX_P0
HDMI_LS_TX_N0
CH3
1
2 0.1U_0201_10V K X5R NOLS@
HDMI_TX_P0
RH7
1 EMI@
2 8.2_0402_1%
HDMI_L_TX_P0
CH4
1
2 0.1U_0201_10V K X5R NOLS@
HDMI_TX_N0
RH8
1 EMI@
2 8.2_0402_1%
HDMI_L_TX_N0
+5VS
+5V_Display UH1
OUT 1 1
@ CH6 0.1U_0201_10V K X5R
HDMI_LS_TX_P1
HDMI_LS_TX_N1
CH7
1
2 0.1U_0201_10V K X5R NOLS@
HDMI_TX_P1
RH9
1 EMI@
2 8.2_0402_1%
HDMI_L_TX_P1
CH8
1
2 0.1U_0201_10V K X5R NOLS@
HDMI_TX_N1
RH10 1 EMI@
2 8.2_0402_1%
HDMI_L_TX_N1
HDMI_LS_TX_N2
CH9
1
2 0.1U_0201_10V K X5R NOLS@
HDMI_TX_P2
RH11 1 EMI@
2 8.2_0402_1%
HDMI_L_TX_P2
CH10
1
2 0.1U_0201_10V K X5R NOLS@
HDMI_TX_N2
RH12 1 EMI@
2 8.2_0402_1%
HDMI_L_TX_N2
+3VS C
RH13 1M_0402_5% NOLS@
G
NOLS@
LS@ CH8 SD043000080 0_0201_5%
LS@ CH9 SD043000080 0_0201_5%
LS@ CH10 SD043000080 0_0201_5%
QH1A 2N7002KDW_SOT363-6
RH14 RH15 RH17 RH18
1 1 1 1
NOLS@ NOLS@ NOLS@ NOLS@
2 2 2 2
470_0201_5% 470_0201_5% 470_0201_5% 470_0201_5%
RH19 RH20 RH21 RH22
1 1 1 1
NOLS@ NOLS@ NOLS@ NOLS@
2 2 2 2
470_0201_5% 470_0201_5% 470_0201_5% 470_0201_5%
+5V_Display HDMI_CTRL_DAT HDMI_CTRL_CLK
1
LS@ CH7 SD043000080 0_0201_5%
HDMI_HPD
6
RH16 20K_0402_5%
HDMI_L_CLKN
2
LS@ CH4 SD043000080 0_0201_5%
1
CPU_DP2_HPD
HDMI_L_CLKP HDMI_L_TX_N0 HDMI_L_TX_P0 HDMI_L_TX_N1 HDMI_L_TX_P1 HDMI_L_TX_N2 HDMI_L_TX_P2
+3VS D
5
G NOLS@
4
S
B
23 22 21 20
B
1
1 2
HDMI_CTRL_CLK
HDMI_CTRL_CLK
5
6 NOLS@
2
2
1 2
2 CPU_DP2_CTRL_CLK
4
CPU_DP2_CTRL_DATA
HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield GND CK+ GND D0GND D0_shield GND D0+ D1D1_shield D1+ D2D2_shield D2+
2N7002KDW_SOT363-6 QH1B
RH26 2.2K_0402_5%
1
QH2A 2N7002KDW 2N SC88-6 SB00000EO00
RH25 2.2K_0402_5%
JHDMI1
+5V_Display
RH24 2.2K_0402_5%
NOLS@
+3VS
NOLS@ RH23 2.2K_0402_5%
1
+3VS
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
LOTES_AHDM0064-P001A DC232007B00 ME@
3
LS@ CH3 SD043000080 0_0201_5%
Near JHDMI1
D
LS@ CH2 SD043000080 0_0201_5%
S
LS@ CH1 SD043000080 0_0201_5%
S IC AP2330W-7 SC59 3P PWR SW SA00004ZA00
2
HDMI_LS_TX_P2
CH5 0.1U_0201_10V K X5R
2
1
2
HDMI_HPD
2
C
W=40mils 1
GND 2
3
IN
HDMI_CTRL_DAT
3 NOLS@
HDMI_CTRL_DAT
HDMI_CTRL_DAT
DH1 9 10
1
1
HDMI_CTRL_DAT
HDMI_L_TX_N1
DH2 9 10
1
1
HDMI_L_TX_N1
HDMI_L_CLKP
DH3 9 10
1
1
HDMI_L_CLKP
HDMI_CTRL_CLK
8
9
2
2
HDMI_CTRL_CLK
HDMI_L_TX_P1
8
9
2
2
HDMI_L_TX_P1
HDMI_L_CLKN
8
9
2
2
HDMI_L_CLKN
HDMI_HPD
7
7
4
4
HDMI_HPD
HDMI_L_TX_N2
7
7
4
4
HDMI_L_TX_N2
HDMI_L_TX_P0
7
7
4
4
HDMI_L_TX_P0
+5V_Display
6
6
5
5
+5V_Display
HDMI_L_TX_P2
6
6
5
5
HDMI_L_TX_P2
HDMI_L_TX_N0
6
6
5
5
HDMI_L_TX_N0
3
3
3
3
3
3
QH2B 2N7002KDW 2N SC88-6 SB00000EO00
@ESD@
@ESD@
8
@ESD@
8
L05ESDL5V0NA-4 SLP2510P8 ESD
8
L05ESDL5V0NA-4 SLP2510P8 ESD
L05ESDL5V0NA-4 SLP2510P8 ESD
A
A
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA
HDMI_CTRL_CLK
HDMI_CTRL_DAT
1
1
1
1
CH11 10P_0402_50V8J 2 @RF@
CH12 10P_0402_50V8J 2 @RF@
CH13 10P_0402_50V8J 2 @RF@
2
CH14 10P_0402_50V8J @RF@
Security Classification Issued Date
2018/09/21
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc.
Size Document Number Custom
HDMI
R ev
LA-H101P
Date: Thursday, September 20, 2018
1
0.A
Sheet
30
of
51
A
B
C
D
E
NGFF WLAN /BT(Key E) +3VALW
NGFF Wireless LAN / BT (Key E) [PCIE+USB/CNVi]
W=20mils
@
3
W=20mils
1
D
S
1
+3VS_WLAN
422.18mA QW10
1
+3VS_WLAN PJ2301_SOT23-3
2
G
2
2
CW3 0.01U_0402_16V7K CNVi@
Imax : 2.0 A
2 2
2
1 2
Close to KEY E pin2,4
0_0402_5%
1
+3VS_WLAN 5
UW1
IN
OUT GND
4
EN(EN#)
OC#
1
1 @
2
2
CW11 @ 10U_0402_6.3V6M
CW9 1U_0201_6.3V6M CNVi@
2
1
+3VS_WLAN
2 3
RW60 100_0402_1%
G524B2T11U_SOT23-5 SA00007BW00 CNVi@
@
2
4.7U_0402_6.3V6M CNVi@
CW5 0.1U_0201_10V6K CNVi@
CNVi@ CW6 0.01U_0402_16V7K
CNVi_PWR_EN#_R
1
CNVi_PWR_EN#
CW10 0.1U_0201_10V6K
CNVi_PWR_EN#_R
2
Imax : 2.0 A CW61 CNVi@ 1U_0201_6.3V6M
+3VS_WLAN
CW4
CNVi@ RW41
Close to KEY E pin72,74
1
+3VS_WLAN
1
1
CW2 CNVi@ 0.1U_0201_10V6K
+3VALW
I (Max) : 2.0 A(+3VS_WLAN) RDS(Typ) : 70 mohm V drop : 0.14 V
CNVi_PWR_EN#_R
1
CW1 CNVi@ 4.7U_0402_6.3V6M
1
1
2
1
D
3
1
S
2
QW11 2N7002KW_SOT323-3
G
Jefferson Peak:1360mA@peak Thunder_Peak_2:1100mA@peak
current current
@
2
2
+3VS_WLAN
CNVi Module PIN Def i ne
BT CNV_CRX_DTX_N1 CNV_CRX_DTX_P1
USB20_P10 USB20_N10 CNV_CRX_DTX_N1 CNV_CRX_DTX_P1 CNV_CRX_DTX_N0 CNV_CRX_DTX_P0
CNV_CRX_DTX_N0 CNV_CRX_DTX_P0
CLK_CNV_CRX_DTX_N CLK_CNV_CRX_DTX_P
WLAN
1 GND USB_D+ 3 USB_D- 5 7 GND WGR_D1N 9 WGR_D1P 11 GND 13 WGR_D0N 15 WGR_D0P 17 GND 19 WGR_CLKN 21 WGR_CLKP 23
CLK_CNV_CRX_DTX_N CLK_CNV_CRX_DTX_P
Near JWLAN1
PCIE_CTX_DRX_P11 PCIE_CTX_DRX_N11
PCIE_CRX_DTX_P11 PCIE_CRX_DTX_N11
CC82 CC83
CLK_PCIE_P3 CLK_PCIE_N3 CLKREQ_PCIE#3 PCIE_WAKE# CNV_CTX_DRX_N1 CNV_CTX_DRX_N1 CNV_CTX_DRX_P1 CNV_CTX_DRX_P1 CNV_CTX_DRX_N0 CNV_CTX_DRX_N0 CNV_CTX_DRX_P0 CNV_CTX_DRX_P0 CLK_CNV_CTX_DRX_N CLK_CNV_CTX_DRX_N CLK_CNV_CTX_DRX_P CLK_CNV_CTX_DRX_P
3
RWL1 RWL2
GND 25 1 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_P11 PETp0 27 1 2 0.1U_0201_10V6K PCIE_CTX_C_DRX_N11 PETn0 29 GND 31 PERp0 33 PERn0 35 GND 37 REFCLKP039 REFCLKN041 GND 43 CLKREQ_PCIE#3_R 1 2 0_0402_5% CLKREQ0#45 WAKE#_R 1 2 0_0402_5% 47 @ PEWake0# GND 49 WT_D1N 51 WT_D1P 53 GND 55 WT_D0N 57 WT_D0P 59 GND 61 WT_CLKN63 WT_CLKP65 GND 67 GND
69
JWLAN1
GND_1 USB_D+ USB_DGND_7 SDIO_CLK SDIO_CMD SDIO_DAT0 SDIO_DAT1 SDIO_DAT2 SDIO_DAT3 SDIO_WAKE SDIO_RST
3.3VAUX_2 3.3VAUX_4 LED1# PCM_CLK PCM_SYNC PCM_OUT PCM_IN LED2# GND_18 UART_WAKE UART_TX
UART_RX GND_33 UART_RTS PET_RX_P0 UART_CTS PET_RX_N0 CLink_RST GND_39 CLink_DATA PER_TX_P0 CLink_CLK PER_TX_N0 COEX3 GND_45 COEX2 REFCLK_P0 COEX1 REFCLK_N0 SUSCLK(32KHz) GND_51 PERST0# CLKREQ0# W_DISABLE2# PEWAKE0# W_DISABLE1# GND_57 I2C_DAT RSVD/PCIE_RX_P1 I2C_CLK I2C_IRQ RSVD/PCIE_RX_N1 GND_63 RSVD_64 RSVD/PCIE_TX_P1 RSVD_66 RSVD/PCIE_TX_N1 RSVD_68 GND_69 RSVD_70 RSVD_71 3.3VAUX_72 RSVD_73 3.3VAUX_74 GND_75 GND1 GND2
2 +3P3A 4 +3P3A 6 LED#1 8 PCM_CLK CNV_RF_RESET#_R 10 RF_RESET_B 12 PCM_IN CLKREQ_CNV#_R 14 CLKREQ0 16 LED2# 18 GND/LNA_EN 20 UART WAKE# CNV_BRI_CRX_R_DTX 22 BRI_RSP CNV_RGI_CTX_R_DRX 24 RGI_DT CNV_RGI_CRX_R_DTX 26 RGI_RSP CNV_BRI_CTX_R_DRX 28 BRI_DT 30 Clink RESET 32 Clink DATA 34 Clink CLK 36 COEX3 38 COEX_RXD 40 COEX_TXD 42 C_P32K 44 PERST0# 46 W_DISABLE2# 48 W_DISABLE1# 50 A4WP_I2C_DATA 52 A4WP_I2C_CLK 54 A4WP_IRQ# CLKIN_XTAL 56 REFCLK0 58 PERST1# 60 CLKREQ1# 62 PEWake1# 64 +3P3A 66 +3P3A
RW4
1 CNVi@ 2 33_0201_5%
CNV_RF_RESET#
RW6
1 CNVi@ 2 33_0201_5%
CLKREQ_CNV#
2 0_0201_5% RW9 1 @ RW11 1 CNVi@ 2 22_0402_5% RW13 RW14 RW15 RW16
UART0_RX CNV_BRI_CRX_DTX
1 2 0_0201_5% @ 1 CNVi@ 2 33_0402_5% 1 CNVi@ 2 22_0402_5% 1 CNVi@ 2 33_0402_5% EC_TX EC_RX
WLBT_OFF# WL_OFF#
UART0_TX CNV_RGI_CTX_DRX
CNV_RGI_CRX_DTX
CNV_BRI_CTX_DRX
SUSCLK PCI_RST# WLBT_OFF# WL_OFF# 3
CLKIN_XTAL
68 GND
BELLW_80152-3221 SP070013E00 ME@
The connectivity module power supply pin shall be connected directly to thr rail DSW. From 567240_Intel_Wireless_AC_9560_Jefferson_Peak_EPS_Rev1.1
Note: The real behavior of BT_DISABLE are BT_DISABLE=LOW, BT=OFF BT_DISABLE=HIGH, BT=ON
+3VS_WLAN
PCH EDS : M.2 CNV Mode Select
RW58 1
@
2 10K_0402_5%
WLBT_OFF#
GPP_F6/CNV_RGI_DT
RW59 1
@
2 10K_0402_5%
WL_OFF#
0 = Integrated CNVi enable.
RW61 1
@
2 10K_0402_5%
CLKREQ_PCIE#3_R
1 = Integrated CNVi disable. +1.8VALW 4
4
CNV_RGI_CTX_R_DRX
RW156 1 CNVi@ 2 20K_0201_5%
CNV_BRI_CTX_R_DRX
RW157 1
100K_0402_5% 2
@
2 20K_0201_5%
1 RW26 EC_TX
71.5K_0402_1% 1 CNVi@ 2 RW27 CLKREQ_CNV#
Compal Secret Data
Security Classification Issued Date
2018/09/21
Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title Size
Compal Electronics, Inc. NGFF WLAN / BT Document Number
R ev
LA-H101P Date:
Thursday, September 20, 2018 E
Sheet
0.A
31
of
51
5
4
3
2
1
+3VS_SSD
SSD(TYPE M)
1 @
2
+3VS_SSD
+3VS
C21 10U_0402_6.3V6M
2
C20 10U_0402_6.3V6M
2
1
C19
1
0.1U_0201_10V6K
2
C18 0.01U_0402_16V7K
1
1
R10
2 +3VS_SSD
0_0805_5%
D
D
SSD SATA
PCIE_CTX_DRX_N13 PCIE_CTX_DRX_P13
PCIE_CRX_DTX_N14 PCIE_CRX_DTX_P14
PCIE_CTX_DRX_N14 PCIE_CTX_DRX_P14
PCIE_CRX_DTX_N15 PCIE_CRX_DTX_P15
PCIE_CTX_DRX_N15 PCIE_CTX_DRX_P15
SATA_CRX_DTX_P2 SATA_CRX_DTX_N2
SATA_CTX_DRX_N2 SATA_CTX_DRX_P2
CC84 CC85
1 1
2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K
PCIE_CTX_C_DRX_N13 PCIE_CTX_C_DRX_P13
CC86 CC87
1 1
2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K
PCIE_CTX_C_DRX_N14 PCIE_CTX_C_DRX_P14
CC88 CC89
1 1
2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K
PCIE_CTX_C_DRX_N15 PCIE_CTX_C_DRX_P15
CC90 CC91
1 1
2 0.22U_0402_6.3V6K 2 0.22U_0402_6.3V6K
SATA_CTX_C_DRX_N2 SATA_CTX_C_DRX_P2
CLK_PCIE_N1 CLK_PCIE_P1
GND GND PERn3 PERp3 GND PETn3 PETp3 GND PERn2 PERp2 GND PETn2 PETp2 GND PERn1 PERp1 GND PETn1 PETp1 GND PERn0/SATA-B+ PERp0/SATA-BGND PETn0/SATA-APETp0/SATA-A+ GND REFCLKN REFCLKP GND
3P3VAUX 3P3VAUX NC NC DAS/DSS# 3P3VAUX 3P3VAUX 3P3VAUX 3P3VAUX NC NC NC NC NC NC NC NC NC DEVSLP NC NC NC NC NC PERST# CLKREQ# PEWake# NC NC
2 0_0402_5%
NGFF_SSD_PEDET
2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58
R12 10K_0402_5%
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57
@
1
PCIE_CRX_DTX_N13 PCIE_CRX_DTX_P13
1
NGFF_SSD_PEDET#
D
2
G
3
SSD PCIE
R11
JSSD1
DEVSLP2
Q1 S 2N7002KW_SOT323-3 SB000009Q80
NGFF_SSD_PEDET# PCI_RST# CLKREQ_PCIE#1
H : PCIE Interface L : SATA Interface Fellow 543016_SKL_U_Y_PDG_0_9
C
C
NGFF_SSD_PEDET#
59 61 63 65 67
NC PEDET(NC-PCIE/GND-SATA) GND GND GND
SUSCLK(32kHz) 3P3VAUX 3P3VAUX 3P3VAUX GND1 GND2
60 62 64 66 68 69
BELLW_80159-3221 SP070018L00 ME@
SATA HDD SATA HDD Conn.
For Power consumption Measurement +5VS
B
+5VS_HDD
580mA RHD5 1
JHDD1
2 0_0805_5%
SATA_CTX_DRX_P1 SATA_CTX_DRX_N1
SATA_CRX_DTX_N1 SATA_CRX_DTX_P1
1 2
1 1
2 0.01U_0402_16V7K 2 0.01U_0402_16V7K
SATA_CTX_C_DRX_P1 SATA_CTX_C_DRX_N1
CHD13 CHD15
1 1
2 0.01U_0402_16V7K 2 0.01U_0402_16V7K
SATA_CRX_C_DTX_N1 SATA_CRX_C_DTX_P1
1 2 3 4 5 6 7
0.1U_0201_10V6K CHD6
2
10U_0402_6.3V6M CHD5
1
CHD9 CHD11
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+5VS_HDD
B
GND A+ AGND BB+ GND V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12
GND GND
24 23
SDAN_603006-022041 DC01000CE00 ME@
A
A
Security Classification Issued Date
2018/09/21
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. SSD/HDD
Size Document Number Custom Date:
LA-H101P
Thursday, September 20, 2018 1
R ev 0.A
Sheet
32
of
51
A
B
C
D
ALC3287
Speaker
DMIC_CLK
RA7
1
EC_MUTE#
RA8
1
2 BLM15PX221SN1D_2P DMIC_CLK_R
EMI@
2 0_0402_5%
4 5 2
PDB PLUG_IN
48 47
GNDA GNDA GNDA
2
CA7
1
2 2.2U_0402_6.3V6M
38
CA8
1
2 2.2U_0402_6.3V6M
39
CA9
1
2 2.2U_0402_6.3V6M
32
EXT_MIC_SLEEVE RA10 1
2 2.2K_0402_5%
29
EXT_MIC_RING2
2 2.2K_0402_5%
28
RA11 1
GNDA
CA10 1
2
1U_0201_6.3V6M
25 24
GNDA
CA11
1
2 1U_0402_6.3V6K
23
CA14
1
2 2.2U_0402_6.3V6M LDO2
21
CA15
1
2 2.2U_0402_6.3V6M LDO3
19
HP_OUTR
Headphone
NC
PDB JD1 JD2 +5VDDA_CODEC
6
@ESD@
2
1 2
MIC2-CAP
5VSTB AVDD1
MIC2-VREFO-R
CPVDD/AVDD2
MIC2-VREFO-L
DVDD
CPVEE
PVDD1
CBN
PVDD2
CBP
Thermal_Pad
LDO2-CAP
AVSS1
LDO3-CAP
AVSS2
+3.3VS --> +IOVDD_CODEC +3VS
33
2
5
CA6 SPK_R2+_CONN
4
I/O2
VDD
GND
I/O3
I/O1
3
SPK_L2+_CONN
2
1
SPK_L1-_CONN
AZC099-04S.R7G_SOT23-6
Place near Pin20
RA9
1
2 10K_0402_5%
GNDA
40
2
20
+1.8VDD_CODEC
3
+3VDD_CODEC
18
+5VS
+IOVDD_CODEC +5VS_PVDD
41 46 49 37 22
1 2
CA12
RA12 1 1
2
Consumption
CA13
EMI
0_0805_5%
Test
W=40mils W=40mils
2
SM010009U00 SM010009U00 1 BLM15BD121SN1D_2P EMI@ RA14 2 1 BLM15BD121SN1D_2P EMI@ RA13 2 2 47_0402_5% EMI@ RA15 1 2 47_0402_5% EMI@ RA16 1 SD028470A80 SD028470A80
EXT_MIC_SLEEVE EXT_MIC_RING2 HP_OUTL HP_OUTR
RA17 10K_0402_5%
@
@
+3VS
+IOVDD_CODEC 1
2 0_0603_5%
1 CA20 2
CA21 2
1
1
2
2
GNDA GNDA EMI@ EMI@
1 CA28 2
Place near Pin18
1 CA22
JHP1
HGNDA / HGNDB , W=60mils
2
HGNDA HPOUT_L
RA22 1
2 0_0402_5%
3 1
HPOUT_L1
5
Place near Pin3 PLUG_IN HPOUT_R
RA23 1
2 0_0402_5%
HPOUT_R1
BEEP# HDA_SPKR
1 RA27 1 RA29
2 4.7K_0402_5% 2 4.7K_0402_5%
1 CA25
PC_BEEP 2 0.1U_0201_10V K X5R
@ RA30 0_0402_5%
Place near Pin20
6
2
R/L
1
2
3
GND
M/G
7
2
2 0_0402_5%
1
1
CA24
2
4
GND
2
0.1U_0201_10V K X5R
4
1
1
2
3 1 2 0_0402_5%
RA32 1
2 RA28 1
CA29 @ESD@ 100P_0402_50V8J
@ESD@
2 0_0402_5%
5
YUQIU_PJ567-F07M1BE-F SP011609088 ME@
RA24 33K_0402_5%
2 0_0402_5%
RA26 1
DA4 SCA00001A00 AZ5125-02S.R7G_SOT23-3
RA31 1
ESD@
PC Beep
@ESD@
+1.8VDD_CODEC
DA3 SCA00004300 CEST23LC5VB C/A_SOT23-3
+1.8VS --> +1.8VDD_CODEC
G/M L/R
6
4
HGNDB
2 0_0402_5%
3
Combo Jack (Normal Open)
2 0_0402_5%
GNDA
RA25 1
GNDA GNDA EMI@ EMI@
+3VDD_CODEC
RA21 1 1
GNDA
HGNDB HGNDA HPOUT_L HPOUT_R
+3VS --> +3VDD_CODEC
0.1U_0201_10V K X5R
RA20
2.2U_0402_6.3V6M
2 0_0603_5%
Place near Pin40
+1.8VS
ACES_50271-0040N-001 SP02000TS00 ME@
LDO1-CAP
0.1U_0201_10V K X5R
RA19 1
0.1U_0201_10V K X5R
3
DA2
I/O4
GNDA
+5VDDA_CODEC
1
1
GNDA
+5VS
2
+5VS SPK_R1-_CONN
GPIO1/DMIC-CLK
ALC3287-CG_MQFN48_6X6
+5VS --> +5VDDA_CODEC
1
1
GND1 GND2
ESD
GPIO0/DMIC-DATA12
VREF
2
1 2 3 4
ESD protection needs to be placed near connector side +1.8VDD_CODEC
SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
1
1000P_0402_50V7K
HP_OUTL
26
NC
DVDD-IO
wide 40MIL
27
Speaker
2
DMIC_DAT
HPOUT-R
SPK_R2+
1
1 DMIC_DAT
HPOUT-L
NC
SPK_R1-
45
JSPK1
CA19 220P_0402_50V7K
8
NC
44
CA18 220P_0402_50V7K 1 2
12
SPK-OUT-R+
43
5 6
CA17 470P_0402_50V7K
9
SPK-OUT-R-
NC
1000P_0402_50V7K EMI@ CA5
10
SPK-OUT-L-
SDATA-IN
SPK_L1-
1 2 3 4 1000P_0402_50V7K EMI@ CA4
11
SPK_L2+
SPK_L1-_CONN SPK_L2+_CONN SPK_R1-_CONN SPK_R2+_CONN
0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5%
CA16 470P_0402_50V7K
16
42
2 2 2 2
CA2
HDA_SDIN0_R
SPK-OUT-L+
DC_DET/EPAD
35
1 1 1 1
RA5 RA6 RA1 RA3
1000P_0402_50V7K EMI@ CA3
1 RA2 2 33_0402_5%
HDA_SDIN0
LINE2-R
SDATA-OUT
SPK_L1SPK_L2+ SPK_R1SPK_R2+
36
EMI@
BCLK
SPEAK 4 ohm : 40MIL SPEAK 8 ohm : 20MIL
2
13
LINE2-L
EXT_MIC_SLEEVE
2
17
SYNC
EXT_MIC_RING2
31
1
HDA_BIT_CLK_R HDA_SDOUT_R
14
30
1
1 33_0402_5%
MIC2-R/SLEEVE
10K_0402_5% RA18
@EMI@
MIC2-L/RING2
I2C_CLK
2.2U_0402_6.3V6M
1
RA4 2
I2C_DATA
PC_BEEP
0.1U_0201_10V K X5R
@EMI@ 22P_0402_50V8J
CA1
15
34
4.7U_0402_6.3V6M
7 HDA_SYNC_R
PCBEEP
wide 40MIL
EMI
UA1 6
E
GNDA
Place near Pin34
GNDA
Compal Secret Data
Security Classification Issued Date
2018/09/21
Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. HD Audio Codec_ALC3287
Size Document Number Custom
Date:
LA-H101P
Thursday, September 20, 2018 E
Sheet
Rev 0.A
33
of
51
3
4
5
+3VL
+3VL
C35
@EMI@ 2 1 22P_0402_50V8J R22
+3VALW_EC
1
@
2
R19
@EMI@
KB_MUTLI_KEY
KB_MUTLI_KEY
EMI
1 10_0402_1%
SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
CLK_LPC_EC PCI_RST#
2 47K_0402_5% 2 1
C36
PCI_RST# EC_RST#
EC_SCI# PM_CLKRUN#
0.1U_0201_10V K X5R
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15
B
KSO[0..17]
KSO[0..17]
KSI[0..7]
KSI[0..7]
[34] [24,42]
+3VL 1 1
R31 R32
2 2.2K_0402_5% 2 2.2K_0402_5%
EC_SMB_CK1 EC_SMB_DA1
KB_MUTLI_KEY GPU_PROHOT#
EC_SMB_CK1 EC_SMB_DA1
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
@
2
@
1 2
U11
1 2 3 4 5 7 8 10 12 13 37 20 38
55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 77 78 79 80
2
C26 100P_0402_50V8J @
C27 0.1U_0201_10V K X5R
GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC & MISC LPC_AD0
AD
VCIN1_BATT_TEMP/AD0/GPIO38 VCIN1_BATT_DROP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD_BID/AD3/GPIO3B AD4/GPIO42 AD5/GPIO43
DA0/GPIO3C DA Output EN_DFAN1/DA1/GPIO3D KSI0/GPIO30 DA2/GPIO3E KSI1/GPIO31 DA3/GPIO3F KSI2/GPIO32 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B KSI5/GPIO35 PSCLK2/GPIO4C PS2 Interface KSI6/GPIO36 PSDAT2/GPIO4D KSI7/GPIO37 TP_CLK/GPIO4E KSO0/GPIO20 TP_DATA/GPIO4F KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 ENKBL/GPXIOA00 KSO4/GPIO24 WOL_EN/GPXIOA01 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 KSO7/GPIO27 SPI Device Interface KSO8/GPIO28 KSO9/GPIO29 MISO/GPIO5B KSO10/GPIO2A MOSI/GPIO5C SPI Flash ROM SPICLK/GPIO58 KSO11/GPIO2B KSO12/GPIO2C SPICS#/GPIO5A KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 KSO17/GPIO49 GPIO50 BATT_CHG_LED#/GPIO52 CAPS_LED#/GPIO53 GPIO EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 DPWROK_EC/GPIO59
1 1
R39
1
@
2 10K_0201_5% 2 10K_0201_5%
EC_FAN_SPEED1 EC_FAN_SPEED2
2 10K_0201_5%
GPU_PROHOT#
EC_TX EC_RX PCH_PWROK PWR_BATT_LOW# VR_PWRGD
+3VALW
1
R44
@
2 10K_0402_5%
EC_FAN_SPEED1
PBTN_OUT#
PBTN_OUT#
122 123
EC_RSMRST#/GPXIOA03 GPXIOA04 VCIN1_ADP_PROCHOT/GPXIOA05 VCOUT1_PROCHOT#/GPXIOA06 VCOUT0_MAIN_PWR_ON/GPXIOA07 BKOFF#/GPXIOA08 GPIO GPO GPXIOA09 PCH_PWR_EN/GPXIOA10 PWR_VCCST_PG/GPXIOA11
GPI
PBTN_OUT#/GPIO5D PM_SLP_S4#/GPIO5E
VCIN1_AC_IN/GPXIOD01 EC_ON/GPXIOD02 ON/OFF#/GPXIOD03 LID_SW#/GPXIOD04 SUSP#/GPXIOD05 GPXIOD06 PECI/GPXIOD07 V18R/VCC_IO2
GND GND GND GND GND
PBTN_OUT# PM_SLP_S4#
2
C28 1000P_0402_50V7K @
63 64 65 66 75 76
ADP_I CUST_TEMP3 TS_DISABLE# CUST_TEMP2
NOVO#
83 84 85 86 87 88
I2C_2_SCL I2C_2_SDA EC_SMB_CK4 EC_SMB_DA4
VCIN1_BATT_TEMP
C32
1
2
VCIN1_AC_IN
C34
1
2
1
2 10K_0402_5%
1
TAB_SW#
124
R17 R18
1 C340@ 2 1K_0402_5% 1 C340@ 2 1K_0402_5%
I2C_2_SCL I2C_2_SDA
R20 R21
1 C340@ 2 2.7K_0402_5% 1 C340@ 2 2.7K_0402_5%
EC_PCIE_WAKE#
R24
1
@
2 4.7K_0402_5%
KB_MUTLI_KEY
R25
1
@
2 10K_0402_5%
can just only stuff for S340 15" LID_SW# R26
1
TAB_SW#
R27
1
EC_MUTE#
R28
1
EC_SPI_CS0#
R30
1
NO KBL
0
2 100K_0402_5% 2 100K_0402_5% @
2 10K_0402_5%
2
B
100K_0402_5%
Follow ENE suggestion for Auto load
EC_SPI_MISO
EC_SPI_MOSI EC_SPI_CLK EC_SPI_CS0# +3VL
CUST_TEMP1 SENSOR_EC_INT
EC_MUTE# BATT_CHG_LED# CAPS_LED# PWR_LED# BATT_LOW_LED# SYSON VR_ON AC_PRESENT
EC_MUTE#
KB_MUTLI_KEY
R29
1
2 10K_0402_5%
NOVO#
R33
1
2 100K_0402_5%
ON/OFF#
R34
1
2 100K_0402_5%
EC_RSMRST# 3V/5VALW_PG VCOUT1_PROCHOT#
EC_PCIE_WAKE# R37
VCOUT1_PROCHOT#
VCOUT0_MAIN_PWR_ON
BKOFF# TYPEC_LIMIT_CTL1
CNVi_PWR_EN# PCIE_WAKE# 1 2 0_0402_5%
VCIN1_AC_IN
EC_ON ON/OFF#
LID_SW# SUSP# NUM_LED#
ON/OFF# SUSP# PECI
R41
VCC_IO2
R43
1
1 1
2 @
2
43_0402_1% 0_0402_5%
H_PECI
SUSP# PCIE_WAKE#
R35
1
@
2 100K_0402_5%
C
+3VALW_EC
C39 4.7U_0402_6.3V6M
VCOUT1_PROCHOT#
2
VR_HOT#
R40
1
2 0_0402_5%
R42
1
2 0_0402_5%
H_PROCHOT#
1 2
PCH_PWROK
1
PH on KB side
2
ESD
ESD
D
1
KB_BL_PWM
C38 ESD@ 100P_0402_50V8J
C42 ESD@ 100P_0402_50V8J
R45 10K_0402_5% NOKBL@
Security Classification
2
D
1
A
+3VALW
ENBKL SYS_PWROK
ME_EN VCIN0_PH1
KBL_ID
KBL
100P_0402_50V8J
2 4.7K_0402_5%
EC_SMB_CK4 EC_SMB_DA4
Keyboard BackLight_SELECT Funct i on
@
100P_0402_50V8J
I2C_2_SCL I2C_2_SDA EC_SMB_CK4 EC_SMB_DA4 USB_CHG_ILIM_SEL
TAB_SW#
119 120 126 128
110 112 114 115 116 117 118
NOVO# TP_DISABLE# DGPU_PWR_EN [11,26] USB_EN#
USB_EN#
97 98 99 109
100 101 102 103 104 105 106 107 108
VCIN1_BATT_TEMP
68 70 71 72
73 74 89 90 91 92 93 95 121 127
ECAGND
11 24 35 94 113
KB9022QD_LQFP128_14X14 SA000075S30
2
R15
R16
VCCST_PWRGD BEEP# EC_FAN_PWM1
AGND
C
R36 R38
PM_SLP_S3#/GPIO04 GPIO07 GPIO08 GPIO0A GPIO0B GPIO0C AC_PRESENT/GPIO0D PWM2/GPIO11 FAN_SPEED1/GPIO14 FANFB1/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A
21 23 26 27
69
+3VS
6 14 15 16 17 18 19 25 28 29 30 31 32 34 36
+5VALW USB_EN#
+3VS
EC_VCCST_PG/GPIO0F BEEP#/GPIO10 EC_FAN_PWM/GPIO12 AC_OFF/GPIO13
SM Bus
PM_SLP_S3# USB_CHG_CTL1 EC_CLEAR_CMOS# USB_CHG_CTL3 USB_CHG_EN USB_CHG_CTL2 USB_CHG_STATUS# KB_BL_PWM EC_FAN_SPEED1
1
ECAGND
PWM Output
CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCI#/GPIO0E CLKRUN#/GPIO1D
1
L2 1 2 ECAGND BLM15AX601SN1D _2P SM01000KL00
+EC_VCCA
8
+EC_VCCA
SM01000KL00
1
9 22 33 96 111 125
2
1
C33 1000P_0402_50V7K
1
C31 1000P_0402_50V7K
A
2
C30 0.1U_0201_10V K X5R
C29 0.1U_0201_10V K X5R
1
2 0_0603_5%
7
L1 1 2 BLM15AX601SN1D _2P
+3VALW_EC
+3VALW_EC
VCC_LPC VCC VCC VCC VCC0 VCC
1
R14
6
67
2
AVCC
1
2018/09/21
Issued Date
Compal Secret Data Deciphered Date
2019/09/21
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1
2
3
4
5
6
Compal Electronics, Inc.
EC KB9022QD
Size Document Number Custom 7
Date:
R ev 0.A
LA-H101P
Thursday, September 20, 2018
Sheet
8
34
of
51
A
B
C
D
E
KSI[0..7]
USB20_P7 USB20_N7 +3VS
1
RFP2
1
@
2 0_0402_5%
8 7 6 5 4 3 2 1
+5VS
JXT_FP201H-008G10M SP010020S00
Touch Pad
+3VS
DFP1 ESD@ CEST23LC5VB C/A_SOT23-3 SCA00004300
1
RTP1
+5VS_KB CAPS_LED#_R KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1
CFP1 0.1U_0201_10V K X5R
2 @ CTP1 0.1U_0201_10V K X5R
1
0_0402_5%
2
RTP2 4.7K_0402_5%
+TP_VCC
8 7 6 5 4 3 2 1
I2C_0_SCL I2C_0_SDA
TP_INT# TP_DISABLE#
2
2
KB_MUTLI_KEY
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
JKB1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
JKB2
ME@
GND GND
33 34
NUM_LED#
R266 1
S340_15@ 2
+5VS_KB CAPS_LED#_R KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1 KSO16 KSO17 NUM_LED#_R
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
KB_MUTLI_KEY
866_0402_5%
JXT_FP257H-032S10M
ME@
10 9
G2 G1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ME@
GND2 GND1
34 33
2
ACES_51612-0320M-001 SP011410151
SP01002FA00
ACES_51522-00801-001 SP01001AE00
2
3
1
CTP3 100P_0402_50V8J
@
@ CTP2 100P_0402_50V8J
1
8 7 6 5 4 3 2 1
S340-14 & S340-15 Right Pin Define
R265 2
CAPS_LED#
CAPS_LED#_R
1 866_0402_5%
1
DTP1 @ESD@ L03ESDL5V0CC3-2_SOT23-3
C229 ESD@ 0.1U_0201_10V K X5R
2
1
JTP1
RTP4 0_0402_5%
+3VS
2
KSO[0..17]
1
C340-15 Left Pin Define
2
3
1
ESD
H
9 GND GND
8 7 6 5 4 3 2 1
+3VS_FP
2 0_0402_5%
KSI[0..7]
KSO[0..17]
ME@
1
+3VALW
RFP1
JFP1
2
10
G
Keyboard
Finger printer 1
F
ESD
3
3
Keyboard Backlight
BATT LED
+5VS
D
ME2301DC-G_SOT23-3
1
RKBL2 KBL@ 1 2
KB_BL_PWM
30K_0402_1%
2
2
G
+5VS_KBL
1
S
3
RKBL1 KBL@ 10K_0402_5%
1
RS2 C340@ 1 2 523_0402_1%
1
RS3 S340@ 1 2 412_0402_1%
1
RS4 S340@ 1 2 523_0402_1%
1
1 2
2@ CKBL3
KBL@
0.01U_0402_16V7K
LED5
2 1
JKBL2 ME@
1 2 3 4 G1 G2
+5VS_KBL
B
1 2 3 4
BOT
2
SC500005930 LTST-C191KFKT-2CA_ORANGE
BATT_CHG_LED#
BATT_LOW_LED#
LED2
S340@
2
+VL
SC50000BB10 LTW-C193TS5-C_WHITE LED3
A
S340@
TOP
2
SC500005930 LTST-C191KFKT-2CA_ORANGE
4
JKBL1 ME@
1 2 3 G1 4 G2
5 6
Security Classification
C
2018/09/21
Issued Date
ACES_52501-00401-W01 SP011806072
ACES_51570-00401-P02 SP01002LF00
A
C340@
A
S340-15
S340-14 & C340-15 1 2 3 4 5 6
2 SC50000BB10 LTW-C193TS5-C_WHITE
4
+5VS_KBL
C340@
KBL@
KBL@ CKBL2 0.1U_0201_10V K X5R
1
QKBL1
CKBL1 10U_0402_6.3V6M
+5VALW
LED4
RS1 C340@ 1 2 412_0402_1%
Compal Secret Data Deciphered Date
2019/09/21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D
E
F
Title
Compal Electronics, Inc. KBL/KBD/LED/TP/HS Conn.
Size Document Number Custom Date: G
R ev 0.A
LA-H101P
Thursday, September 20, 2018
Sheet
35
H
of
51
5
4
3
2
1
G-Sensor
EC_FAN_PWM2 EC_FAN_SPEED2 1
+5VS
FAN 1
+3VS
D
+3VS_GS_R RGS1 1
2 1
2 0_0402_5%
+3VS_GS_R
7 10 5 6
CGS1 C340@ 0.1U_0201_10V K X5R
2 12
EC_SMB_DA4 EC_SMB_CK4
UGS1
2
C340@
VDD CSB
VDDIO PS
INT1 INT2
NC
1
CF1 10U_0402_6.3V6M
1 2 3 4 5 6
[33] EC_FAN_PWM1 [33] EC_FAN_SPEED1
EC_FAN_SPEED1
4 1
1 9 8
2
@RF@ CF4 6.8P_0402_50V8C
1 2
@RF@ CF7 6.8P_0402_50V8C
JFAN1 D
1 2 3 4 G1 G2 CVILU_CI4404M1HRT-NH SP02000VH00 ME@
@RF@ CF5 6.8P_0402_50V8C
BMA253_LGA12 SA000096W00
2
2
EC_FAN_PWM1
3 11
SDO GND GNDIO
SDx SCx
@RF@ CF3 6.8P_0402_50V8C
2
1 0_0603_5% +5VS_FAN1
2
RF1
1
@RF@ CF8 6.8P_0402_50V8C
+5VS
SMB Address: 0X18
2
@RF@ CF6 6.8P_0402_50V8C
1 0_0603_5% +5VS_FAN2
2
RF2 1
2 1
CF2 10U_0402_6.3V6M
1 2 3 4 5 6
[33] EC_FAN_PWM2 [33] EC_FAN_SPEED2
JFAN2 1 2 3 4 G1 G2 CVILU_CI4404M1HRT-NH SP02000VH00 ME@
Hall Sensor C
C
THERMISTOR for S340 14" +3VALW +3VS
2
1 CHS1 10P_0402_50V8J 2 C340@
VDD
2 CHS3 0.1U_0201_10V K X5R S340_14@1
VOUT
3
BOTTOM VCORE 1 2
QTH1
CHS4 10P_0402_50V8J S340_14@
C
TOP DDR
2
MMBT3904WH_SOT323-3
B E
CTH3 2200P_0402_25V7K @
CTH4 2200P_0402_25V7K
1
2
REMOTE1-
1
1 3
B
2
2
MMBT3904WH_SOT323-3E
1
CTH5 2200P_0402_25V7K @
CT114 2200P_0402_25V7K
+3VS_THM
UTH1 1
REMOTE2+ C
QTH2
Close UTH1
REMOTE1+
BOTTOM GPU B
1 2
LID_SW#
1
CTH1 0.1U_0201_10V6K
S340_14@ APX8132AI-TRG_SOT23-3
2
LID_SW#
2 0_0402_5%
@
1
UHS2
GND
LID_SW#
1
3
2 CHS2 0.1U_0201_10V K X5R C340@ 1
VOUT
3
1
1
VDD
GND
UHS1
2
+3VS_THM
+3VS_THM RTH3
C340@ APX8132AI-TRG_SOT23-3
REMOTE1+
2
REMOTE1-
3
REMOTE2+
4
REMOTE2-
5
VCC
SCL
DP1
SDA
DN1
ALERT#
DP2
THERM#
DN2
GND
10
EC_SMB_CK2
9
EC_SMB_DA2
1
+3VALW
EC_SMB_CK2
[8,24,33]
EC_SMB_DA2
[8,24,33]
8 7
@
RTH2 10K_0402_5%
2
for C340
THM_ALERT#
6
F75303M_MSOP10
2
B
SA000046C00
REMOTE2-
Address 1001_101xb REMOTE1,2 (+/-) : Trace width/space:10/10 mil Trace length:
