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PCS-931 Line Differential Relay Instruction Manual
NR Electric Co., Ltd.
Preface
Preface Introduction This guide and the relevant operating or service manual documentation for the equipment provide full information on safe handling, commissioning and testing of this equipment. Documentation for equipment ordered from NR is dispatched separately from manufactured goods and may not be received at the same time. Therefore, this guide is provided to ensure that printed information normally present on equipment is fully understood by the recipient. Before carrying out any work on the equipment, the user should be familiar with the contents of this manual, and read relevant chapter carefully. This chapter describes the safety precautions recommended when using the equipment. Before installing and using the equipment, this chapter must be thoroughly read and understood.
Health and Safety The information in this chapter of the equipment documentation is intended to ensure that equipment is properly installed and handled in order to maintain it in a safe condition. When electrical equipment is in operation, dangerous voltages will be present in certain parts of the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger personnel and equipment and cause personal injury or physical damage. Before working in the terminal strip area, the equipment must be isolated. Proper and safe operation of the equipment depends on appropriate shipping and handling, proper storage, installation and commissioning, and on careful operation, maintenance and servicing. For this reason, only qualified personnel may work on or operate the equipment. Qualified personnel are individuals who:
Are familiar with the installation, commissioning, and operation of the equipment and of the system to which it is being connected;
Are able to safely perform switching operations in accordance with accepted safety engineering practices and are authorized to energize and de-energize equipment and to isolate, ground, and label it;
Are trained in the care and use of safety apparatus in accordance with safety engineering practices;
Are trained in emergency procedures (first aid).
Instructions and Warnings The following indicators and standard definitions are used: PCS-931 Line Differential Relay
i Date: 2015-10-22
Preface
DANGER! means that death, severe personal injury and considerable equipment damage will occur if safety precautions are disregarded. WARNING! means that death, severe personal and considerable equipment damage could occur if safety precautions are disregarded. CAUTION! means that light personal injury or equipment damage may occur if safety precautions are disregarded. NOTICE! is particularly applies to damage to device and to resulting damage of the protected equipment.
DANGER! NEVER allow a open current transformer (CT) secondary circuit connected to this device while the primary system is live. Open CT circuit will produce a dangerously high voltage that cause death. WARNING! ONLY qualified personnel should work on or in the vicinity of this device. This personnel MUST be familiar with all safety regulations and service procedures described in this manual. During operating of electrical device, certain part of the device is under high voltage. Severe personal injury and significant device damage could result from improper behavior. WARNING! Do NOT touch the exposed terminals of this device while the power supply is on. The generated high voltage causes death, injury, and device damage. WARNING! Thirty seconds is NECESSARY for discharging the voltage. Hazardous voltage can be present in the DC circuit just after switching off the DC power supply. CAUTION! Earthing Securely earthed the earthing terminal of the device. Operating environment ONLY use the device within the range of ambient environment and in an ii
PCS-931 Line Differential Relay Date: 2015-10-22
Preface
environment free of abnormal vibration. Ratings Check the input ratings BEFORE applying AC voltage/current and power supply to the device. Printed circuit board Do NOT attach or remove printed circuit board if the device is powered on. External circuit Check the supply voltage used when connecting the device output contacts to external circuits, in order to prevent overheating. Connection cable Carefully handle connection cables without applying excessive force. NOTICE! The firmware may be upgraded to add new features or enhance/modify existing features, please MAKE SURE that the version of this manual is compatible with the product in your hand.
Copyright © 2016 NR. All rights reserved. We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination to third parties is strictly forbidden except where expressly authorized. The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated. We reserve the rights to make technical improvem ents without notice. NR ELECTRIC CO., LTD.
Tel: +86-25-87178888
Headquarters: 69, Suyuan Avenue, Jiangning, Nanjing 211102, China Manufactory: 18, Xinfeng Road, Jiangning, Nanjing 211111, China P/N: ZL_PCS-931_X_Instruction Manual_EN_Overseas General_X
PCS-931 Line Differential Relay
Fax: +86-25-87178999 Website: www.nrelect.com, www.nrec.com Version: R2.01
iii Date: 2015-10-22
Preface
Documentation Structure The manual provides a functional and technical description of this relay and a comprehensive set of instructions for the relay’s use and application. All contents provided by this manual are summarized as below:
1 Introduction Briefly introduce the application, functions and features about this device.
2 Technical Data Introduce the technical data about this relay, such as electrical specifications, mechanical specifications, ambient temperature and humidity range, communication port parameters, type tests, setting ranges and accuracy limits and the certifications that our products have passed.
3 Operation Theory Introduce a comprehensive and detailed functional description of all protective elements.
4 Supervision Introduce the automatic self-supervision function of this device.
5 Management Introduce the management function (measurement and recording) of this device.
6 Hardware Introduce the main function carried out by each plug-in module of this relay and providing the definition of pins of each plug-in module.
7 Settings List settings including system settings, communication settings, label settings, logic links and etc., and some notes about the setting application.
8 Human Machine Interface Introduce the hardware of the human machine interface (HMI) module and a detailed guide for the user how to use this relay through HMI. It also lists all the information which can be view through HMI, such as settings, measurements, all kinds of reports etc.
9 Configurable Function Introduce configurable function of the device and all configurable signals are listed.
10 Communication Introduce the communication port and protocol which this relay can support, IEC60970-5-103, IEC61850 and DNP3.0 protocols are introduced in details.
iv
PCS-931 Line Differential Relay Date: 2015-10-22
Preface
11 Installation Introduce the recommendations on unpacking, handling, inspection and storage of this relay. A guide to the mechanical and electrical installation of this relay is also provided, incorporating earthing recommendations. A typical wiring connection to this device is indicated.
12 Commissioning Introduce how to commission this relay, comprising checks on the calibration and functionality of this relay.
13 Maintenance A general maintenance policy for this relay is outlined.
14 Decommissioning and Disposal A general decommissioning and disposal policy for this relay is outlined.
15 Manual Version History List the instruction manual version and the modification history records.
Typographic and Graphical Conventions Deviations may be permitted in drawings and tables when the type of designator can be obviously derived from the illustration. The following symbols are used in drawings:
&
AND gate ≥1
OR gate
Comparator BI
SET
EN
Binary signal via opto-coupler I>
Input signal from comparator with setting
Input signal of logic setting for function enabling
PCS-931 Line Differential Relay
v Date: 2015-10-22
Preface SIG
Input of binary signal except those signals via opto-coupler
XXX
Output signal
Timer t t
Timer (optional definite-time or inverse-time characteristic) 10ms
0ms
Timer [delay pickup (10ms), delay dropoff (0ms), non-settable] [XXX]
0ms
Timer (delay pickup, settable) 0ms
[XXX]
Timer (delay dropoff, settable) [XXX]
[XXX]
Timer (delay pickup, delay dropoff, settable) IDMT
Timer (inverse-time characteristic)
---xxx is the symbol
Symbol Corresponding Relationship Basic
Example
A, B, C
L1, L2, L3
Ia, Ib, Ic, I0
IL1, IL2, IL3, IN
AN, BN, CN
L1N, L2N, L3N
Ua, Ub, Uc
VL1, VL2, VL3
ABC
L123
Uab, Ubc, Uca
VL12, VL23, VL31
U (voltage)
V
U0, U1, U2
VN, V1, V2
vi
PCS-931 Line Differential Relay Date: 2015-10-22
1 Introduction
1 Introduction Table of Contents 1 Introduction ....................................................................................... 1-a 1.1 Application....................................................................................................... 1-1 1.2 Function ........................................................................................................... 1-4 1.3 Features ........................................................................................................... 1-7
List of Figures Figure 1.1-1 Typical application of PCS-931 for single circuit breaker ................................. 1-1 Figure 1.1-2 Typical application of PCS-931 for double circuit breakers .............................. 1-2 Figure 1.1-3 Functional diagram of PCS-931............................................................................ 1-3
PCS-931 Line Differential Relay
1-a Date: 2015-10-22
1 Introduction
PCS-931 Line Differential Relay
1-b Date: 2015-10-22
1 Introduction
1.1 Application PCS-931 is a digital line differential protection with the main and back-up protection functions, which is designed for overhead line or cables and hybrid transmission lines of various voltage levels.
52
52
PCS-931
Optical fibre channel
PCS-931
Communication channel via direct dedicated fibre or MUX
Figure 1.1-1 Typical application of PCS-931 for single circuit breaker
In the case of main protection, PCS-931 comprises dual-channels current differential protection which can clear any internal fault instantaneously for the whole line with the aid of protection signal. Pilot distance protection (PUTT, POTT, blocking and unblocking) and pilot directional earth-fault protection with dual-channels (selectable for independent communication channel or sharing channel with POTT) are optional. Deviation of power frequency component (DPFC) distance protection with fixed forward direction can perform extremely high speed operation for close-up faults. There is direct transfer trip (DTT) feature incorporated in the device. PCS-931 also includes distance protection (1 forward zones and 4 settable forward or reverse zone distance protection with selectable mho or quadrilateral characteristic, dedicated pilot distance zone for pilot distance protection), out-of-step protection, 4 stages directional earth fault protection, 4 stages directional phase overcurrent protection, 3 stages directional negative-sequence overcurrent protection, 3 stages voltage protection (under/over voltage protection), 1 stage negative-sequence overvoltage protection, 4 stages frequency protection (under/over frequency protection), broken conductor protection, reverse power protection, pole discrepancy protection, breaker failure protection, thermal overload protection, and dead zone protection etc. Morever, a backup overcurrent and earth fault protection will be automatically enabled when VT circuit fails. In addition, stub differential protection is provided for one and a half breakers arrangement when transmission line is put into maintenance. PCS-931 can be configured to support single circuit breaker application or double circuit breakers application by PCS-Explorer. If the device is applied to double circuit breakers mode, all protection functions related to the number of circuit breaker will be affected, including circuit breaker position supervision, breaker failure protection, dead zone protection, pole discrepancy protection, synchrocheck, automatic reclosure, trip logic, CT circuit supervision, control and synchrocheck for manual closing.
PCS-931 Line Differential Relay
1-1 Date: 2015-10-22
1 Introduction Bus1 Single-phase voltage
52
PCS-931
Line 1 Three-phase voltage 52
Line 2 Single-phase voltage
52
Bus2
Figure 1.1-2 Typical application of PCS-931 for double circuit breakers
PCS-931 has selectable mode of single-phase tripping or three-phase tripping and configurable auto-reclosing mode for 1-pole, 3-poles and 1/3-pole operation. PCS-931 with appropriate selection of integrated protection functions can be applied for various voltage levels and primary equipment such as cables, overhead lines, interconnectors and transformer feeder, etc. It also supports configurable binary inputs, binary outputs, LEDs and IEC 61850 protocol.
PCS-931 Line Differential Relay
1-2 Date: 2015-10-22
1 Introduction BUS
52
81 85
21D 59Q
87L
21
50/51P
50/51G
50/51Q
50GVT
50PVT
50BF
49
46BC
32R
62PD
FR 59G
78 59P
FL Data Transmit/Receive
27P 50DZ
87STB (Only for one and a half breakers arrangement) SOTF
25
79
LINE
Figure 1.1-3 Functional diagram of PCS-931 No.
Function
ANSI
1
Current differential protection
87L
2
Pilot protection
85
3
DPFC distance protection
21D
4
Distance protection
21
5
Out-of-step protection
78
6
Phase overcurrent protection
50/51P
7
Earth fault protection
50/51G
8
Negative-sequence overcurrent protection
50/51Q
9
Overvoltage protection
59P
10
Undervoltage protection
27P
11
Negative-sequence overvoltage protection
59Q
12
Residual overvoltage protection
59G
13
Frequency protection
81
14
Broken conductor protection
46BC
15
Reverse power protection
32R
16
Breaker failure protection
50BF
17
Thermal overload protection
49
18
Stub differential protection
87STB
19
Dead zone protection
50DZ
20
Pole discrepancy protection
62PD
21
Switch onto fault
SOTF
22
Phase overcurrent protection when VT circuit failure
50PVT
23
Earth fault protection when VT circuit failure
50GVT
24
Synchronism check
25
PCS-931 Line Differential Relay
1-3 Date: 2015-10-22
1 Introduction 25
Automatic reclosure
79
26
Fault recorder
FR
27
Fault location
FL
1.2 Function 1.
Protection Function
Current differential protection
DPFC current differential element
Steady-state current differential element
Neutral current differential element
Distance protection (including eight zones)
One zone DPFC distance protection with fixed forward direction
One zone distance protection with fixed forward direction (including phase-to-ground and phase-to-phase, mho or quadrilateral characteristic)
One zone pilot distance protection with fixed forward direction (including phase-to-ground and phase-to-phase, mho or quadrilateral characteristic)
One zone pilot distance protection with fixed reverse direction (including phase-to-ground and phase-to-phase, mho or quadrilateral characteristic)
Four zones distance protection with settable forward or reverse direction (including phase-to-ground and phase-to-phase, mho or quadrilateral characteristic)
Load encroachment for mho and quadrilateral characteristic distance element
Power swing blocking releasing, selectable for each of above mentioned zones
Out-of-step protection
Overcurrent protection
Four stages phase overcurrent protection, selectable time characteristic (definite-time or inverse-time) and directionality (forward direction, reverse direction or non-directional)
Four stages directional earth fault protection, selectable time characteristic (definite-time or inverse-time) and directionality (forward direction, reverse direction or non-directional)
Four stages negative-sequence overcurrent protection, selectable time characteristic (definite-time or inverse-time) and directionality (forward direction, reverse direction or non-directional)
Breaker failure protection
Optional instantaneously re-tripping
One stage with two delay timers PCS-931 Line Differential Relay
1-4 Date: 2015-10-22
1 Introduction
Thermal overload protection
Stub differential protection
Dead zone protection
Pole discrepancy protection
Broken conductor protection
Reverse power protection
Switch onto fault (SOTF)
Via distance measurement elements
Via dedicated earth fault element
Via phase overcurrent element
Backup protection when VT circuit failure
Phase overcurrent protection when VT circuit failure
Ground overcurrent protection when VT circuit failure
Voltage protection
Three stages overvoltage protection
Three stages undervoltage protection
Three stages residual overvoltage protection
One stage negative-sequence overvoltage protection
Frequency protection
Four stages overfrequency protection
Four stages underfrequency protection
df/dt block criterion for underfrequency protection
Control function
Synchro-checking
Automatic reclosure (single shot or multi-shot (max. 4) for 1-pole AR and 3-pole AR)
Optional pilot scheme logic
Phase-segregated communication logic of distance protection
Weak infeed logic of pilot distance protection
Weak infeed logic of pilot directional earth fault protection
Communication scheme of current differential protection
PCS-931 Line Differential Relay
1-5 Date: 2015-10-22
1 Introduction
Direct optical link
Connection to a communication network, support G.703 and C37.94 protocol
Dual-channels redundancy
2.
Measurement and control function
Remote control (open and closing)
Synchronism check for remote and manual closing (only for one circuit breaker)
Energy metering (active and reactive energy are calculated in import respectively export direction)
3.
Logic
User programmable logic
4.
Additional function
Fault location
Fault phase selection
Parallel line compensation for fault location
VT circuit supervision
CT circuit supervision
Self diagnostic
DC power supply supervision
Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision events, 256 control logs and 1024 device logs.
Disturbance recorder including 32 disturbance records with waveforms (The file format of disturbance recorder is compatible with international COMTRADE file.)
Four kinds of clock synchronization methods
Conventional
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
IRIG-B (RS-485): IRIG-B via RS-485 differential level
PPM (DIN): Pulse per minute (PPM) via the optical coupler
PPS (DIN): Pulse per second (PPS) via the optical coupler
SAS
SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
SNTP (BC): Broadcast SNTP mode via Ethernet network PCS-931 Line Differential Relay
1-6 Date: 2015-10-22
1 Introduction
Message (IEC103): Clock messages through IEC103 protocol
Advanced
IEEE1588: Clock message via IEEE1588
IRIG-B (Fiber): IRIG-B via optical-fibre interface
PPS (Fiber): Pulse per second (PPS) via optical-fibre interface
NoTimeSync
5.
Monitoring
Number of circuit breaker operation (single-phase tripping, three-phase tripping and reclosing)
Channel status
Frequency
6.
Communication
Optional 2 RS-485 communication rear ports conform to IEC 60870-5-103 protocol
1 RS-485 communication rear ports for clock synchronization
Optional 2 or 4 Ethernet ports (depend on the chosen type of MON plug-in module) conform to IEC 61850 protocol, DNP3.0 protocol or IEC 60870-5-103 protocol over TCP/IP
Optional 2 Ethernet ports via optic fiber (ST interface) conform to IEC 61850 protocol, DNP3.0 protocol or IEC 60870-5-103 protocol over TCP/IP
GOOSE and SV communication function (optional NET-DSP plug-in module)
7.
User Interface
Friendly HMI interface with LCD and 9-button keypad on the front panel.
1 front multiplex RJ45 port for testing and setting
1 RS-232 or RS-485 rear ports for printer
Language switchover—English+ selected language
Auxiliary software—PCS-Explorer
1.3 Features
The intelligent device integrated with protection, control and monitor provides powerful protection function, flexible protection configuration, user programmable logic and configurable binary input and binary output, which can meet with various application requirements.
High-performance hardware platform and modularized design, fault detector DSP＋protection DSP. Fault detector DSP manages fault detector and protection DSP manages protection
PCS-931 Line Differential Relay
1-7 Date: 2015-10-22
1 Introduction
calucation. Their data acquisition system is completely independent in electronic circuit. DC power supply of output relay is controlled by the operation of fault detector element, which prevents maloperation due to error from ADC or damage of any apparatus.
Fast fault clearance for faults within the protected line, the operating time is less than 10 ms for close-up faults, less than 15ms for faults in the middle of protected line and less than 25ms for remote end faults.
The unique DPFC distance element integrated in the protective device provides extremely high speed operation and insensitive to power swing.
Self-adaptive floating threshold which only reflects deviation of power frequency component improves the protection sensitivity and stability under the condition of load fluctuation and system disturbance.
Advanced and reliable power swing blocking releasing feature which ensure distance protection operate correctly for internal fault during power swing and prevent distance protection from maloperation during power swing
Flexible automatic reclosure supports various initiation modes and check modes
Multiple setting groups with password protection and setting value saved permanently before modification
Powerful PC tool software can fulfill protection function configuration, modify setting and waveform analysis.
PCS-931 Line Differential Relay
1-8 Date: 2015-10-22
2 Technical Data
2 Technical Data Table of Contents 2 Technical Data ................................................................................... 2-a 2.1 Electrical Specifications ................................................................................. 2-1 2.1.1 AC Current Input .................................................................................................................. 2-1 2.1.2 AC Voltage Input .................................................................................................................. 2-1 2.1.3 Power Supply ....................................................................................................................... 2-1 2.1.4 Binary Input .......................................................................................................................... 2-1 2.1.5 Binary Output ....................................................................................................................... 2-2
2.2 Mechanical Specifications.............................................................................. 2-2 2.3 Ambient Temperature and Humidity Range .................................................. 2-3 2.4 Communication Port ....................................................................................... 2-4 2.4.1 EIA-485 Port ........................................................................................................................ 2-4 2.4.2 Ethernet Port ........................................................................................................................ 2-4 2.4.3 Optical Fibre Port ................................................................................................................. 2-4 2.4.4 Print Port .............................................................................................................................. 2-5 2.4.5 Clock Synchronization Port ................................................................................................. 2-5
2.5 Type Tests ........................................................................................................ 2-5 2.5.1 Environmental Tests............................................................................................................. 2-5 2.5.2 Mechanical Tests ................................................................................................................. 2-5 2.5.3 Electrical Tests ..................................................................................................................... 2-6 2.5.4 Electromagnetic Compatibility ............................................................................................. 2-6
2.6 Certifications ................................................................................................... 2-7 2.7 Terminals ......................................................................................................... 2-7 2.8 Measurement Scope and Accuracy ............................................................... 2-7 2.9 Management Function .................................................................................... 2-8 2.9.1 Control Performance............................................................................................................ 2-8
PCS-931 Line Differential Relay
2-a Date: 2015-10-21
2 Technical Data
2.9.2 Clock Performance .............................................................................................................. 2-8 2.9.3 Fault and Disturbance Recording ........................................................................................ 2-8 2.9.4 Binary Input Signal............................................................................................................... 2-8
2.10 Protective Functions..................................................................................... 2-8 2.10.1 Fault Detector .................................................................................................................... 2-8 2.10.2 Current Differential Protection ........................................................................................... 2-9 2.10.3 Distance Protection ............................................................................................................ 2-9 2.10.4 Phase Overcurrent Protection ........................................................................................... 2-9 2.10.5 Earth Fault Protection ........................................................................................................ 2-9 2.10.6 Negative-sequence Overcurrent Protection ...................................................................... 2-9 2.10.7 Overvoltage Protection ...................................................................................................... 2-9 2.10.8 Undervoltage Protection .................................................................................................. 2-10 2.10.9 Residual Overvoltage Protection ..................................................................................... 2-10 2.10.10 Negative-sequence Overvoltage Protection .................................................................. 2-10 2.10.11 Overfrequency Protection .............................................................................................. 2-10 2.10.12 Underfrequency Protection ............................................................................................ 2-10 2.10.13 Breaker Failure Protection ..............................................................................................2-11 2.10.14 Thermal Overload Protection ..........................................................................................2-11 2.10.15 Stub Differential Protection .............................................................................................2-11 2.10.16 Dead Zone Protection .....................................................................................................2-11 2.10.17 Pole Discrepancy Protection ..........................................................................................2-11 2.10.18 Broken Conductor Protection ........................................................................................ 2-12 2.10.19 Reverse Power Protection ............................................................................................. 2-12 2.10.20 Auto-reclosing ................................................................................................................ 2-12 2.10.21 Transient Overreach ...................................................................................................... 2-12 2.10.22 Fault Locator .................................................................................................................. 2-12
PCS-931 Line Differential Relay
2-b Date: 2015-10-21
2 Technical Data
2.1 Electrical Specifications 2.1.1 AC Current Input Phase rotation
ABC
Nominal frequency (fn)
50Hz, 60Hz
Rated current (In)
1A
Linear to
5A
0.05In~40In (It should measure current without beyond full scale against 20 times of related current and value of DC offset by 100%.)
Thermal withstand -continuously
4In
-for 10s
30In
-for 1s
100In
-for half a cycle
250In
Burden
< 0.15VA/phase @In
Number
Up to 7 current input according to various applications
< 0.25VA/phase @In
2.1.2 AC Voltage Input Phase rotation
ABC
Nominal frequency (fn)
50Hz, 60Hz
Rated voltage (Un)
100V~130V
Linear to
1V~170V
Thermal withstand -continuously
200V
-10s
260V
-1s
300V
Burden at rated
< 0.20VA/phase @Un
Number
Up to 6 voltage input according to various applications
2.1.3 Power Supply Standard
IEC 60255-11:2008
Rated voltage
110Vdc/125Vdc/220Vdc/250Vdc
110Vac/220Vac
Permissible voltage range
88~300Vdc
88~264Vac
Permissible AC ripple voltage
≤15% of the nominal auxiliary voltage
Burden Quiescent condition
[FD.ROC.3I0_Set]
Calculate negativesequence current: I2
I2>[FD.NOC.I2_Set]
7s
FD.Pkp
FD.ROC.Pkp
& FD.NOC.Pkp
EN
FD.NOC.En
Figure 3.5-2 Logic diagram of fault detector
3.5.7 Settings Table 3.5-2 Settings of fault detector No.
Name
Range
Step
Unit
1
FD.DPFC.I_Set
(0.050~30.000)×In
0.001
A
2
FD.ROC.3I0_Set
(0.050~30.000)×In
0.001
A
3
FD.NOC.I2_Set
(0.050~30.000)×In
0.001
A
Remark Current setting of DPFC current fault detector element Current setting of residual current fault detector element Current setting of negative-sequence current fault detector element Enabling/disabling negative-sequence
4
FD.NOC.En
current fault detector element
0 or 1
0: disable 1: enable
3.6 Auxiliary Element 3.6.1 General Application Auxiliary element (AuxE) is mainly used to program logics to meet users’ applications or further improve operating reliability of protection elements. Reliability of protective elements (such as distance element or current differential element) is assured, auxiliary element is usually not required to configure. Auxiliary elements including current change auxiliary element (AuxE.OCD), residual current auxiliary element (AuxE.ROC), phase current auxiliary element (AuxE.OC), voltage change auxiliary element (AuxE.UVD), phase under voltage auxiliary element (AuxE.UVG), phase-to-phase under voltage auxiliary element (AuxE.UVS) and residual voltage auxiliary element (AuxE.ROV), and they can be enabled or disabled by corresponding logic setting or binary inputs. Users can configure them according to applications via PCS-Explorer software.
3-13
PCS-931 Line Differential Relay Date: 2015-10-22
3 Operation Theory
3.6.2 Function Description 1.
Current change auxiliary element AuxE.OCD
It shares DPFC current element of DPFC fault detector. If DPFC fault detector operates (FD.DPFC.Pkp=1) and current change auxiliary element is enabled, current change auxiliary element operates. 2.
Residual current auxiliary element AuxE.ROC
There are 3 stages for residual current auxiliary element (AuxE.ROC1, AuxE.ROC2 and AuxE.ROC3). Each residual current auxiliary element will operate instantly if calculated residual current amplitude is larger than corresponding current setting The criteria are: AuxE.ROC1: 3I0>[AuxE.ROC1.3I0_Set] AuxE.ROC2: 3I0>[AuxE.ROC2.3I0_Set] AuxE.ROC3: 3I0>[AuxE.ROC3.3I0_Set] Where: 3I0: The calculated residual current 3.
Phase current auxiliary element AuxE.OC
There are 3 stages for phase current auxiliary element (AuxE.OC1, AuxE.OC2 and AuxE.OC3). Each phase current auxiliary element will operate instantly if phase current amplitude is larger than corresponding current setting. The criteria are: AuxE.OC1: IΦMAX>[AuxE.OC1.I_Set] AuxE.OC2: IΦMAX>[AuxE.OC2.I_Set] AuxE.OC3: IΦMAX>[AuxE.OC3.I_Set] Where: IΦMAX: The maximum phase current among three phases 4.
Voltage change auxiliary element AuxE.UVD
AuxE.UVD is based on phase-to-ground voltage change measured in all three phases. The criterion is: Δ UΦMAX>[AuxE.UVD.U_Set] Where: ΔUΦMAX: The maximum phase-to-ground voltage change among three phases 5.
Phase under voltage auxiliary element AuxE.UVG
3-14
PCS-931 Line Differential Relay Date: 2015-10-22
3 Operation Theory
AuxE.UVG will operate instantly if any phase-to-ground voltage is lower than corresponding voltage setting. The criterion is: UΦMIN[AuxE.ROCm.3I0_Set] SIG
AuxE.ROCm.En
SIG
AuxE.ROCm.Blk
EN
AuxE.ROCm.En
SIG
AuxE.OCm.En
SIG
AuxE.OCm.Blk
EN
AuxE.OCm.En
& AuxE.ROCm.St
&
AuxE.ROCm.On
& AuxE.OCm.On
SET Ia>[AuxE.OCm.I_Set]
& AuxE.OCm.StA
SET Ib>[AuxE.OCm.I_Set]
& AuxE.OCm.StB
SET Ic>[AuxE.OCm.I_Set]
& AuxE.OCm.StC
SET Ia>[AuxE.OCm.I_Set]
& >=1
AuxE.OCm.St
SET Ib>[AuxE.OCm.I_Set] SET Ic>[AuxE.OCm.I_Set]
3-19
PCS-931 Line Differential Relay Date: 2015-10-22
3 Operation Theory SET
ΔUa>[AuxE.UVD.U_Set]
SET
ΔUb>[AuxE.UVD.U_Set]
SET
ΔUc>[AuxE.UVD.U_Set]
SIG
AuxE.UVD.En
SIG
AuxE.UVD.Blk
EN
AuxE.UVD.En
SIG
AuxE.UVG.En
SIG
AuxE.UVG.Blk
EN
AuxE.UVG.En
SET
UA=1 & AuxE.UVD.St 0s
[AuxE.UVD.t_DDO]
AuxE.UVD.St_Ext
& AuxE.UVD.On
& AuxE.UVG.On
& AuxE.UVG.StA
SET
UB=1
>=1
&
& >=1 &
& [21SOTF.t_1PAR]
&
0
Figure 3.7-47 Logic diagram of distance SOTF protection by 1-pole or 3-pole AR 3-76
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For single-phase permanent fault, distance SOTF protection for 1-pole reclosing onto the faulty phase will trip three-phase circuit breaker. SIG
21SOTF.On
SIG
FD.Pkp
EN
[21SOTF.En_PDF]
SIG
21M(21Q)2.Rls_PSBR
SIG
PD signal
& & [21SOTF.t_PDF]
0
21SOTF.Op_PDF
& &
Figure 3.7-48 Logic diagram of distance SOTF protection by PD condition
Under pole discrepancy condition after single-phase tripping, distance SOTF protection will accelerate to operate if another fault happens to the healthy phase. SIG
21SOTF.Op_ManCls
>=1 21SOTF.Op
SIG
21SOTF.Op_AR
Figure 3.7-49 Logic diagram of distance SOTF protection
3.7.10.4 Settings Table 3.7-15 Settings of distance SOTF protection No.
Name
Range
Step
Unit
Remark Time delay of enabling SOTF protection (shared by distance
1
SOTF.t_En
0.000~10.000
0.001
s
SOTF protection, phase current SOTF protection and residual current SOTF protection) Enabling/disabling distance SOTF
2
21SOTF.En
protection
0 or 1
0: disable 1: enable Enabling/disabling distance
3
21SOTF.Z2.En_ManCls
0 or 1
SOTF
zone
2
of
protection
for
manual closing 1: enable 0: disable Enabling/disabling distance
4
21SOTF.Z3.En_ManCls
0 or 1
SOTF
zone
3
of
protection
for
manual closing 1: enable 0: disable 3-77
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Name
Range
Step
Unit
Remark Enabling/disabling distance
5
21SOTF.Z4.En_ManCls
0 or 1
SOTF
zone
4
of
protection
for
manual closing 1: enable 0: disable Time delay of distance protection
6
21SOTF.t_ManCls
0.000~10.000
0.001
s
accelerating to trip when manual closing Enabling/disabling distance
7
21SOTF.Z2.En_3PAR
0 or 1
SOTF
zone
2
of
protection
for
3-pole reclosing 1: enable 0: disable Enabling/disabling distance
8
21SOTF.Z3.En_3PAR
0 or 1
SOTF
zone
3
of
protection
for
3-pole reclosing 1: enable 0: disable Enabling/disabling distance
9
21SOTF.Z4.En_3PAR
0 or 1
SOTF
zone
4
of
protection
for
3-pole reclosing 1: enable 0: disable Enabling/disabling
zone
2
controlled by PSB of distance 10
21SOTF.Z2.En_PSBR
SOTF
0 or 1
protection
for
3-pole
reclosing 1: enable 0: disable Enabling/disabling
zone
3
controlled by PSB of distance 11
21SOTF.Z3.En_PSBR
SOTF
0 or 1
protection
for
3-pole
reclosing 1: enable 0: disable Enabling/disabling
zone
4
controlled by PSB of distance 12
21SOTF.Z4.En_PSBR
SOTF
0 or 1
protection
for
3-pole
reclosing 1: enable 0: disable
13
21SOTF.t_3PAR
0.000~10.000
0.001
3-78
s
Time delay of distance protection accelerating to trip when 3-pole
PCS-931 Line Differential Relay Date: 2015-10-22
3 Operation Theory No.
Name
Range
Step
Unit
Remark reclosing Enabling/disabling distance SOTF
14
21SOTF.En_1PAR
0 or 1
protection for 1-pole reclosing
1
0: disable 1: enable Time delay of distance protection
15
21SOTF.t_1PAR
0.000~10.000
0.001
s
accelerating to trip when 1-pole reclosing Enabling/disabling distance SOTF protection under pole discrepancy
16
21SOTF.En_PDF
0 or 1
conditions 1: enable 0: disable Time delay of distance protection
17
21SOTF.t_PDF
0.000~10.000
0.001
s
operating under pole discrepancy conditions
18
SOTF.U_Ddl
0~Unn
0.001
V
19
SOTF.t_Ddl
0.000~600.000
0.001
s
Undervoltage setting of deadline detection Time delay of deadline detection Option of manual SOTF mode ManClsBI: initiated by input signal of manual closing
ManClsBI
CBPos: initiated by CB position
CBPos 20
SOTF.Opt_Mode_ManCls
ManClsBI/CBPos:
ManClsBI/
initiated
by
either input signal of manual
CBPos
closing or CB position
AutoInit
AutoInit: initiated by no voltage
All
detection All: initiated by both binary input and no voltage detection
Table 3.7-16 Internal settings of distance SOTF protection No.
Name
Default Value
Unit
Remark Enabling/disabling distance SOTF protection for
1
21SOTF.En_ManCls
1
manual closing 0: disable 1: enable Enabling/disabling distance SOTF protection for
2
21SOTF.En_3PAR
1
3-pole reclosing 0: disable 1: enable
3-79
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3.8 Optical Pilot Channel 3.8.1 General Application The devices can transmit permissive signal, blocking signal, transfer signal and transfer trip used by current differential protection via optical fibre channel. The communication rate can be 64kbits/s or 2048kbits/s via optional dedicated optical fibre channel or multiplex channel. By the setting [FO.Protocol], the device can support G.703 or C37.94.
3.8.2 Function Description Besides current and voltage, 8 digital bits are integrated in each frame of transmission message for various applications. Each received message frame via fibre optical channel will pass through security check to ensure the integrity of the message consistently. 8 binary signals are configurable. The communication channel can be configured as single channel mode or as dual channels mode. (FOx, x can be 1 or 2) according to the optical pilot channel module selected. 3.8.2.1 Channel Interface The modules can communicate in two modes via multiplexer or dedicated optical fibre. Communication through dedicated fibre is usually recommended unless the received power does not meet with the requirement. Channel of 64kbits/s or 2048kbits/s via dedicated fibre is shown in Figure 3.8-1 and Figure 3.8-2. Two fibre cores of optical cable are dedicated to current differential protection. Two fibre cores of optical cable are normally in service, and all data are exchanged via the other healthy core if one core is failed.
Max 2km for 62.5/125um multi-mode FO C37.94 (N*64kbits/s)
PCS-931
TX
RX
RX
TX
PCS-931
ST connectors
ST connectors
Figure 3.8-1 Direct optical link up to 2km with 850nm
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Max 40km/100km for 9/125um single-mode FO
TX
RX
RX
TX
PCS-931
PCS-931
FC connectors
FC connectors
Figure 3.8-2 Direct optical link up to 40km with 1310nm or up to 100km with 1550nm
Channel of 64kbits/s or 2048kbits/s via multiplexer is shown in Figure 3.8-3, Figure 3.8-4 and Figure 3.8-5.
C37.94 (N*64kbits/s)
Multi-mode FO
Communication convertor
TX
RX
RX
TX
E
Interface Link to communicate device
PCS-931
ST connectors
O
ST connectors
Figure 3.8-3 Connect to a communication network via communication convertor
G.703 (64kbits/s)
MUX-64
Single-mode FO
TX
RX
RX
TX
E
Interface
PCS-931
FC connectors
O
Link to communicate device
FC connectors
Figure 3.8-4 Connect to a communication network via MUX-64
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G.703-E1 (2048kbits/s)
MUX-2M
Single-mode FO
TX
RX
RX
TX
E
Interface Link to communicate device
PCS-931
FC connectors
O
FC connectors
Figure 3.8-5 Connect to a communication network via MUX-2M
The protection transmission data format is shown as following table. Bit High
Data Frame
Description
Format
The header of transmission data format
LocID
The identity code of local device
Ia Ib
Three phase current
Ic
low
Time
Time for synchronising
FOx.Send1~FOx.Send8
The eight signals sent by channel No.x
Inter-trip (phase A/B/C)
Please refer to section 3.9.5.5 for the explanation
Permissive signal (phase A/B/C)
Please refer to section 3.9.5.7 for the explanation
Enable DIFF
Differential protection at both sides are enabled
CRC
3.8.2.2 Communication Clock Valid messages exchange is key factor for current differential protection. The device transmits and receives messages based on respective clocks, which are called transmit clock (i.e. clock TX) and receive clock (i.e. clock RX) respectively. Clock RX is fixed to be extracted from message frame, which can ensure no slip frame and no error message received. Clock TX has two options: 1. Use internal crystal clock, which is called internal clock. (master clock) 2. Use external clock. (slave clock) Depend on the clock used by the device at both ends, there are three modes. 1.
Master-master mode
Both ends use internal clock. 2.
Slave-slave mode
Both ends use external clock. 3-82
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3.
Master-slave mode
One of them uses internal clock, the other uses external clock The logic setting [FOx.En_IntClock] is used in current differential protection to select the communication clock. The internal clock is enabled automatically when the logic setting [FOx.En_IntClock] is set as “1”. Contrarily, the external clock is enabled automatically when the logic setting [FOx.En_IntClock] is set to “0”. If the device uses multiplex PCM channel, logic setting [FOx.En_IntClock] at both ends should be set as “0” (Mode 2). If the device uses dedicated optical fibre channel, clock Mode 1 and Mode 3 can be used. Mode 1 is recommended in considering simplification to user, i.e. logic setting [FOx.En_IntClock] at both ends should be set as “1”. 3.8.2.3 Identity Code In order to ensure reliability of the device when digital communication channel is applied, settings [FO.LocID] and [FO.RmtID] are provided as identity code to distinguish uniquely the device at remote end using same channel. Under normal conditions, the identity code of the device at local end should be different with that at remote end. In addition, it is recommended that the identity code of all devices, i.e., the setting [FO.LocID], should be unique in the power grid. The setting range is from 0 to 65535. Only for loop test, they are set as the same. The setting [FO.LocID] of the device at an end should be the same as the setting [FO.RmtID] of the device at opposite end and the greater [FO.LocID] between the two ends is chosen as a master end for sampling synchronism, the smaller [FO.LocID] is slave end. If the setting [FO.LocID] is set the same as [FO.RmtID], that implies the device in loopback testing state. The setting [FO.LocID] is packaged in the message frame and transmitted to the remote end. When the [FO.LocID] of the device at remote end received by local device is same to the setting [FO.RmtID] of local device, the message received from the remote end is valid, and protection information involved in message is read. When these settings are not matched, the message is considered as invalid and protection information involved in message is ignored, corresponding alarms will be issued. 3.8.2.4 Channel Statistics The device has the function of on-line channel monitoring and channel statistics. It can produce channel statistic report automatically at 9:00 every day and the report can be printed for operator to check the channel quality. The monitoring contents of channel status are shown as follows, and they can be viewed by the menu “Main Menu→Test→Prot Ch Counter→Chx Counter”. 1.
FOx.StartTime (starting time)
It shows the starting time of the channel status statistics of the device at local end. 2.
FO.RmtID (ID code of the remote end)
It shows the ID information received by the device at local end now.
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3.
FOx.t_ChLag (propagation delay of channel x)
It shows the calculated communication channel time delay of the device at local end now (unit: us). The calculation is based on the assumption of same channel path for to and from remote end. The device measures propagation delay of communication channel based on the below principle. Side S transmits a frame of message to side M, and meanwhile records the transmitting time “tss” on the basis of clock on side S. When side M receives the message, it will record receiving time “tmr” of the message with its own clock, and return a frame of message to side S at next fixed transmitting time, meanwhile data of “tms-tmr” is included in the frame of message. Side S will receive the message from side M at the time “tsr” and obtain the data of “tms-tmr”. Therefore, the propagation delay of the channel “Td” is obtained through calculation:
Td
(tsr t ss ) (tms t mr ) 2
By using the above calculated “Td”, the device automatically compensate time synchronization of sampling data at each end and transimission time lag.
T1
tss
tsr
tmr Td
tms
"S"
"M"
T2
Figure 3.8-6 Schematic diagram of communication channel time
4.
FOx.N_CRCFail (total number of error frame of channel x)
It shows the total number of the error frames of the device at local end from starting time of channel statistics until now. Error frame means that this frame fails in CRC check. 5.
FOx.N_FramErr (total number of abnormal messages of channel x)
It shows the total number of abnormal messages of the device at local end from starting time of channel statistics until now. 6.
FOx.N_FramLoss (total number of lost frames of channel x)
It shows the total number of the lost frames of the device at local end from starting time of channel statistics until now.
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7.
FOx.N_RmtAbnor (total number of abnormal messages from the remote end of channel x)
It shows the total number of abnormal messages received from the remote end from starting time of channel statistics until now. 8.
FOx.N_CRCFailSec (total number of serious error frames of channel x)
It shows the total number of serious error frame seconds of the device at local end from starting time of the channel statistics until now. 9.
FOx.N_LossSyn (total number of loss synchronous of channel x)
It shows the total number of loss synchronous of the device at local end from starting time of the channel statistics until now.
3.8.3 Function Block Diagram FOx FOx.En
FOx.On
FOx.Send1
FOx.Recv1
FOx.Send2
FOx.Recv2
FOx.Send3
FOx.Recv3
FOx.Send4
FOx.Recv4
FOx.Send5
FOx.Recv5
FOx.Send6
FOx.Recv6
FOx.Send7
FOx.Recv7
FOx.Send8
FOx.Recv8 FOx.Alm FOx.Alm_ID FOx.Alm_87L_Unmatched
3.8.4 I/O Signals Table 3.8-1 I/O signals of pilot channel No.
Input Signal
Description
1
FOx.En
Enabling channel x
2
FOx.Send1
Sending signal 1 of channel x
3
FOx.Send2
Sending signal 2 of channel x
4
FOx.Send3
Sending signal 3 of channel x
5
FOx.Send4
Sending signal 4 of channel x
6
FOx.Send5
Sending signal 5 of channel x
3-85
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3 Operation Theory 7
FOx.Send6
Sending signal 6 of channel x
8
FOx.Send7
Sending signal 7 of channel x
9
FOx.Send8
Sending signal 8 of channel x
Output Signal
Description
1
FOx.On
Channel x is enabled.
1
FOx.Recv1
Receiving signal 1 of channel x
2
FOx.Recv2
Receiving signal 2 of channel x
3
FOx.Recv3
Receiving signal 3 of channel x
4
FOx.Recv4
Receiving signal 4 of channel x
5
FOx.Recv5
Receiving signal 5 of channel x
6
FOx.Recv6
Receiving signal 6 of channel x
7
FOx.Recv7
Receiving signal 7 of channel x
8
FOx.Recv8
Receiving signal 8 of channel x
9
FOx.Alm
Channel x is abnormal
No.
Received ID from the remote end is not as same as the setting
10
FOx.Alm_ID
11
FOx.Alm_87L_Unmatched
[FO.RmtID] of the device in local end The status of differential protection of channel x between local end and remote end are inconsistent
3.8.5 Logic SIG
FOx.On (Remote end)
SIG
87L.FOx.On (Remote end)
SIG
87L.FOx.On (Local end)
& & >=1 & 10s
10s
&
SIG
FOx.Alm_87L_Unmatched
FOx.Alm
Figure 3.8-7 Logic diagram of differential protection enabling alarm
SIG
Receiving transfer signal n from remote side
SIG
FOx.Alm
SIG
FOx.Alm_ID
SIG
FOx.En
& FOx.Recvn
>=1
& FOx.On
EN
FOx.En
Figure 3.8-8 Logic diagram of receiving signal n
n can be 1~8
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PCS-931 Line Differential Relay Date: 2015-10-22
3 Operation Theory
3.8.6 Settings Table 3.8-2 Settings of pilot channel No.
Name
Range
Step
Unit
Remark
1
FO.LocID
0-65535
1
Identity code of the device at local end
2
FO.RmtID
0-65535
1
Identity code of the device at remote end
3
FO.Protocol
4
FOx.BaudRate
G.703
It is used to select protocol type, G.703 or
C37.94
C37.94
64 or 2048
kbps
Baud rate of optical pilot channel x The setting for the times of 64kbits/s, which
5
FOx.Nx64k_C37.94
1-12
1
is an N*64kbits/s standard defined by IEEE c37.94 standard Option of internal clock or external clock
6
FOx.En_IntClock
0 or 1
0: external clock 1: internal clock Enabling/disabling channel x
7
FOx.En
0 or 1
0: disable 1: enable
3.9 Current Differential Protection 3.9.1 General Application Current differential protection can be used as main protection of EHV and HV overhead line or cable. It includes phase-segregated current differential protection and neutral current differential protection. Current differential protection exchanges information among ends through communication channel. The device can flexibly select dedicated optical fibre channel or multiplex channel. The device calculates channel propagation delay continuously, and adjust sampling instant to ensure synchronization of sampled values at both ends. The channel propagation delay is calculated on the basis of the same route for sending and receiving channels. The communication rate used by the device is 64kbits/s or 2048kbits/s. The maximum tolerable one-way channel propagation delay is 20ms. A transfer trip and two transfer signals can be sent to the remote end to fulfill some auxiliary functions via a communication channel. The sensitivity of current differential protection is maintained for long lines by capacitive current compensation. However, line voltage is required for capacitive current compensation and it will be disabled automatically if no voltage is input or VT circuit fails.
3.9.2 Function Description The communication channel between two devices is monitored and its propagation delay is measured continuously. Once channel failure is detected, the current differential protection will be blocked automatically. 3-87
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3 Operation Theory
The detailed channel status, including channel delay, current from the remote end and differential current, can be displayed on the LCD. Current differential protection comprises three elements:
DPFC current differential element (2 stages)
Steady-state current differential element (2 stages)
Neutral current differential element (1 stage)
3.9.2.1 DPFC Current Differential Element (Stage 1) DPFC percent differential element only reflects fault components which can perform a sensitive protection for the transmission line. Lab test shows that it is more sensitive in the heavy load condition than the conventional percent differential element. Operation criteria: ΔIDiffΦ 0.75 ΔIBiasΦ ΔIDiffΦ IH
Equation 3.9-1
Where:
ΔIDiffΦ : The DPFC differential current ( ΔIDiffΦ ΔIMΦ ΔINΦ ) ΔIBiasΦ : The DPFC restraint current ( ΔIBiasΦ ΔIMΦ ΔINΦ ) IH : Max(1.5×[87L.I_Pkp],
1.5UN ) X C1L
The calculation of DPFC restraint current and differential current is phase-segregated. In these summations, charging current is eliminated from the phase currents by the charging current compensation function, so it is not needed to consider capacitive current during disturbance status for current differential setting threashold. If the charging current compensation function is disabled (the setting [87L.En_CapCurrComp] is 1.5UN set as “0”), is not considered to calculate pickup setting. The regulation is adaptive to X C1L other stages of current differential protection. Operation characteristic curve is shown as following figure.
3-88
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3 Operation Theory ΔIDiffΦ
k=1 k=0.75
IH
ΔIBiasΦ
Figure 3.9-1 Operation characteristic of DPFC current differential element
Due to high slope of DPFC percent differential protection, differential protection has higher ability of anti-CT saturation. Meanwhile, the load current won’t affect the sensitivity of DPFC differential elements, so the sensitivity is very high even for high impedance fault under heavy load. 3.9.2.2 DPFC Current Differential Element (Stage 2) Operation criteria:
ΔI DiffΦ 0.75 ΔI BiasΦ ΔI DiffΦ IM
Equation 3.9-2
Where:
IM : Max([87L.I_Pkp],
1.25UN ) X C1L
ΔIDiffΦ and ΔIBiasΦ are the same as those mentioned above.
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3 Operation Theory ΔIDiffΦ
k=1 k=0.75
IM
ΔIBiasΦ
Figure 3.9-2 Operation characteristic of DPFC current differential element
When the above criterion is met, the stage 2 of DPFC current differential element will operate after 1¼ cycles. 3.9.2.3 Steady-state Current Differential Element (stage 1) Operation criteria: IDiffΦ 0.6 IBiasΦ IDiffΦ IH
Equation 3.9-3
Where:
IDiffΦ : The phase differential current ( IDiffΦ IMΦ INΦ ) IBiasΦ : The phase restraint current ( IBiasΦ IMΦ INΦ ) IH : Max(1.5×[87L.I_Pkp],
1.5UN ) X C1L
Calculation of steady-state restraint current and differential current is phase-segregated. In these summations, charging current is eliminated from phase currents by the charging current compensation function. so it is not needed to consider capacitive current during disturbance status for current differential setting threashold Operation characteristic curve is shown as following figure.
3-90
PCS-931 Line Differential Relay Date: 2015-10-22
3 Operation Theory IDiffΦ
k=0.6
IH
IBiasΦ
Figure 3.9-3 Operation characteristic of steady-state current differential element
3.9.2.4 Steady-state Current Differential Element (stage 2) Operation criteria: IDiffΦ 0.6 IBiasΦ IDiffΦ IM
Equation 3.9-4
Where:
IM : Max([87L.I_Pkp],
1.25UN ) X C1L
IDiffΦ and IBiasΦ are the same as those mentioned above.
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k=0.6
IM
IBiasΦ
Figure 3.9-4 Operation characteristic of steady-state current differential element
When the above criterion is met, the stage 2 of steady-state differential current relay will operate after 1¼ cycles. 3.9.2.5 Neutral Current Differential Element The sensitivity of steady-state differential current element is too low for the slight fault during heavy load, and DPFC current differential element can only reflect the slight fault during heavy load, but low for the slow changing fault due to the small change of fault component. Neutral current differential element can be very sensitive to this kind of fault. Operation criteria:
IDiff0 0.75 IBias0 IDiff0 IL IDiffΦ 0.15 IBiasΦ IDiffΦ IL
Equation 3.9-5
Where:
IDiff0 : The neutral differential current
IDiffΦ : The phase differential current IBias 0: The neutral restraint current ( IBias0 IM0 IN0 ) IL : [87L.I_Pkp]
IBiasΦ is the same to those mentioned above 3-92
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In these summations, charging current is eliminated from the phase currents by the charging current compensation function. So it is not needed to consider capacitive current during disturbance status for setting threashold Operation characteristic curve is shown as following figure. IDiff0
k=0.75
IL
IBias0
Figure 3.9-5 Operation characteristic of neutral current differential element
Due to high slope of neutral current differential protection, differential protection has higher ability of anti-CT saturation. When the above criterion is met, the neutral current differential relay will operate with a time delay (controlled by an internal setting, default value is 40ms). 3.9.2.6 Capacitive Current Compensation For the long transmission line whose capacitive current is very large, in order to increase the sensitivity of current differential element especially for an earth fault associated with high fault resistance, capacitive current must be compensated to eliminate the effect that capacitive current has on differential current. The traditional method of compensating capacitive current can only compensate steady-state capacitive current. However, during the transient period, such as circuit energization (as shown in below figure), external fault clearance, etc., there is large transient capacitive current in the line.
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The traditional method cannot compensate the capacitive current completely, hence, a new method is adopted to compensate transient component of capacitive current. 1.
For long transmission line without shunt reactor
Phase capacitive current of line can be derived from “∏” equivalent circuit. Under normal condition, circuit energization and external fault clearance, not only steady-state component but also transient component of capacitive current can be compensated. It can improve the sensitivity of current differential protection.
A
M
ZL
N
ZL
B
ZL
C
Figure 3.9-6 ∏ equivalent circuit
For various system frequencies, the capacitive current which is shown in above figure can be calculated by: ic C
duc dt
Equation 3.9-6
Where:
ic : Capacitive current flowing through each capacitor C : Capacitance value
u c : Voltage across capacitors Based on the result of above equation, i.e. Equation 3.9-6, capacitance of each phase can be gained. 2.
For long transmission line with shunt reactor
Because a part of capacitive current has been compensated by shunt reactor, reactive current IL must be subtracted from capacitive current calculated by above equation, i.e. Equation 3.9-6.
3-94
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uf
uL ub
iLb
iL
uc iLc Figure 3.9-7 Equivalent circuit of shunt reactor
The current and voltage of reactor have the following relation: UL (t) - Uf (t) LP
diL (t) dt
Equation 3.9-7
To perform integral operation from t to t-∆t, iL can be calculated by: iL (t) iL (t - Δt)
1 LP
U (t) U (t)dt t
t Δt
L
Equation 3.9-8
f
Then, ic C
3.
duc iL (t) dt
Equation 3.9-9
For short transmission line
Capacitive current is very small, the sensitivity of current differential protection can still meet the requirement. The function, capacitive current compensation, will be disabled automatically if differential current is smaller than 0.1In. 4.
Transient capacitive current compensation
If transient capacitive current compensation is adopted, according to Equation 3.9-6 and Equation 3.9-9, the compensated transient capactive current of each side is calculated, then the transient differential current and restraint current after compensation is calculated, so differential protection function can be accomplished. 3.9.2.7 CT Supervision If CT circuit fails, an alarm will be issued with a time delay. When CT circuit failure occurs at one end, FD and current differential protection on the end might operate. However, FD on another end will not operate and not send any permissive signal of current differential protection. Therefore, the current differential protection will not maloperate. Meanwhile the healthy end will issue alarm signal [87L.FOx.Alm_Diff] which will be treated as the same as the alarm [CTS.Alm]. However, if CT circuit failure associated with internal fault or pickup due to system disturbance is detected, the device will show two kinds of behavior. If logic setting [87L.En_CTS_Blk] (differential protection being blocked during CT circuit failure) is 3-95
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set as “1”, the current differential protection will be blocked. If logic setting [87L.En_CTS_Blk] is set as “0” and the current differential current of the faulty phase is more than the differential current setting [87L.I_Pkp_CTS] during CT circuit failure, the current differential protection will operate with alarm signal being issued at the same time. 3.9.2.8 CT Saturation Two detectors are used to prevent undesired tripping caused by severe CT saturation during external close up fault. If the differential current is determined to be caused by CT saturation, the device will block differential protection to prevent mal-operation. 1.
High restraint coefficient and self-adaptive floating restraint threshold
Due to high slope of DPFC percent differential protection, differential protection has higher ability of anti-CT saturation. For external fault as following figure, the restraint current will be able to reflect the real quantity of system for a short time after current cross zero point and can be used as the restraint current after CT enters into saturation status by the use of self-adaptive floating threshold technology. Fault-Current-SideA 10
A
5 0 -5 -10
0
20
40
60
80
100
120
140
80
100
120
140
80
100
120
140
Fault-Current-SideB 20
A
10 0 -10
0
20
40
60 Diff-Current
20
A
10 0 -10
0
20
40
60 Restraint-Current
20 CT
A
10 0 -10 -20
0
20
40
60
80
100
120
140
(During external fault) Figure 3.9-8 Relation between CT saturation differential current and restraint current
2.
Asynchronous method: as shown in Figure 3.9-8, there is a short time before CT is saturated after fault current cross zero point, during the period, CT can convert fault current accurately, so there is restraint current but no differential current, the congruent relationship between increased differential current and increased restraint current is used to judge if there is a internal or external fault, strong anti-saturation ability can be get according to this method.
The above methods can prevent current differential protection from mal-operation if there is more than 1/4 cycle before CT is saturated.
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3.9.2.9 Synchronous Sampling Between both ends, the device with greater ID code, normally called “master”, is taken as reference, the device on the other end with smaller ID code, normally called “slave”, adjusts the sampling interval to synchronization with “master”. The devices exchange synchronization sampled values via communication channels. The preconditions for synchronization sampling of the devices between both ends include: 1.
The maximum unidirectional channel propagation delay ≤20ms.
2.
The sending and receiving channels are of same route or same propagation delay (i.e. the propagation delay of the two directions shall be equivalent).
Please refer to section 3.8 for more detail about optical pilot channel. 3.9.2.10 CT Ratio Adjust If the ratio of CTs on two ends of the line is different, current of two ends must be corrected to one reference value. PCS-931 regards local end as the referenced end, differential current and restraint current can be calculated since the current of the remote end is corrected by the setting. [87L.K_Cr_CT]. Setting principle: Suppose CT ratio, Terminal M: k M=IM1n : IM2n; Terminal N: kN=IN1n : IN2n IM1n: primary rated current of terminal M, IM2n: secondary rated current of terminal M IN1n: primary rated current of terminal N, IN2n: secondary rated current of terminal N If IM1n>= IN1n Terminal M: [87L.K_Cr_CT]=1.00 Terminal N: [87L.K_Cr_CT]=IN1n / IM1n For example: Terminal M: CT ratio=1250 : 5, the setting [87L.K_Cr_CT] is set as “0.5” Terminal N: CT ratio=2500 : 1, the setting [87L.K_Cr_CT] is set as “1.0” If current of terminal M is IM, current of terminal N is IN, the differential current and restraint current calculated on terminal M is:
I DiffΦ IMΦ
INΦ 87L.K_Cr_CT
I BiasΦ IMΦ
INΦ 87L.K_Cr_CT
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3.9.3 Function Block Diagram 87L 87L.FOx.En1
87L.On
87L.FOx.En2
87L.FOx.Op
87L.FOx.Blk
87L.Op 87L.Op_A 87L.Op_B 87L.Op_C 87L.Op_DPFC1 87L.Op_DPFC2 87L.Op_Biased1 87L.Op_Biased2 87L.Op_Neutral 87L.Op_InterTrp 87L.FOx.Alm_Diff 87L.FOx.Alm_Comp
3.9.4 I/O Signals Table 3.9-1 I/O signals of current differential protection No.
Input Signal
1
87L.FOx.En1
2
87L.FOx.En2
3
87L.FOx.Blk
No.
Output Signal
Description Current differential protection enabling input 1, it is triggered from binary input or programmable logic etc. (corresponding to channel x) Current differential protection enabling input 2, it can be a binary inputs or a logic link. (corresponding to channel x) Current differential protection blocking input, it is triggered from binary input or programmable logic etc. (corresponding to channel x) Description
1
87L.On
Current differential protection is enabled.
2
87L.FOx.On
Current differential protection is enabled. (corresponding to channel x) Current differential protection operates, if any of them “[87L.Op_DPFC1],
3
87L.Op
[87L.Op_DPFC2], [87L.Op_Biased1], [87L.Op_Biased2], [87L.Op_Neutral], [87L.Op_InterTrp]” operates, then [87L.Op] will operate.
4
87L.Op_A
Current differential protection of phase A operates
5
87L.Op_B
Current differential protection of phase B operates
6
87L.Op_C
Current differential protection of phase C operates
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87L.Op_DPFC1
Stage 1 of DPFC current differential element operates
8
87L.Op_DPFC2
Stage 2 of DPFC current differential element operates
9
87L.Op_Biased1
Stage 1 of steady-state current differential element operates
10
87L.Op_Biased2
Stage 2 of steady-state current differential element operates
11
87L.Op_Neutral
Zero-sequence current differential element operates
12
87L.Op_InterTrp
Inter-tripping element operates
13
87L.FOx.Alm_Diff
Differential current of channel x is abnormal
14
87L.FOx.Alm_Comp
The settings [XC1] and [XC0] and differential current of the device for channel x are mismatched.
|IDiff_Actual|[87L.I_Pkp_CTS]
EN
[87L.En_CTS_Blk]
SIG
CT circuit failure
SIG
87L.FOx.Alm_Diff
SIG
87L.FOx.On
SET
IDiff>[87L.I_Pkp](A)
SET
IDiff>0.15×IBias(A)
& >=1 >=1 & & Differential condition 1 (phase A)
& Common differential condition (phase A)
& Differential condition 1 (phase B)
SET
IDiff>[87L.I_Pkp](B)
& Common differential condition (phase B)
SET
IDiff>0.15×IBias(B)
& Differential condition 1 (phase C)
SET
IDiff>[87L.I_Pkp](C)
& Common differential condition (phase C)
SET
IDiff>0.15×IBias(C)
SIG
Differential condition 1 (phase A)
SIG
DIFF permitted (phase A)
EN
[87L.En_LocDiff]
SIG
Differential condition 1 (phase B)
SIG
DIFF permitted (phase B)
SIG
Differential condition 1 (phase C)
SIG
DIFF permitted (phase C)
SIG
FD.Pkp
& Differential condition 2 (phase A)
>=1
& Differential condition 2 (phase B)
>=1
& >=1
Differential condition 2 (phase C)
Figure 3.9-10 Differential condition of current differential protection
Where: IDiff: differential current IBias: restraint current A: phase A B: phase B 3-100
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C: phase C DIFF permitted (phase A/B/C): current differential protection permissive signal for phase A/B/C that received from the remote end via communication channel. Please refer to section 3.9.5.7 about the conditions to send permissive signal. 3.9.5.2 DPFC Differential Element SIG
Differential condition 2 (phase A)
SIG
DPFC DIFF1 (phase A)
SIG
Differential condition 2 (phase B)
SIG
DPFC DIFF1 (phase B)
SIG
Differential condition 2 (phase C)
SIG
DPFC DIFF1 (phase C)
EN
[87L.En_DPFC1]
SIG
87L.Op_DPFC1 (phase A)
SIG
87L.Op_DPFC1 (phase B)
SIG
87L.Op_DPFC1 (phase C)
SIG
Differential condition 2 (phase A)
SIG
DPFC DIFF2 (phase A)
SIG
Differential condition 2 (phase B)
SIG
DPFC DIFF2 (phase B)
SIG
Differential condition 2 (phase C)
SIG
DPFC DIFF2 (phase C)
EN
[87L.En_DPFC2]
SIG
87L.Op_DPFC2 (phase A)
SIG
87L.Op_DPFC2 (phase B)
SIG
87L.Op_DPFC2 (phase C)
& 87L.Op_DPFC1 (phase A)
& 87L.Op_DPFC1 (phase B)
& 87L.Op_DPFC1 (phase C)
>=1 87L.Op_DPFC1
& 1¼ cycles
0ms
87L.Op_DPFC2 (phase A)
1¼ cycles
0ms
87L.Op_DPFC2 (phase B)
1¼ cycles
0ms
87L.Op_DPFC2 (phase C)
&
&
>=1 87L.Op_DPFC2
Figure 3.9-11 DPFC differential element of current differential protection
Where: DPFC DIFF1: stage 1 of DPFC differential element DPFC DIFF2: stage 2 of DPFC differential element
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3.9.5.3 Steady-state Differential Element SIG
Differential condition 2 (phase A)
SIG
Steady-state DIFF1 (phase A)
SIG
Differential condition 2 (phase B)
SIG
Steady-state DIFF1 (phase B)
SIG
Differential condition 2 (phase C)
SIG
Steady-state DIFF1 (phase C)
EN
[87L.En_Biased1]
SIG
87L.Op_Biased1 (phase A)
SIG
87L.Op_Biased1 (phase B)
SIG
87L.Op_Biased1 (phase C)
SIG
Differential condition 2 (phase A)
SIG
Steady-state DIFF2 (phase A)
SIG
Differential condition 2 (phase B)
SIG
Steady-state DIFF2 (phase B)
SIG
Differential condition 2 (phase C)
SIG
Steady-state DIFF2 (phase C)
EN
[87L.En_Biased2]
SIG
87L.Op_Biased2 (phase A)
SIG
87L.Op_Biased2 (phase B)
SIG
87L.Op_Biased2 (phase C)
& 87L.Op_Biased1 (phase A)
& 87L.Op_Biased1 (phase B)
& 87L.Op_Biased1 (phase C)
>=1 87L.Op_Biased1
& 1¼ cycles
0ms
87L.Op_Biased2 (phase A)
1¼ cycles
0ms
87L.Op_Biased2 (phase B)
1¼ cycles
0ms
87L.Op_Biased2 (phase C)
&
&
>=1 87L.Op_Biased2
Figure 3.9-12 Steady-state differential element of current differential protection
Where: Steady-state DIFF1: stage 1 of steady-state differential element Steady-state DIFF2: stage 2 of steady-state differential element
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3.9.5.4 Neutral Current Differential Element SIG
Differential condition 2 (phase A)
SIG
REF DIFF (phase A)
SIG
Differential condition 2 (phase B)
SIG
REF DIFF (phase B)
SIG
Differential condition 2 (phase C)
SIG
REF DIFF (phase C)
EN
[87L.En_Neutral]
SIG
87L.Op_Neutral (phase A)
SIG
87L.Op_Neutral (phase B)
SIG
87L.Op_Neutral (phase C)
& t
0ms
87L.Op_Neutral (phase A)
t
0ms
87L.Op_Neutral (phase B)
t
0ms
87L.Op_Neutral (phase C)
&
&
>=1 87L.Op_Neutral
Figure 3.9-13 Neutral current differential element of current differential protection
3.9.5.5 Differential Inter-trip Element When a fault associated with high resistance occurrs in the outlet of long transmission line, the device of local end, which is near the fault, can pick up immediately, but, considering the influence of a considerable power source, the device of the remote end, which is far from the fault, can not pick up due to inapparent fault component. In order to avoid this case, any protection (such as distance protection, overcurrent protection and etc.) of local end operates, inter-trip signal of corresponding phase will be sent to the remote end. After receiving the inter-trip signal, the device of the remote end can pick up, if corresponding differential condition is met and the setting [87L.En_InterTrp] is set as “1”, the faulty phase will be inter-tripped. SIG
Differential condition 1 (phase A)
SIG
Inter-trip element (phase A)
SIG
52b_PhA
SIG
Differential condition 1 (phase B)
SIG
Inter-trip element (phase B)
SIG
52b_PhB
SIG
Differential condition 1 (phase C)
SIG
Inter-trip element (phase C)
SIG
52b_PhC
&
&
>=1 87L.InterTrp_Pkp
&
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Differential condition 2 (phase A)
SIG
Inter-trip element (phase A)
SIG
52b_PhA
SIG
Differential condition 2 (phase B)
SIG
Inter-trip element (phase B)
SIG
52b_PhB
SIG
Differential condition 2 (phase C)
SIG
Inter-trip element (phase C)
SIG
52b_PhC
EN
[87L.En_InterTrp]
SIG
87L.Op_InterTrp (phase A)
SIG
87L.Op_InterTrp (phase B)
SIG
87L.Op_InterTrp (phase C)
& & 10ms
0ms
87L.Op_InterTrp (phase A)
10ms
0ms
87L.Op_InterTrp (phase B)
10ms
0ms
87L.Op_InterTrp (phase C)
& &
& &
>=1 87L.Op_InterTrp
Figure 3.9-14 Differential inter-trip element of current differential protection
3.9.5.6 Weak Infeed SIG
3U0>1V
SIG
3U2>6V
SIG
UA=1 & 10s
87L.FOx.Alm_Diff
& 2s
EN
10s
10s
87L.FOx.Alm_Comp
[87L.En_CapCurrComp]
Figure 3.9-17 Self-check of current differential protection
Where: FOx: channel x
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Idiff: differential current of channel x Calculated Idiff ≠ Actual ldiff: |IDiff_Actual|=1
SET
[85.Opt_PilotMode]=PUTT
SET
[85.Opt_PilotMode]=POTT
& >=1
Figure 3.10-2 Logic diagram of receiving signal
Pilot distance protection has the following application modes: 3.10.2.1 Zone Extension When pilot scheme protection is out of service due to pilot channel failure or no pilot scheme protection is provided. The fault outside zone 1 only can be cleared by zone 2 with a time delay. It can not ensure that all faults within protected line are cleared instantaneously. As a supplement of pilot scheme protection, zone extension can clear the fault within the whole line instantaneously. Different with pilot distance protection, zone extension can also operate for external close up fault in parallel line, but power supply can be restored by AR. So zone extension should be blocked when AR is out of service and is not ready. In order to prevent too many lines from disconnecting with system due to zone extension operate when the circuit breaker is closed into permanent fault, zone extension should be blocked when AR operates. For temporary fault, the line can be into service again after AR operates successfully. For permanent fault in either local line or parallel line, distance protection with a time delay will operate. SIG
FD.Pkp
SIG
85-x.ZX.En1
SIG
85-x.ZX.En2
EN
[85.ZX.En]
SIG
85-x.ZX.Blk1
SIG
85-x.ZX.Blk2
SIG
79.Ready
SIG
Zpilot
& & & 85-x.ZX.On
>=1 & [85.t_DPU_ZX]
&
0ms
85-x.Op_ZX
Figure 3.10-3 Zone extension
Zone extension uses the setting of pilot zone (ZPilot), and its operation characteristic can be Mho 3-109
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or Quad. 3.10.2.2 Permissive Underreaching Transfer Trip (PUTT) Distance elements zone 1 (Z1) with underreaching setting and pilot zone (ZPilot) with overreaching setting are used for this scheme. Z1 element will send permissive signal to the remote end and release tripping after Z1 time delay expired. After receiving permissive signal with ZPilot element pickup, a tripping signal will be released. The signal transmission element for PUTT is set according to underreaching mode, so current reversal need not be considered. For PUTT, there may be a dead zone under weak power source condition. If the fault occurs outside Z1 zone at strong power source side, Z1 at weak power supply side may not operate to trip and transmit permissive signal, and pilot distance protection will not operate. Therefore, the system fault can only be removed by Z2 at strong power source side with time delay. ZPilot Z2 Z1 EM
M
A
Fault
B
Z1
EN
N
Z2 ZPilot
Relay A
Relay B
Z1
Z1
&
& 85-x.Op_Z
85-x.Op_Z
ZPilot
ZPilot
Figure 3.10-4 Simple schematic of PUTT
Pilot distance protection always adopts pilot channel 1, and the logic of PUTT is shown in Figure 3.10-5.
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21M1(21Q1).Op
0ms
100ms
85-x.ExTrp
0ms
150ms
>=1 &
SIG
SET
[85.Opt_PilotMode]=PUTT
SIG
85-x.Z.On
SIG
FD.Pkp
SIG
85-x.Valid_Recv1
SIG
ZPilot
85-x.Send1
& & & 8ms
0ms
85-x.Op_Z
Figure 3.10-5 Logic diagram of pilot distance protection (PUTT)
3.10.2.3 Permissive Overreaching Transfer Trip (POTT) ZPilot will send permissive signal to remote end once it picks up and release tripping signal upon receiving permissive signal from the remote end. When POTT is applied on parallel lines arrangement and the ZPilot setting covers 50% of the parallel line, there may be a problem under current reversal condition, settings for current reversal condition should be considered, please refer to section 3.10.2.6 for details. Under weak power source condition, the problem of dead zone at weak power source end is eliminated by the weak infeed logic, please refers to section 3.10.2.7 for details. ZPilot Z2
M
EM
Zpilot_Rev A
Fault
B
EN
N Zpilot_Rev
Z2 ZPilot
Relay A ZPilot
& >=1
Relay B
& 85-x.Op_Z
85-x.Op_Z
WI
>=1
ZPilot
WI
Figure 3.10-6 Simple schematic of POTT
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Zpilot
SIG
85-x.ExTrp
SIG
CB open position
>=1 0ms
150ms
&
>=1
& 200ms
0ms
& SIG
85-x.Valid_Recv1
SIG
ZPilot
& >=1
SIG
85-x.Z.On
SIG
WI
85-x.Send1
& & t1
t2
& 85-x.Op_Z
& 8ms
SIG
FD.Pkp
SET
[85.Opt_PilotMode]=POTT
0ms
Figure 3.10-7 Logic diagram of pilot distance protection (POTT)
Where: t1: pickup time delay of current reversal, the setting [85.t_DPU_CR1] t2: dropoff time delay of current reversal, the setting [85.t_DDO_CR1] 3.10.2.4 Blocking Permissive scheme has high security, but it relies on pilot channel seriously. Pilot distance protection will not operate when there is an internal fault with abnormal channel. Blocking scheme could be considered as an alternative. Blocking scheme takes use of pilot distance element Zpilot operation to terminate sending of blocking signal. Blocking signal will be sent once fault detector picks up without pilot zone Zpilot operation. Pilot distance protection will operate with a short time delay if pilot distance element operates and not receiving blocking signal after timer expired. The setting of pilot zone element Zpilot in Blocking scheme is overreaching, so current reversal condition should be considered. However, the short time delay of pilot distance protection has an enough margin for current reversal, that this problem has been resolved. The short time delay must consider channel delay and with a certain margin to set. As shown in Figure 3.10-8, an external fault happens to line MN. The fault is behind the device at M side, for blocking scheme, the device at M side will send blocking signal to the device at N side. If channel delay is too long, the device at side N has operated before receiving blocking signal. Hence, the time delay of pilot distance protection adopted in blocking scheme should be set according to channel delay.
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Fault
M
A
N
B
EN
Figure 3.10-8 Simple schematic of system fault
For blocking scheme, pilot distance protection will operate when there is an internal fault with abnormal channel, however, it is possible that pilot distance protection issue an undesired trip when there is an external fault with abnormal channel. ZPilot
EM
M
Zpilot_Rev A
Fault
B
EN
N
Zpilot_Rev ZPilot
Relay A
Relay B
FD.Pkp
&
Zpilot
& [85.t_DPU_Blocking1]
85-x.Op_Z
85-x.Op_Z
&
FD.Pkp
&
Zpilot
[85.t_DPU_Blocking1]
Figure 3.10-9 Simple schematic of blocking
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Zpilot
SIG
85-x.ExTrp
SIG
CB open position
>=1 0ms
150ms
& & 200ms SIG
>=1
0ms
&
85-x.Valid_Recv1
85-x.Send1
& SIG
FwdDir_ZPilot
SIG
WI
SIG
FD.Pkp
SET
[85.Opt_PilotMode]=Blocking
SIG
85-x.Z.On
>=1 & [85.t_DPU_Blocking1]
85-x.Op_Z
&
Figure 3.10-10 Logic diagram of pilot distance protection (Blocking)
Current reversal logic is only used for permissive scheme. For blocking scheme, the time delay of pilot distance protection has enough margin for current reversal, so current reversal need not be considered. 3.10.2.5 Unblocking Permissive scheme will trip only when it receives permissive signal from the remote end. However, it may not receive permissive signal from the remote end when pilot channel fails. For this case, pilot distance protection can adopt unblocking scheme. Under normal conditions, the signaling equipment works in the pilot frequency, and when the device operates to send permissive signal, the signaling equipment will be switched to high frequency. While pilot channel is blocked, the signaling equipment will receive neither pilot frequency signal nor high frequency signal. The signaling equipment will provide a contact to the device as unblocking signal. When the device receives unblocking signal from the signaling equipment, it will recognize channel failure, and unblocking signal will be taken as permissive signal temporarily. The unblocking function can only be used together with PUTT and POTT. EN
[85.En_Unblocking1]
SIG
85-x.Unblocking1
&
&
[85.t_Unblocking1] 0ms SIG
Detecting multi-phase fault
SET
[85.Opt_PilotCh1]
SIG
Pilot distance forward element
>=1 & 85-x.Unblocking1 Valid
Figure 3.10-11 Logic diagram of pilot distance protection (Unblocking) 3-114
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3.10.2.6 Current Reversal When there is a fault in one of the parallel lines, the direction of the fault current may change during the sequence tripping of the circuit breaker at both ends as shown in Figure 3.10-12: When a fault occurs on line C–D near breaker D, the fault current through line A-B to D will flow from A to B. When breaker D is tripped, but breaker C is not tripped, the fault current in line A-B will then flow from B to A. This process is the current reversal. M Strong source EM
N A
B
C
M Weak source EN
N A
B EN
EM
D
C
Direction of fault current flow before CB‘D’open
D
Direction of fault current flow after CB‘D’open
Figure 3.10-12 Current reversal
As shown above, the device A judges a forward fault while the device B judges a reverse fault before break D is tripped. However, the device A judges a reverse fault while the device B judges a forward fault after breaker D is tripped. There is a competition between pickup and drop off of pilot zones in the device A and the device B when the fault measured by the device A changes from forward direction into reverse direction and vice versa for the device B. There may be maloperation for the device in line A-B if the forward direction of the device B has operated but the forward direction of the device A drops off slightly slower or the forward direction of the device B has operated but the forward direction information of the device A is still received due to the channel delay (the permissive signal is received). In general, the following two methods shall be adopted to solve the problem of current reversal: 1.
The fault shall be measured by means of the reverse element of the device B. Once the reverse element of the device B operates, the send signals and the tripping circuit will be blocked for a period of time after a short time delay. This method can effectively solve the problem of competition between the device A and the device B, but there shall be a precondition. The reverse element of the device B must be in cooperation with the forward element of the device A, i.e. in case of a fault in adjacent lines, if the forward element of the device A operates, and the reverse element of the device B must also operate. Once the bilateral cooperation fails, the anticipated function cannot be achieved. In addition, the blocking time for sending signals and the tripping circuit after the reverse element of the device B operates shall be set in combination with the channel time delay.
2.
Considering the pickup and drop off time difference of distance elements and the channel time delay between the device A and the device B, the maloperation due to current reversal shall be eliminated by setting the time delay. The reverse direction element of the device is not required for this method, the channel time delay and the tripping time of adjacent breaker shall be taken into account comprehensively.
This protection device adopts the second method to eliminate the maloperation due to current reversal. 3-115
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Pilot forward zone start condition
& t1
SIG
t2
Current reversal blocking
Signal received conditon
Figure 3.10-13 Logic diagram of current reversal blocking
t1: [85.t_DPU_CR1] t2: [85.t_DDO_CR1] Referring to above figure, when signal from the remote end is received without pilot forward zone pickup, the current reversal blocking logic is enabled after t1 delay. The time delay of t1 [85.t_DPU_CR1] shall be set the shortest possible but allowing sufficient time for pilot forward zone pickup, generally set as 25ms. Once the current reversal logic is enabled, the healthy line device B transfer tripping is blocked. The logic will be disabled by either the dropoff of signal or the pickup of pilot forward zone. A time delay t2 [85.t_DDO_CR1] is required to avoid maloperation for the case that the pilot forward zone (or forward element of pilot directional earth-fault protection) of device B picks up before the signal from device A drops off. Considering the channel propagation delay and the pickup and drop-off time difference of pilot forward zone (or pilot directional earth-fault element) with margin, t2 is generally set between 25ms~40ms. Because the time delay of pilot distance protection has an enough margin to current reversal, current reversal blocking only used for permissive scheme not blocking scheme. 3.10.2.7 Weak Infeed In case of a fault in line at one end of which there is a weak power source, the fault current supplied to the fault point from the weak power source is very small or even nil, and the conventional distance element could not operate. The weak infeed logic combines the protection information from the strong power source end and the electric feature of the local end to cope with the case. The weak infeed logic can be only applied for BOTT and POTT. The weak infeed logic has options for echo or both echo and tripping. ZPilot Z1 M
EM
Zpilot_Rev
A
Fault
Zpilot_Rev B
Z1
EN
N
ZPilot Load
Figure 3.10-14 Line fault description 3-116
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When the weak infeed logic is enabled, distance forward and reverse element and direction element of directional earth-fault protection do not operate with the voltage lower than the setting [85.U_UV_WI] after the device picks up, upon receiving signal from remote end, the weak infeed logic will echo the signal back to remote end for 200ms if the weak infeed echo is enabled, the weak infeed end will echo signal and release tripping according to the logic. ZPilot_Rev at weak source end must coordinate with ZPilot_Set of the remote end. The coverage of ZPilot_Rev must exceed that of ZPilot_Set of the remote end. ZPilot_Rev only activates in the protection calculation when the weak infeed logic is enabled. In case of the weak infeed logic not enabled, the setting coordination is not required. If the device does not pick up, and the weak infeed logic is enabled, upon receiving signal from remote end with the voltage lower than the setting [85.U_UV_WI], the weak infeed logic will echo back to remote end for 200ms. When either weak infeed echo or weak infeed tripping is enabled, then the weak infeed logic is deemed to be enabled. During the device picking up, the weak infeed logic is shown in Figure 3.10-15. SIG
FD.Pkp
SIG
85-x.Valid_Recv1
SIG
Pilot DEF forward direction
SIG
Pilot DEF reverse direction
SIG
Pilot distance forward direction
SIG
Pilot distance reverse direction
EN
[85.En_WI]
SET
Up=1
>=1
200ms
0ms
&
Figure 3.10-15 Weak infeed logic during pickup
If the device does not pick up, the weak infeed logic is shown as the following figure: SIG
Signal receive condition
EN
[85.En_WI]
SET
Up=1 &
SIG
85-x.Abnor_Ch1
SIG
85-x.Unblocking1 Valid
SET
[85.Opt_PilotMode]=PUTT
& >=1
>=1 85-x.Valid_Recv_DEF
EN
[85.DEF.En_IndepCh]
SET
[85.Opt_PilotMode]=Blocking
&
& >=1
SIG
85-x.Recv2
SIG
85-x.Abnor_Ch2
SIG
85-x.Unblocking2 Valid
&
Figure 3.11-2 Logic diagram of receiving signal SIG
FwdDir_ROC
& 85-x.FwdDir_DEF_Pilot
SIG
3I0>[85.DEF.3I0_Set]
SIG
RevDir_ROC
& 85-x.RevDir_DEF_Pilot
SIG
FD.ROC.Pkp
Figure 3.11-3 Forward/reverse direction of zero-sequence power
3.11.2.1 Permissive Transfer Trip (PTT) Pilot protection with permissive scheme receives permissive signal from the device of remote end, so as to combine with local discrimination condition to accelerate tripping, so it has high security. Operation of forward directional earth fault element is used to send permissive signal to the remote end when the protection is enabled and will release tripping signal upon receiving permissive signal from the remote end with further guarded by no operation of reverse directional earth fault element. This ensures the security of the protection. The following figure shows the schematic of permissive transfer trip.
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M
EM
A
Fault
B
EN
N
85-x.RevDir_DEF_Pilot 85-x.FwdDir_DEF_Pilot
Relay A 85-x.FwdDir_DEF_Pilot
&
& [85.DEF.t_DPU]
85-x.Op_DEF
85-x.Op_DEF
[85.DEF.t_DPU] 85-x.FwdDir_DEF_Pilot Relay B
Figure 3.11-4 Simple schematic of DEF (permissive scheme)
For blocking scheme, pilot directional earth-fault protection will operate when there is an internal fault with abnormal channel, however, it is possible that pilot directional earth-fault protection issue an undesired trip when there is an external fault with abnormal channel. 0ms
SIG
85-x.ExTrp
SIG
CB open position
SIG
85-x.Valid_Recv_DEF
SIG
FD.Pkp
SIG
85-x.FwdDir_DEF_Pilot
SIG
85-x.RevDir_DEF_Pilot
SIG
85-x.Valid_Recv_DEF
SIG
FD.Pkp
SET
[85.Opt_PilotMode]=PUTT
SET
[85.Opt_PilotMode]=POTT
SIG
85-x.DEF.On
150ms
&
>=1
& 200ms
0ms
& 85-x.Send_DEF
& & & t1
t2
&
>=1 & &
& [85.DEF.t_DPU]
>=1
85-x.Op_DEF
& EN
[85.DEF.En_IndepCh]
Figure 3.11-5 Logic diagram of DEF (permissive scheme)
t1: pickup time delay of current reversal t2: dropoff time delay of current reversal 3-123
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When adopting independent pilot channel 2, settings of t1 [85.t_DPU_CR2] and t2 [85.t_DDO_CR2] should be considered individually from channel 1. When sharing pilot channel 1 with pilot distance protection, t1 and t2 are the settings [85.t_DPU_CR1] and [85.t_DDO_CR1] respectively. 3.11.2.2 Blocking Permissive scheme has high security, but it relies on pilot channel seriously. Pilot directional earth-fault protection will not operate when there is an internal fault with abnormal channel. Blocking scheme could be considered as an alternative. Blocking scheme sends blocking signal when fault detector picks up and zero-sequence forward element does not operate or both zero-sequence forward element and zero-sequence reverse element do not operate. Pilot directional earth-fault protection will operate if forward directional zero-sequence overcurrent element operates and not receiving blocking signal. 85-x.FwdDir_DEF_Pilot
EM
85-x.RevDir_DEF_Pilot
M
A
Fault
B
EN
N
85-x.RevDir_DEF_Pilot 85-x.FwdDir_DEF_Pilot
Relay A
Relay B
FD.Pkp
FD.Pkp
& 85-x.RevDir_DEF_Pilot
&
&
&
85-x.FwdDir_DEF_Pilot
85-x.FwdDir_DEF_Pilot
&
& 85-x.Op_DEF
&
85-x.RevDir_DEF_Pilot
85-x.Op_DEF
[85.DEF.t_DPU]
& [85.DEF.t_DPU]
Figure 3.11-6 Simple schematic of blocking
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Trp
SIG
85-x.ExTrp
SIG
CB open position
SIG
85-x.FwdDir_DEF_Pilot
SIG
85-x.RevDir_DEF_Pilot
SIG
85-x.Valid_Recv_DEF
SIG
FD.Pkp
SET
[85.Opt_PilotMode]=Blocking
SIG
85-x.DEF.On
>=1 0ms
150ms
>=1 & 85-x.Send_DEF
& &
& [85.DEF.t_DPU]
85-x.Op_DEF
&
Figure 3.11-7 Logic diagram of DEF (Blocking scheme)
When DEF shares pilot channel 1 with pilot distance protection, time delay of pilot directional earth-fault protection will change from the setting [85.DEF.t_DPU] to the setting [85.t_DPU_Blocking1]. Because the time delay of pilot directional earth-fault protection has enough margin for current reversal, so blocking scheme should not consider the current reversal condition. 3.11.2.3 Unblocking Permissive scheme will operate only when it receives permissive signal from the remote end. However, it may not receive permissive signal from the remote end when pilot channel fails. For this case, pilot directional earth-fault protection can adopt unblocking scheme. Under normal conditions, the signaling equipment works in the pilot frequency, and when the device operates to send permissive signal, the signaling equipment will be switched to high frequency. While the channel is blocked, the signaling equipment will receive neither pilot frequency signal nor high frequency signal. The signaling equipment will provide a contact to the device as unblocking signal. When the device receives unblocking signal from the signaling equipment, it will recognize channel failure, and unblocking signal will be taken as permissive signal temporarily. The unblocking scheme can only be used together with permissive scheme. EN
[85.En_Unblocking2]
SIG
85-x.Unblocking2
& & & [85.t_Unblocking2]
SIG
Selection of multi-phase
EN
[85.Opt_PilotCh2]
SIG
Pilot DEF forward detection
85-x.Unblocking2 Valid
0ms
>=1
Figure 3.11-8 Logic diagram for unblocking 3-125
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3.11.2.4 Current Reversal The reach of directional earth-fault protection is difficult to define. There may have problem for pilot direction earth-fault protection applied on parallel line arrangement due to current reversal phenomenon. Current reversal blocking logic using time delay method is adopted in the device. It is the same logic as pilot distance protection. Please refer to section 3.10.2.6 for details. The only difference is that different signal receive terminal is used if independent channel is selected. 3.11.2.5 CB Echo It is the same logic as pilot distance protection. Please refer to section 3.10.2.8 for details. The only difference is that different signal receive terminal is used if independent channel is selected.
3.11.3 Function Block Diagram 85 85-x.DEF.En1
85-x.DEF.On
85-x.DEF.En2
85-x.Op_DEF
85-x.DEF.Blk
85-x.DEF_BlkAR
85-x.Abnor_Ch1
85-x.Send1
85-x.Abnor_Ch2
85-x.Send2
85-x.Rcv1 85-x.Rcv2 85-x.ExTrp 85-x.Unblocking1 85-x.Unblocking2
3.11.4 I/O Signals Table 3.11-1 I/O signals of pilot directional earth-fault protection No.
Input Signal
1
85-x.DEF.En1
2
85-x.DEF.En2
3
85-x.DEF.Blk
4
85-x.Abnor_Ch1
5
85-x.Abnor_Ch2
Description Pilot directional earth-fault protection x enabling input 1, it is triggered from binary input or programmable logic etc. (x=1 or 2) Pilot directional earth-fault protection x enabling input 2, it is triggered from binary input or programmable logic etc. (x=1 or 2) Pilot directional earth-fault protection x blocking input, it is triggered from binary input or programmable logic etc. (x=1 or 2) Input signal of indicating that pilot channel 1 is abnormal for pilot directional earth-fault protection x (x=1 or 2) Input signal of indicating that pilot channel 2 is abnormal for pilot directional earth-fault protection x (x=1 or 2)
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6
85-x.Recv1
7
85-x.Recv2
8
85-x.ExTrp
9
85-x.Unblocking1
Unblocking signal 1 for pilot directional earth-fault protection x (x=1 or 2)
10
85-x.Unblocking2
Unblocking signal 2 for pilot directional earth-fault protection x (x=1 or 2)
No.
Output Signal
earth-fault protection x (x=1 or 2) Input signal of receiving permissive signal via channel 2 for pilot directional earth-fault protection x (x=1 or 2) Input signal of initiating sending permissive signal from external tripping signal (x=1 or 2)
Description
1
85-x.DEF.On
Pilot directional earth-fault protection x is enabled. (x=1 or 2)
2
85-x.Op_DEF
Pilot directional earth-fault protection x operates. (x=1 or 2)
3
85-x.DEF_BlkAR
Pilot directional earth-fault protection x operates to block AR. (x=1 or 2) Output signal of sending permissive signal 1 for pilot directional earth-fault
4
85-x.Send1
protection x when pilot directional earth-fault protection sharing pilot channel 1 with pilot distance protection (x=1 or 2) Output signal of sending permissive signal 2 for pilot directional earth-fault
5
85-x.Send2
protection x when pilot directional earth-fault protection adopting independent pilot channel 2 (x=1 or 2)
3.11.5 Settings Table 3.11-2 Settings of pilot directional earth-fault protection No.
Name
Range
Step
Unit
Remark Enabling/disabling pilot directional
1
85.DEF.En
earth-fault protection
0 or 1
0: disable 1: enable Enabling/disabling pilot directional earth-fault protection operate to block AR
2
85.DEF.En_BlkAR
0 or 1
0: selective phase tripping and not blocking AR 1: three-phase tripping and blocking AR Enabling/disabling channel
for
pilot
independent directional
earth-fault protection 3
85.DEF.En_IndepCh
0:
0 or 1
pilot
directional
earth-fault
protection sharing same channel with pilot distance protection 1:
pilot
directional
earth-fault
adopting independent pilot channel 4
85.En_Unblocking2
Enabling/disabling
0 or 1
unblocking
scheme for pilot DEF via pilot
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Name
Range
Step
Unit
Remark channel 2 0: disable 1: enable
5
85.DEF.3I0_Set
(0.050~30.000)×In
0.001
A
6
85.DEF.t_DPU
0.001~10.000
0.001
s
Current setting of pilot directional earth-fault protection Time delay of
85.t_DPU_CR2
0.000~1.000
0.001
s
directional
earth-fault protection Time
7
pilot
delay
pickup for
current
reversal logic when pilot directional earth-fault
protection
adopts
independent pilot channel 2 Time delay dropoff for current 8
85.t_DDO_CR2
0.000~1.000
0.001
s
reversal logic when pilot directional earth-fault
protection
adopts
independent pilot channel 2 Table 3.11-3 Internal settings of pilot distance protection No. 1
Name
Default Value
85.t_Unblocking2
Unit
0.2
s
Remark Pickup time delay of unblocking scheme for pilot channel 2 Option of PLC channel for pilot channel 2
2
85.Opt_PilotCh2
1
0: phase-to-phase channel 1: phase-to-ground channel
3.12 Current Direction 3.12.1 General Application Overcurrent protection is widely used in the power system as backup protection, but in some cases, the direction of current is necessary to aid to complete the selective tripping. As shown below: L EM
M C
Fault
D
N A
B
EN
Figure 3.12-1 Line fault description
When line LM has an earth fault, the fault currents flowing through the relay A and the relay D are of similar magnitude in most cases. It is desirable that the fault is isolated from the power system by tripping the circuit breaker C and circuit breaker D. Hence, the overcurrent protection of relay A and relay D require to associate with current direction to fulfill selective tripping. Directional earth fault protection has a time delay due to coordinate with that of downstream so it 3-128
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3 Operation Theory
cannot clear the fault quickly. Pilot directional earth-fault protection, which is fulfilled by directional earth fault element on both ends, it can maintain fast operation and achieve high sensitivity to detect high resistance fault.
3.12.2 Function Description The module computes direction of phase current and phase-to-phase current, zero-sequence current and negative-sequence current. The direction of phase current and phase-to-phase current equips with an under-voltage direction function to ensure that phase or phase-to-phase overcurrent protection has explicit directionality when the polarized voltage is too low for close up fault. The direction of zero-sequence current and negative-sequence current direction equips with an impedance compensation function to ensure that zero-sequence or negative-sequence overcurrent protection has explicit directionality when the zero-sequence voltage or the negative-sequence voltage is too low. 3.12.2.1 Phase/Phase-to-phase Current Direction By setting the characteristic angle [RCA_OC] to determine the most sensitive forward angle of phase current and phase-to-phase current, power value is calculated using phase current with phase polarized voltage or phase-to-phase current with phase-to-phase polarized voltage to determine the direction of phase current or phase-to-phase current respectively in forward direction or reverse direction. When the power value is zero, neither forward direction nor reverse direction is considered. As shown below: jX U
φ
θ
I
R
O
Forward direction
Reverse direction
Figure 3.12-2 Vector diagram of current and voltage
Where: φ is the setting [RCA_OC] 3-129
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θ is the phase angle between polarized voltage and current The power value is calculated as below: P=U×[I×COS(θ-φ)] 1.
If P>0, the current direction polarized by U is forward direction
2.
If P0, the direction of zero /negative-sequence current is reverse direction
If P [50/51Px.I_Set]
Equation 3.13-1
Where: Ip is measured phase current. [50/51Px.I_Set] is the current setting of stage x (x=1, 2, 3, or 4) of overcurrent element. 3.13.2.3 Direction Control Element Please refer to section 3.10 for details. 3.13.2.4 Harmonic Blocking Element When phase overcurrent protection is used to protect feeder-transformer circuits harmonic blocking function can be selected for each stage of phase overcurrent element by configuring logic setting [50/51Px.En_Hm2_Blk] (x=1, 2, 3 or 4) to prevent maloperation due to inrush current. When the percentage of second harmonic component to fundamental component of any phase current is greater than the setting [50/51P.K_Hm2], harmonic blocking element operates to block stage x overcurrent element if corresponding logic setting [50/51Px.En_Hm2_Blk] enabled. Operation criterion: Equation 3.13-2
Where: is second harmonic of phase current
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is fundamental component of phase current. [50/51P.K_Hm2] is harmonic blocking coefficient. If fundamental component of any phase current is lower than the minimum operating current (0.1In), then harmonic calculation is not carried out and harmonic blocking element does not operate. 3.13.2.5 Characteristic Curve All stages can be selected as definite-time or inverse-time characteristic, inverse-time operating characteristic is as follows.
Equation 3.13-3
Where: Iset is current setting [50/51Px.I_Set]. Tp is time multiplier setting [50/51Px.TMS]. α is a constant. K is a constant. C is a constant. I is measured phase current from line CT The user can select the operating characteristic from various inverse-time characteristic curves by setting [50/51Px.Opt_Curve], and parameters of available characteristics for selection are shown in the following table. Table 3.13-1 Inverse-time curve parameters 50/51Px.Opt_Curve
α
K
Time Characteristic
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
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α
K
Time Characteristic
C
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
UserDefine
Programmable user-defined
If all available curves do not comply with user application, user may set [50/51Px.Opt_Curve] as “UserDefine” to customize the inverse-time curve characteristic with constants α, K and C. (only stage 1) When inverse-time characteristic is selected, if calculated operating time is less than setting [50/51Px.tmin], then the operating time of the protection changes to the value of setting [50/51Px.tmin] automatically. Define-time or inverse-time phase overcurrent protection drops off instantaneously after fault current disappears.
3.13.3 Function Block Diagram 50/51Px 50/51Px.En1
50/51Px.On
50/51Px.En2
50/51Px.StA
50/51Px.Blk
50/51Px.StB 50/51Px.StC 50/51Px.St 50/51Px.Op
3.13.4 I/O Signals Table 3.13-2 I/O signals of phase overcurrent protection No.
Input Signal
1
50/51Px.En1
2
50/51Px.En2
3
50/51Px.Blk
No.
Description Stage x of phase overcurrent protection enabling input 1, it is triggered from binary input or programmable logic etc. Stage x of phase overcurrent protection enabling input 2, it is triggered from binary input or programmable logic etc. Stage x of phase overcurrent protection blocking input, it is triggered from binary input or programmable logic etc.
Output Signal
Description
1
50/51Px.On
Stage x of phase overcurrent protection is enabled.
2
50/51Px.Op
Stage x of phase overcurrent protection operates.
3
50/51Px.St
Stage x of phase overcurrent protection starts.
4
50/51Px.StA
Stage x of phase overcurrent protection starts (A-Phase).
5
50/51Px.StB
Stage x of phase overcurrent protection starts (B-Phase).
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50/51Px.StC
Stage x of phase overcurrent protection starts (C-Phase).
3.13.5 Logic EN
[50/51Px.En]
SIG
50/51Px.En1
SIG
50/51Px.En2
SIG
50/51Px.Blk
SET
Ia>[50/51Px.I_Set]
& & 50/51Px.On
>=1 50/51Px.St & 50/51Px.StA
SET
Ib>[50/51Px.I_Set]
& 50/51Px.StB
SET
Ic>[50/51Px.I_Set]
& 50/51Px.StC
SET
[50/51Px.Opt_Dir]=Forward
SIG
Forward DIR
SET
[50/51Px.Opt_Dir]=Reverse
SIG
Reverse DIR
SIG
VTS.Alm
EN
[50/51Px.En_VTS_Blk]
SET
[50/51Px.Opt_Dir]=Non-Directional
SIG
I3P
SET
[50/51Px.En_Hm2_Blk]
SIG
50/51Px.On
SIG
FD.Pkp
SET
[50/51Px.Opt_Curve]=DefTime
&
&
>=1 >=1
&
2nd Hm Detect
&
&
&
& [50/51Px.t_Op]
0
>=1 50/51Px.Op
& SIG
Timer t
50/51Px.St
Figure 3.13-1 Logic diagram of phase overcurrent protection
x=1, 2, 3, 4
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3.13.6 Settings Table 3.13-3 Settings of phase overcurrent protection No.
Name
Range
Step
Unit
Remark Setting
1
50/51P.K_Hm2
0.000~1.000
0.001
of
component
second for
harmonic
blocking
phase
overcurrent elements 2
50/51P1.I_Set
(0.050~30.000)×In
0.001
A
3
50/51P1.t_Op
0.000~20.000
0.001
s
Current setting for stage 1 of phase overcurrent protection Time delay for stage 1 of phase overcurrent protection Enabling/disabling stage 1 of phase
4
50/51P1.En
overcurrent protection
0 or 1
0: disable 1: enable Enabling/Disabling
auto-reclosing
blocked when stage 1 of phase 5
50/51P1.En_BlkAR
0 or 1
overcurrent protection operates 0: disable 1: enable Enabling/Disabling stage 1 of phase overcurrent protection is blocked by
6
50/51P1.En_VTS_Blk
0 or 1
VT circuit failure 0: disable 1: enable
Non-Directional 7
50/51P1.Opt_Dir
Direction option for stage 1 of phase
Forward
overcurrent protection
Reverse
Enabling/disabling second harmonic blocking for stage 1 of phase 8
50/51P1.En_Hm2_Blk
0 or 1
overcurrent protection 0: disable 1: enable
DefTime IECN IECV IECE 9
50/51P1.Opt_Curve
IECST
Option of characteristic curve for
IECLT
stage
ANSIE
protection
1
of
phase
overcurrent
ANSIV ANSI ANSIM ANSILTE 3-139
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Name
Range
Step
Unit
Remark
ANSILTV ANSILT UserDefine Time multiplier setting for stage 1 of 10
50/51P1.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection Minimum operating time for stage 1 11
50/51P1.tmin
0.000~20.000
0.001
s
of inverse-time phase overcurrent protection Constant
12
50/51P1.Alpha
0.010~5.000
“α”
for
stage
customized
0.001
1
of
inverse-time
characteristic
phase
overcurrent
protection Constant 13
50/51P1.C
0.000~20.000
“C”
for
stage
customized
0.001
1
of
inverse-time
characteristic
phase
overcurrent
protection Constant 14
50/51P1.K
0.050~20.000
“K”
for
stage
customized
0.001
characteristic
1
of
inverse-time phase
overcurrent
protection 15
50/51P2.I_Set
(0.050~30.000)×In
0.001
A
16
50/51P2.t_Op
0.000~20.000
0.001
s
Current setting for stage 2 of phase overcurrent protection Time delay for stage 2 of phase overcurrent protection Enabling/disabling stage 2 of phase
17
50/51P2.En
overcurrent protection
0 or 1
0: disable 1: enable Enabling/Disabling
auto-reclosing
blocked when stage 2 of phase 18
50/51P2.En_BlkAR
0 or 1
overcurrent protection operates 0: disable 1: enable Enabling/Disabling stage 2 of phase overcurrent protection is blocked by
19
50/51P2.En_VTS_Blk
0 or 1
VT circuit failure 0: disable 1: enable
Non-Directional 20
50/51P2.Opt_Dir
Direction option for stage 2 of phase
Forward
overcurrent protection
Reverse 21
50/51P2.En_Hm2_Blk
0 or 1
Enabling/disabling second harmonic
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Name
Range
Step
Unit
Remark blocking for stage 2 of phase overcurrent protection 0: disable 1: enable
DefTime IECN IECV IECE IECST 22
50/51P2.Opt_Curve
IECLT
Option of characteristic curve for
ANSIE
stage
ANSIV
protection
2
of
phase
overcurrent
ANSI ANSIM ANSILTE ANSILTV ANSILT Time multiplier setting for stage 2 of 23
50/51P2.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection. Minimum operating time for stage 2 24
50/51P2.tmin
0.000~20.000
0.001
s
of inverse-time phase overcurrent protection
25
50/51P3.I_Set
(0.050~30.000)×In
0.001
A
26
50/51P3.t_Op
0.000~20.000
0.001
s
Current setting for stage 3 of phase overcurrent protection Time delay for stage 3 of phase overcurrent protection Enabling/disabling stage 3 of phase
27
50/51P3.En
overcurrent protection
0 or 1
0: disable 1: enable Enabling/Disabling
auto-reclosing
blocked when stage 3 of phase 28
50/51P3.En_BlkAR
0 or 1
overcurrent protection operates 0: disable 1: enable Enabling/Disabling stage 3 of phase overcurrent protection is blocked by
29
50/51P3.En_VTS_Blk
0 or 1
VT circuit failure 0: disable 1: enable
30
50/51P3.Opt_Dir
Non-Directional
Direction option for stage 3 of phase
Forward
overcurrent protection 3-141
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Name
Range
Step
Unit
Remark
Reverse Enabling/disabling second harmonic blocking for stage 3 of phase 31
50/51P3.En_Hm2_Blk
0 or 1
overcurrent protection 0: disable 1: enable
DefTime IECN IECV IECE IECST 32
50/51P3.Opt_Curve
IECLT
Option of characteristic curve for
ANSIE
stage
ANSIV
protection
3
of
phase
overcurrent
ANSI ANSIM ANSILTE ANSILTV ANSILT Time multiplier setting for stage 3 of 33
50/51P3.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection. Minimum operating time for stage 3 34
50/51P3.tmin
0.000~20.000
0.001
s
of inverse-time phase overcurrent protection
35
50/51P4.I_Set
(0.050~30.000)×In
0.001
A
36
50/51P4.t_Op
0.000~20.000
0.001
s
Current setting for stage 4 of phase overcurrent protection Time delay for stage 4 of phase overcurrent protection Enabling/disabling stage 4 of phase
37
50/51P4.En
overcurrent protection
0 or 1
0: disable 1: enable Enabling/Disabling
auto-reclosing
blocked when stage 4 of phase 38
50/51P4.En_BlkAR
0 or 1
overcurrent protection operates 0: disable 1: enable Enabling/Disabling stage 4 of phase overcurrent protection is blocked by
39
50/51P4.En_VTS_Blk
0 or 1
VT circuit failure 0: disable 1: enable
3-142
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Name
Range
Step
Unit
Non-Directional 40
50/51P4.Opt_Dir
Remark Direction option for stage 4 of phase
Forward
overcurrent protection
Reverse
Enabling/disabling second harmonic blocking for stage 4 of phase 41
50/51P4.En_Hm2_Blk
0 or 1
overcurrent protection 0: disable 1: enable
DefTime IECN IECV IECE IECST 42
50/51P4.Opt_Curve
IECLT
Option of characteristic curve for
ANSIE
stage
ANSIV
protection
4
of
phase
overcurrent
ANSI ANSIM ANSILTE ANSILTV ANSILT Time multiplier setting for stage 4 of 43
50/51P4.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection. Minimum operating time for stage 4 44
50/51P4.tmin
0.010~20.000
0.001
s
of inverse-time phase overcurrent protection
3.14 Earth Fault Protection 3.14.1 General Application During normal operation of power system, there is trace residual current, whereas a fault current flows to earth will result in greater residual current. Therefore, residual current is adopted for the calculation of earth fault protection. In order to improve the selectivity of earth fault protection in power grid with multiple power sources, directional element can be selected to control earth fault protection. For application on line-transformer unit, second harmonic also can be selected to block earth fault protection to avoid the effect of sympathetic current on the protection.
3.14.2 Function Description Earth fault protection has following functions: 1.
Four-stage earth fault protection with independent logic, current and time delay settings. 3-143
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2.
All stages can be selected as definite-time or inverse-time characteristic. The inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics, and a user-defined inverse-time curve is available for stage 1 of earth fault protection.
3.
Directional element can be selected to control each stage of earth fault protection with three options: no direction, forward direction and reverse direction.
4.
Second harmonic can be selected to block each stage of earth fault protection.
5.
Stage 2, 3, 4 of earth fault protection can enable short time delay to improve operation speed.
3.14.2.1 Overview Earth fault protection consists of following three elements: 1.
Overcurrent element: each stage equipped with one independent overcurrent element.
2.
Directional control element: one direction control element shared by all overcurrent elements, and each overcurrent element can individually select protection direction.
3.
Harmonic blocking element: one harmonic blocking element shared by all overcurrent elements and each overcurrent element can individually enable the output signal of harmonic blocking element as a blocking input.
3.14.2.2 Zero-sequence Overcurrent Element The operation criterion for each stage of earth fault protection is: 3I0>[50/51Gx.3I0_Set]
Equation 3.14-1
Where: 3I0 is the calculated residual current. [50/51Gx.3I0_Set] is the current setting of stage x (x=1, 2, 3, or 4) of earth fault protection. 3.14.2.3 Direction Control Element Please refer to section 3.10 for details. 3.14.2.4 Harmonic Blocking Element In order to prevent effects of inrush current on earth fault protection, harmonic blocking function can be selected for each stage of earth fault element by configuring logic setting [50/51Gx.En_Hm2_Blk] (x=1, 2, 3 or 4). When the percentage of second harmonic component to fundamental component of residual current is greater than the setting [50/51G.K_Hm2], harmonic blocking element operates to block stage x of earth fault protection if corresponding logic setting [50/51Gx.En_Hm2_Blk] is enabled Operation criterion: Equation 3.14-2
3-144
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Where: is second harmonic of residual current
is fundamental component of residual current. [50/51G.K_Hm2] is harmonic blocking coefficient. If fundamental component of residual current is lower than the minimum operating current (0.1In) then harmonic calculation is not carried out and harmonic blocking element does not operate. 3.14.2.5 Characteristic Curve All 4 stages earth fault protection can be selected as definite-time or inverse-time characteristic, and inverse-time operating time curve is as follows.
Equation 3.14-3
Where: Iset is residual current setting [50/51Gx.3I0_Set]. Tp is time multiplier setting [50/51Gx.TMS]. K is a constant C is a constant. α is a constant. 3I0 is the calculated residual current. The user can select the operating characteristic from various inverse-time characteristic curves by setting [50/51Gx.Opt_Curve], and parameters of available characteristics for selection are shown in the following table. Table 3.14-1 Inverse-time curve parameters 50/51Gx.Opt_Curve
Time Characteristic
α
K
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
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α
K
Time Characteristic
C
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
UserDefine
Programmable User-defined
If all available curves do not comply with user application, user may set [50/51Gx.Opt_Curve] as “UserDefine” to customize the inverse-time curve characteristic, and constants K, α and C with configuration tool software. (only stage 1) When inverse-time characteristic is selected, if calculated operating time is less than setting [50/51Gx.tmin], then the operating time of the protection changes to the value of setting [50/51Gx.tmin] automatically. Define-time or inverse-time directional earth-fault protection drops off instantaneously after fault current disappears.
3.14.3 Function Block Diagram 50/51Gx 50/51Gx.En1
50/51Gx.On
50/51Gx.En2
50/51Gx.On_ShortDly
50/51Gx.Blk
50/51Gx.St
50/51Gx.En_ShortDly
50/51Gx.Op
50/51Gx.Blk_ShortDly
3.14.4 I/O Signals Table 3.14-2 I/O signals of earth fault protection No.
Input Signal
1
50/51Gx.En1
2
50/51Gx.En2
3
50/51Gx.Blk
4
50/51Gx.En_ShortDly
5
50/51Gx.Blk_ShortDly
No.
Output Signal
Description Stage x of earth fault protection enabling input 1, it is triggered from binary input or programmable logic etc. (x=1, 2, 3, 4) Stage x of earth fault protection enabling input 2, it is triggered from binary input or programmable logic etc. (x=1, 2, 3, 4) Stage x of earth fault protection blocking input, it is triggered from binary input or programmable logic etc. (x=1, 2, 3, 4) Short time delay for stage x of earth fault protection enabling input, it is triggered from binary input or programmable logic etc. (x=2, 3, 4) Short time delay for stage x of earth fault protection blocking input, it is triggered from binary input or programmable logic etc. (x=2, 3, 4) Description
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50/51Gx.On
Stage x of earth fault protection is enabled. (x=1, 2, 3, 4)
2
50/51Gx.On_ShortDly
Short time delay for stage x of earth fault protection is enabled. (x=2, 3, 4)
3
50/51Gx.St
Stage x of earth fault protection starts. (x=1, 2, 3, 4)
4
50/51Gx.Op
Stage x of earth fault protection operates. (x=1, 2, 3, 4)
3.14.5 Logic EN
[50/51G1.En]
SIG
50/51G1.En1
SIG
50/51G1.En2
SIG
50/51G1.Blk
SIG
FD.Pkp
SET
3I0>[50/51G1.3I0_Set]
EN
[50/51G1.En_Abnor_Blk]
SIG
No abnormal conditions
& & 50/51G1.On
&
>=1
&
SET
[50/51G1.Opt_Dir]=Forward
&
&
& 50/51G1.St
&
SIG
Forward DIR
SET
[50/51G1.Opt_Dir]=Reverse
SIG
Reverse DIR
SET
[50/51G1.Opt_Dir]=Non_Directional
SIG
CTS.Alm
EN
[50/51G1.En_CTS_Blk]
SIG
I3P
SET
[50/51G1.En_Hm2_Blk]
SIG
50/51G1.St
>=1 &
>=1
& >=1 2nd Hm Detect
&
&
Timer t
>=1
&
50/51G1.Op [50/51G1.t_Op]
SET
0
[50/51G1.Opt_Curve]=DefTime
Figure 3.14-1 Logic diagram of earth fault protection (stage 1)
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[50/51Gx.En_ShortDly]
SIG
50/51Gx.En_ShortDly
SIG
50/51Gx.Blk_ShortDly
EN
[50/51Gx.En]
SIG
50/51Gx.En1
SIG
50/51Gx.En2
SIG
50/51Gx.Blk
SIG
FD.Pkp
SET
3I0>[50/51Gx.3I0_Set]
EN
[50/51Gx.En_Abnor_Blk]
SIG
No abnormal conditions
& 50/51Gx.On_ShortDly
& & 50/51Gx.On
&
>=1
&
SET
[50/51Gx.Opt_Dir]=Forward
&
&
SIG
Forward DIR
SET
[50/51Gx.Opt_Dir]=Reverse
SIG
Reverse DIR
SET
[50/51Gx.Opt_Dir]=Non_Directional
SIG
CTS.Alm
EN
[50/51Gx.En_CTS_Blk]
SIG
I3P
SET
[50/51Gx.En_Hm2_Blk]
SIG
50/51Gx.St
>=1 &
>=1
& >=1 2nd Hm Detect
&
&
Timer t
& SET
& 50/51Gx.St
&
>=1 [50/51Gx.t_Op]
0
[50/51Gx.t_ShortDly]
0
50/51Gx.Op
[50/51Gx.Opt_Curve]=DefTime
& SIG
50/51Gx.On_ShortDly
Figure 3.14-2 Logic diagram of earth fault protection (stage x)
x=2, 3, 4 3-148
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Abnormal condition 1: when the system is under pole disagreement condition, for 1-pole AR, earth fault protection will operate. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “1”, the stage x of earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “0”, earth fault protection is not controlled by direction element. Abnormal condition 2: When manually closing circuit breaker, three phases of the circuit breaker maybe not operate simultaneously, and SOTF protection should operate. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “1”, the stage x of earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “0”, earth fault protection is not controlled by direction element. Abnormal condition 3: VT circuit failure. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “1”, the stage x of earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “0”, earth fault protection is not controlled by direction element.
3.14.6 Settings Table 3.14-3 Settings of earth fault protection No.
Name
Range
Step
Unit
Remark Setting
1
50/51G.K_Hm2
0.000~1.000
0.001
of
second
harmonic
component for blocking earth fault elements
2
50/51G1.3I0_Set
(0.050~30.000)×In
0.001
A
3
50/51G1.t_Op
0.000~20.000
0.001
s
Current setting for stage 1 of earth fault protection Time delay for stage 1 of earth fault protection Enabling/disabling stage 1 of
4
50/51G1.En
earth fault protection
0 or 1
0: disable 1: enable Enabling/Disabling auto-reclosing blocked when stage 1 of earth
5
50/51G1.En_BlkAR
0 or 1
fault protection operates 0: disable 1: enable
Non_Directional 6
50/51G1.Opt_Dir
Forward
Direction option for stage 1 of earth fault protection
Reverse
Enabling/disabling
second
harmonic blocking for stage 1 of 7
50/51G1.En_Hm2_Blk
0 or 1
earth fault protection 0: disable 1: enable
8
50/51G1.En_Abnor_Blk
Enabling/disabling blocking for
0 or 1
stage 1 of earth fault protection
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Name
Range
Step
Unit
Remark under abnormal conditions 0: disable 1: enable Enabling/disabling blocking for stage 1 of earth fault protection
9
50/51G1.En_CTS_Blk
0 or 1
under CT failure conditions 0: disable 1: enable
DefTime IECN IECV IECE IECST IECLT 10
50/51G1.Opt_Curve
ANSIE
Option of characteristic curve for
ANSIV
stage 1 of earth fault protection
ANSI ANSIM ANSILTE ANSILTV ANSILT UserDefine Time multiplier setting for stage 1 11
50/51G1.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection Minimum operating time for stage 12
50/51G1.tmin
0.050~20.000
0.001
s
1 of inverse-time earth fault protection Constant “α” for stage 1 of
13
50/51G1.Alpha
0.010~5.000
customized
0.001
characteristic
inverse-time earth
fault
protection Constant “C” for stage 1 of 14
50/51G1.C
0.000~20.000
customized
0.001
characteristic
inverse-time earth
fault
protection Constant “K” for stage 1 of 15
50/51G1.K
0.050~20.000
customized
0.001
characteristic
inverse-time earth
fault
protection 16
50/51G2.3I0_Set
(0.050~30.000)×In
0.001
A
17
50/51G2.t_Op
0.000~20.000
0.001
s
3-150
Current setting for stage 2 of earth fault protection Time delay for stage 2 of earth PCS-931 Line Differential Relay
Date: 2015-10-22
3 Operation Theory No.
Name
Range
Step
Unit
Remark fault protection
18
50/51G2.t_ShortDly
0.000~20.000
0.001
s
Short time delay for stage 2 of earth fault protection Enabling/disabling stage 2 of
19
50/51G2.En
earth fault protection
0 or 1
0: disable 1: enable Enabling/disabling
short
time
delay for stage 2 of earth fault 20
50/51G2.En_ShortDly
0 or 1
protection 0: disable 1: enable Enabling/Disabling auto-reclosing blocked when stage 2 of earth
21
50/51G2.En_BlkAR
0 or 1
fault protection operates 0: disable 1: enable
Non_Directional 22
50/51G2.Opt_Dir
Forward
Direction option for stage 2 of earth fault protection
Reverse
Enabling/disabling
second
harmonic blocking for stage 2 of 23
50/51G2.En_Hm2_Blk
0 or 1
earth fault protection 0: disable 1: enable Enabling/disabling blocking for stage 2 of earth fault protection
24
50/51G2.En_Abnor_Blk
0 or 1
under abnormal conditions 0: disable 1: enable Enabling/disabling blocking for stage 2 of earth fault protection
25
50/51G2.En_CTS_Blk
0 or 1
under CT failure conditions 0: disable 1: enable
DefTime IECN IECV 26
50/51G2.Opt_Curve
IECE
Option of characteristic curve for
IECST
stage 2 of earth fault protection
IECLT ANSIE ANSIV 3-151
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Name
Range
Step
Unit
Remark
ANSI ANSIM ANSILTE ANSILTV ANSILT Time multiplier setting for stage 2 27
50/51G2.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection Minimum operating time for stage 28
50/51G2.tmin
0.050~20.000
0.001
s
2 of inverse-time earth fault protection
29
50/51G3.3I0_Set
(0.050~30.000)×In
0.001
A
30
50/51G3.t_Op
0.000~20.000
0.001
s
31
50/51G3.t_ShortDly
0.000~20.000
0.001
s
Current setting for stage 3 of earth fault protection Time delay for stage 3 of earth fault protection Short time delay for stage 3 of earth fault protection Enabling/disabling stage 3 of
32
50/51G3.En
earth fault protection
0 or 1
0: disable 1: enable Enabling/disabling
short
time
delay for stage 3 of earth fault 33
50/51G3.En_ShortDly
0 or 1
protection 0: disable 1: enable Enabling/Disabling auto-reclosing blocked when stage 3 of earth
34
50/51G3.En_BlkAR
0 or 1
fault protection operates 0: disable 1: enable
Non_Directional 35
50/51G3.Opt_Dir
Forward
Direction option for stage 3 of earth fault protection
Reverse
Enabling/disabling
second
harmonic blocking for stage 3 of 36
50/51G3.En_Hm2_Blk
0 or 1
earth fault protection 0: disable 1: enable Enabling/disabling blocking for
37
50/51G3.En_Abnor_Blk
stage 3 of earth fault protection
0 or 1
under abnormal conditions 0: disable
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Name
Range
Step
Unit
Remark 1: enable Enabling/disabling blocking for stage 3 of earth fault protection
38
50/51G3.En_CTS_Blk
0 or 1
under CT failure conditions 0: disable 1: enable
DefTime IECN IECV IECE IECST IECLT 39
50/51G3.Opt_Curve
Option of characteristic curve for
ANSIE
stage 3 of earth fault protection
ANSIV ANSI ANSIM ANSILTE ANSILTV ANSILT
Time multiplier setting for stage 3 40
50/51G3.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection Minimum operating time for stage 41
50/51G3.tmin
0.050~20.000
0.001
s
3 of inverse-time earth fault protection
42
50/51G4.3I0_Set
(0.050~30.000)×In
0.001
A
43
50/51G4.t_Op
0.000~20.000
0.001
s
44
50/51G4.t_ShortDly
0.000~20.000
0.001
s
Current setting for stage 4 of earth fault protection Time delay for stage 4 of earth fault protection Short time delay for stage 4 of earth fault protection Enabling/disabling stage 4 of
45
50/51G4.En
earth fault protection
0 or 1
0: disable 1: enable Enabling/disabling
short
time
delay for stage 4 of earth fault 46
50/51G4.En_ShortDly
0 or 1
protection 0: disable 1: enable Enabling/Disabling auto-reclosing
47
50/51G4.En_BlkAR
0 or 1
blocked when stage 4 of earth fault protection operates 3-153
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Name
Range
Step
Unit
Remark 0: disable 1: enable
Non_Directional 48
50/51G4.Opt_Dir
Direction option for stage 4 of
Forward
earth fault protection
Reverse
Enabling/disabling
second
harmonic blocking for stage 4 of 49
50/51G4.En_Hm2_Blk
0 or 1
earth fault protection 0: disable 1: enable Enabling/disabling blocking for stage 4 of earth fault protection
50
50/51G4.En_Abnor_Blk
0 or 1
under abnormal conditions 0: disable 1: enable Enabling/disabling blocking for stage 4 of earth fault protection
51
50/51G4.En_CTS_Blk
0 or 1
under CT failure conditions 0: disable 1: enable
DefTime IECN IECV IECE IECST IECLT 52
50/51G4.Opt_Curve
Option of characteristic curve for
ANSIE
stage 4 of earth fault protection
ANSIV ANSI ANSIM ANSILTE ANSILTV ANSILT
Time multiplier setting for stage 4 53
50/51G4.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection Minimum operating time for stage 54
50/51G4.tmin
0.050~20.000
0.001
s
4 of inverse-time earth fault protection
3-154
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3.15 Negative-sequence Overcurrent Protection 3.15.1 General Application When an asymmetric short-circuit fault happens to the power system or the power system is under asymmetrical three-phase operation, the power system will generate negative-sequence current. Negative-sequence overcurrent will cause generator, motor and other equipments serious damage, so negative-sequence overcurrent protection is used to prevent them. In order to make negative-sequence overcurrent protection own selectivity in multiplex power supply system, negative-sequence overcurrent protection can be controlled by direction control element.
3.15.2 Function Description Negative-sequence overcurrent has following functions: 1.
Four-stage negative-sequence overcurrent protection with independent logic, current and time delay settings.
2.
Each stage can be selected to block AR by the setting and stage 3 of negative-sequence overcurrent protection can be selected to operate to trip or alarm.
3.
All stages can be selected as definite-time or inverse-time characteristic. The inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics, and a user-defined inverse-time curve is available for stage 1 of negative-sequence overcurrent protection.
4.
Directional element can be selected to control each stage of negative-sequence overcurrent protection with three options: no direction, forward direction and reverse direction.
5.
CT circuit failure can be selected to block each stage of negative-sequence overcurrent protection.
6.
Each stage can select independent releasing threshold based on the ratio of negative-sequence current to positive-sequence current to prevent negative-sequence overcurrent protection from undesired operation for three-phase fault with asymmetrical position exchange of three-phase.
3.15.2.1 Overview Negative-sequence overcurrent protection consists of following three elements: 1.
Fault detector: each stage is controlled by the fault detector based on negative-sequence current. Negative-sequence overcurrent protection can operate when the fault detector based on negative-sequence current operate and it is enabled.
2.
Overcurrent element: each stage is equipped with one independent overcurrent element.
3.
Directional control element: one direction control element is shared by all overcurrent elements, and each overcurrent element can individually select protection direction.
4.
Ratio element: each stage is equipped with one independent ratio element (I2/I1), usually the same setting is applied for all stages. 3-155
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3.15.2.2 Negative-sequence Overcurrent Element The operation criterion for each stage of negative-sequence overcurrent protection is: I2>[50/51Qx.I2_Set] &
Equation 3.15-1
I2/I1>[50/51Qx.I2/I1_Set] Where: I2 is the calculated negative-sequence current. I1 is the calculaged positive-sequence current. [50/51Qx.I2_Set] is the current setting of stage x (x=1, 2, 3 or 4) of negative-sequence overcurrent protection. 3.15.2.3 Direction Control Element Please refer to section 3.10 for details. 3.15.2.4 Characteristic Curve All 4 stages negative-sequence overcurrent protection can be selected as definite-time or inverse-time characteristic, and inverse-time operating time curve is as follows.
Equation 3.15-2
Where: Iset is negative-sequence curren setting [50/51Qx.I2_Set]. Tp is time multiplier setting [50/51Qx.TMS]. K is a constant C is a constant. α is a constant. I2 is the calculated negative-sequence current. The user can select the operating characteristic from various inverse-time characteristic curves by setting [50/51Qx.Opt_Curve], and parameters of available characteristics for selection are shown in the following table. Table 3.15-1 Inverse-time curve parameters 50/51Gx.Opt_Curve DefTime
Time Characteristic
K
α
C
Definite time
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α
K
Time Characteristic
C
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
UserDefine
Programmable User-defined
If all available curves do not comply with user application, user may set [50/51Qx.Opt_Curve] as “UserDefine” to customize the inverse-time curve characteristic, and constants K, α and C with configuration tool software. (only stage 1) When inverse-time characteristic is selected, if calculated operating time is less than setting [50/51Qx.tmin], then the operating time of the protection changes to the value of setting [50/51Qx.tmin] automatically. Define-time or inverse-time directional negative-sequence overcurrent protection drops off instantaneously after fault current disappears.
3.15.3 Function Block Diagram 50/51Qx 50/51Gx.En1
50/51Qx.On
50/51Gx.En2
50/51Qx.St
50/51Qx.Blk
50/51Qx.Op 50/51Q4.Alm
3.15.4 I/O Signals Table 3.15-2 I/O signals of negative-sequence overcurrent protection No.
Input Signal
1
50/51Qx.En1
2
50/51Qx.En2
Description Stage x of negative-sequence overcurrent protection enabling input 1, it is triggered from binary input or programmable logic etc. (x=1, 2, 3, 4) Stage x of negative-sequence overcurrent protection enabling input 2, it is triggered from binary input or programmable logic etc. (x=1, 2, 3, 4)
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50/51Qx.Blk
Stage x of negative-sequence overcurrent protection blocking input, it is triggered from binary input or programmable logic etc. (x=1, 2, 3, 4)
Output Signal
Description
1
50/51Qx.On
Stage x of negative-sequence overcurrent protection is enabled. (x=1, 2, 3, 4)
2
50/51Qx.St
Stage x of negative-sequence overcurrent protection starts. (x=1, 2, 3, 4)
3
50/51Qx.Op
Stage x of negative-sequence overcurrent protection operates. (x=1, 2, 3, 4)
4
50/51Q4.Alm
Stage 4 of negative-sequence overcurrent protection operates to alarm.
3.15.5 Logic EN
[50/51Qx.En]
SIG
50/51Qx.En1
SIG
50/51Qx.En2
SIG
50/51Qx.Blk
SET
I2/I1>[50/51Qx.I2/I1_Set]
SET
I2>[50/51Qx.I2_Set]
EN
[50/51Qx.En_Abnor_Blk]
SIG
No abnormal conditions
& & 50/51Qx.On
&
>=1 &
&
& 50/51Qx.St Timer t
&
50/51Qx.Op
t
SET
[50/51Qx.Opt_Dir]=Forward
SIG
Forward DIR
SET
[50/51Qx.Opt_Dir]=Reverse
SIG
Reverse DIR
SET
[50/51Qx.Opt_Dir]=Non_Directional
SIG
CTS.Alm
EN
[50/51Qx.En_CTS_Blk]
SIG
FD.NOC.Pkp
& >=1 &
>=1
&
Figure 3.15-1 Logic diagram of negative-sequence overcurrent protection
x=1, 2 or 3 Abnormal condition 1: when the system is under pole disagreement condition, for 1-pole AR, negative-sequence overcurrent protection will operate. If the logic setting [50/51Qx.En_Abnor_Blk] is set as “1”, the stage x of negative-sequence overcurrent protection will be blocked. If the logic setting [50/51Qx.En_Abnor_Blk] is set as “0”, negative-sequence overcurrent protection is not controlled by direction element. Abnormal condition 2: When manually closing circuit breaker, three phases of the circuit breaker maybe not operate simultaneously, and SOTF protection should operate. If the logic setting 3-158
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[50/51Qx.En_Abnor_Blk] is set as “1”, the stage x of negative-sequence overcurrent protection will be blocked. If the logic setting [50/51Qx.En_Abnor_Blk] is set as “0”, negative-sequence overcurrent protection is not controlled by direction element. Abnormal condition 3: VT circuit failure. If the logic setting [50/51Qx.En_Abnor_Blk] is set as “1”, the stage x of negative-sequence overcurrent protection will be blocked. If the logic setting [50/51Qx.En_Abnor_Blk] is set as “0”, negative-sequence overcurrent protection is not controlled by direction element. EN
[50/51Q4.En]
SIG
50/51Q4.En1
SIG
50/51Q4.En2
SIG
50/51Q4.Blk
SET
I2/I1>[50/51Q4.I2/I1_Set]
SET
I2>[50/51Q4.I2_Set]
EN
[50/51Q4.En_Abnor_Blk]
SIG
No abnormal conditions
& & 50/51Q4.On
&
>=1 &
&
& 50/51Q4.St
&
SET
[50/51Q4.Opt_Dir]=Forward
SIG
Forward DIR
SET
[50/51Q4.Opt_Dir]=Reverse
SIG
Reverse DIR
SET
[50/51Q4.Opt_Dir]=Non_Directional
SIG
CTS.Alm
EN
[50/51Q4.En_CTS_Blk]
SIG
FD.NOC.Pkp
EN
[50/51Q4.En_Trp]
& >=1 &
>=1
Timer t
&
50/51Q4.Alm
t
&
Timer t
&
50/51Q4.Op
t
Figure 3.15-2 Logic diagram of stage 4 of negative-sequence overcurrent protection
3.15.6 Settings Table 3.15-3 Settings of negative-sequence overcurrent protection No.
Name
Range
Step
Unit
Remark Current setting for stage 1 of
1
50/51Q1.I2_Set
(0.050~30.000)×In
0.001
A
negative-sequence
overcurrent
protection 2
50/51Q1.I2/I1_Set
0.00~1.00
0.01
Ratio coefficient (I2/I1) for stage 1 of negative-sequence overcurrent 3-159
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Name
Range
Step
Unit
Remark protection Time
3
50/51Q1.t_Op
0.000~20.000
0.001
s
delay
for
stage
negative-sequence
1
of
overcurrent
protection Enabling/disabling
stage 1
negative-sequence 4
50/51Q1.En
0 or 1
of
overcurrent
protection 0: disable 1: enable Enabling/Disabling auto-reclosing blocked
5
50/51Q1.En_BlkAR
when
stage
negative-sequence
0 or 1
1
of
overcurrent
protection operates 0: disable 1: enable
6
50/51Q1.Opt_Dir
Non_Directional
Direction option for stage 1 of
Forward
negative-sequence
Reverse
protection Enabling/disabling
overcurrent
blocking
for
stage 1 of negative-sequence 7
50/51Q1.En_Abnor_Blk
overcurrent
0 or 1
protection
under
abnormal conditions 0: disable 1: enable Enabling/disabling
blocking
for
stage 1 of negative-sequence 8
50/51Q1.En_CTS_Blk
overcurrent protection under CT
0 or 1
failure conditions 0: disable 1: enable
DefTime IECN IECV IECE IECST 9
50/51Q1.Opt_Curve
IECLT
Option of characteristic curve for
ANSIE
stage 1 of negative-sequence
ANSIV
overcurrent protection
ANSI ANSIM ANSILTE ANSILTV ANSILT
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Name
Range
Step
Unit
Remark
UserDefine Time multiplier setting for stage 1 10
50/51Q1.TMS
0.010~200.000
of
0.001
inverse-time
negative-sequence
overcurrent
protection Minimum operating time for stage 11
50/51Q1.tmin
0.050~20.000
0.001
s
1
of
inverse-time
negative-sequence
overcurrent
protection Constant “α” for stage 1 of 12
50/51Q1.Alpha
0.010~5.000
customized
0.001
inverse-time
characteristic negative-sequence overcurrent protection Constant “C” for stage 1 of
13
50/51Q1.C
0.000~20.000
customized
0.001
inverse-time
characteristic negative-sequence overcurrent protection Constant “K” for stage 1 of
14
50/51Q1.K
0.050~20.000
customized
0.001
inverse-time
characteristic negative-sequence overcurrent protection Current setting for stage 2 of
15
50/51Q2.I2_Set
(0.050~30.000)×In
0.001
A
negative-sequence
overcurrent
protection Ratio coefficient (I2/I1) for stage 2 16
50/51Q2.I2/I1_Set
0.00~1.00
0.01
of negative-sequence overcurrent protection Time
17
50/51Q2.t_Op
0.000~20.000
0.001
s
delay
for
stage
negative-sequence
2
of
overcurrent
protection Enabling/disabling
stage 2
negative-sequence 18
50/51Q2.En
0 or 1
of
overcurrent
protection 0: disable 1: enable Enabling/Disabling auto-reclosing blocked
19
50/51Q2.En_BlkAR
when
stage
negative-sequence
0 or 1
2
of
overcurrent
protection operates 0: disable 1: enable
20
50/51Q2.Opt_Dir
Non_Directional
Direction option for stage 2 of
Forward
negative-sequence
overcurrent 3-161
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Name
Range
Step
Unit
Reverse
Remark protection Enabling/disabling
blocking
for
stage 2 of negative-sequence 21
50/51Q2.En_Abnor_Blk
overcurrent
0 or 1
protection
under
abnormal conditions 0: disable 1: enable Enabling/disabling
blocking
for
stage 2 of negative-sequence 22
50/51Q2.En_CTS_Blk
overcurrent protection under CT
0 or 1
failure conditions 0: disable 1: enable
DefTime IECN IECV IECE IECST 23
50/51Q2.Opt_Curve
IECLT
Option of characteristic curve for
ANSIE
stage 2 of negative-sequence
ANSIV
overcurrent protection
ANSI ANSIM ANSILTE ANSILTV ANSILT Time multiplier setting for stage 2 24
50/51Q2.TMS
0.010~200.000
of
0.001
inverse-time
negative-sequence
overcurrent
protection Minimum operating time for stage 25
50/51Q2.tmin
0.050~20.000
0.001
s
2
of
inverse-time
negative-sequence
overcurrent
protection Current setting for stage 3 of 26
50/51Q3.I2_Set
(0.050~30.000)×In
0.001
A
negative-sequence
overcurrent
protection Ratio coefficient (I2/I1) for stage 3 27
50/51Q3.I2/I1_Set
0.00~1.00
0.01
of negative-sequence overcurrent protection Time
28
50/51Q3.t_Op
0.000~20.000
0.001
s
delay
for
negative-sequence
stage
3
of
overcurrent
protection 3-162
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Name
Range
Step
Unit
Remark Enabling/disabling
stage 3
negative-sequence 29
50/51Q3.En
0 or 1
of
overcurrent
protection 0: disable 1: enable Enabling/Disabling auto-reclosing blocked
30
50/51Q3.En_BlkAR
when
stage
negative-sequence
0 or 1
3
of
overcurrent
protection operates 0: disable 1: enable
31
50/51Q3.Opt_Dir
Non_Directional
Direction option for stage 3 of
Forward
negative-sequence
Reverse
protection Enabling/disabling
overcurrent
blocking
for
stage 3 of negative-sequence 32
50/51Q3.En_Abnor_Blk
overcurrent
0 or 1
protection
under
abnormal conditions 0: disable 1: enable Enabling/disabling
blocking
for
stage 3 of negative-sequence 33
50/51Q3.En_CTS_Blk
overcurrent protection under CT
0 or 1
failure conditions 0: disable 1: enable
DefTime IECN IECV IECE IECST 34
50/51Q3.Opt_Curve
IECLT
Option of characteristic curve for
ANSIE
stage 3 of negative-sequence
ANSIV
overcurrent protection
ANSI ANSIM ANSILTE ANSILTV ANSILT Time multiplier setting for stage 3 35
50/51Q3.TMS
0.010~200.000
0.001
of negative-sequence
inverse-time overcurrent
protection
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Name
Range
Step
Unit
Remark Minimum operating time for stage
36
50/51Q3.tmin
0.050~20.000
0.001
s
3
of
inverse-time
negative-sequence
overcurrent
protection Current setting for stage 4 of 37
50/51Q4.I2_Set
(0.050~30.000)×In
0.001
A
negative-sequence
overcurrent
protection Ratio coefficient (I2/I1) for stage 4 38
50/51Q4.I2/I1_Set
0.00~1.00
0.01
of negative-sequence overcurrent protection Time
39
50/51Q4.t_Op
0.000~20.000
0.001
s
delay
for
stage
negative-sequence
4
of
overcurrent
protection Enabling/disabling
stage 4
negative-sequence 40
50/51Q4.En
0 or 1
of
overcurrent
protection 0: disable 1: enable Enabling/Disabling stage 4 of negative-sequence
41
50/51Q4.En_Trp
0 or 1
overcurrent
protection operate to trip or alarm. 0: alarm 1: trip Enabling/Disabling auto-reclosing blocked
42
50/51Q4.En_BlkAR
when
stage
negative-sequence
0 or 1
4
of
overcurrent
protection operates 0: disable 1: enable
43
50/51Q4.Opt_Dir
Non_Directional
Direction option for stage 4 of
Forward
negative-sequence
Reverse
protection Enabling/disabling
overcurrent
blocking
for
stage 4 of negative-sequence 44
50/51Q4.En_Abnor_Blk
overcurrent
0 or 1
protection
under
abnormal conditions 0: disable 1: enable Enabling/disabling
blocking
for
stage 4 of negative-sequence 45
50/51Q4.En_CTS_Blk
0 or 1
overcurrent protection under CT failure conditions 0: disable
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Name
Range
Step
Unit
Remark 1: enable
DefTime IECN IECV IECE IECST 46
50/51Q4.Opt_Curve
IECLT
Option of characteristic curve for
ANSIE
stage 4 of negative-sequence
ANSIV
overcurrent protection
ANSI ANSIM ANSILTE ANSILTV ANSILT Time multiplier setting for stage 4 47
50/51Q4.TMS
0.010~200.000
of
0.001
inverse-time
negative-sequence
overcurrent
protection Minimum operating time for stage 48
50/51Q4.tmin
0.050~20.000
0.001
s
4
of
inverse-time
negative-sequence
overcurrent
protection
3.16 Overcurrent Protection for VT Circuit Failure 3.16.1 General Application When protection VT circuit fails, distance protection will be disabled. As a substitute, definite-time or inverse-time phase overcurrent protection and ground overcurrent protection will be enabled automatically, if selected, as backup protection of distance protection.
3.16.2 Function Description Phase overcurrent protection and ground overcurrent protection can be selected as definite-time or inverse-time characteristic. The inverse-time characteristic is selectable among IEC and ANSI/IEEE standard inverse-time characteristics, and a user-defined inverse-time curve. Define-time or inverse-time phase overcurrent protection drops off instantaneously after fault current disappears. The inverse-time operating characteristic is as follows.
Equation 3.16-1
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Where: Iset is current setting [50PVT.I_Set] or [50GVT.3I0_Set]. Tp is time multiplier setting [50PVT.TMS] or [50GVT.TMS]. α is a constant. K is a constant. C is a constant. I is measured phase current from line CT The user can select the operating characteristic from various inverse-time characteristic curves by setting [50PVT.Opt_Curve] and [50GVT.Opt_Curve], and parameters of available characteristics for selection are shown in the following table. Table 3.16-1 Inverse-time curve parameters [50PVT.Opt_Curve]/[50GVT.Opt_Curve]
Time Characteristic
K
α
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
UserDefine
Programmable user-defined
If all available curves do not comply with user application, user may set [50PVT.Opt_Curve] and [50GVT.Opt_Curve] as “UserDefine” to customize the inverse-time curve characteristic with constants α, K and C. When inverse-time characteristic is selected, if calculated operating time is less than setting [50PVT.tmin] or [50GVT.tmin], then the operating time of the protection changes to the value of setting [50PVT.tmin] or [50GVT.tmin] automatically.
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3.16.3 Function Block Diagram 50PVT/50GVT 50PVT.En1
50PVT.On
50PVT.En2
50PVT.Op
50PVT.Blk
50PVT.St
50GVT.En1
50PVT.StA
50GVT.En2
50PVT.StB
50GVT.Blk
50PVT.StC 50GVT.On 50GVT.Op 50GVT.St
3.16.4 I/O Signals Table 3.16-2 I/O signals of overcurrent protection for VT circuit failure No.
Input Signal
1
50PVT.En1
2
50PVT.En2
3
50PVT.Blk
4
50GVT.En1
5
50GVT.En2
6
50GVT.Blk
No.
Description Phase overcurrent protection for VT circuit failure enabling input 1, it is triggered from binary input or programmable logic etc. Phase overcurrent protection for VT circuit failure enabling input 2, it is triggered from binary input or programmable logic etc. Phase overcurrent protection for VT circuit failure blocking input, it is triggered from binary input or programmable logic etc. Ground overcurrent protection for VT circuit failure enabling input 1, it is triggered from binary input or programmable logic etc. Ground overcurrent protection for VT circuit failure enabling input 2, it is triggered from binary input or programmable logic etc. Ground overcurrent protection for VT circuit failure blocking input, it is triggered from binary input or programmable logic etc.
Output Signal
Description
1
50PVT.On
Phase overcurrent protection for VT circuit failure is enabled.
2
50PVT.Op
Phase overcurrent protection for VT circuit failure operates.
3
50PVT.St
Phase overcurrent protection for VT circuit failure starts.
4
50PVT.StA
Phase overcurrent protection for VT circuit failure starts (A-Phase).
5
50PVT.StB
Phase overcurrent protection for VT circuit failure starts (B-Phase).
6
50PVT.StC
Phase overcurrent protection for VT circuit failure starts (C-Phase).
7
50GVT.On
Ground overcurrent protection for VT circuit failure is enabled.
8
50GVT.Op
Ground overcurrent protection for VT circuit failure operates.
9
50GVT.St
Ground overcurrent protection for VT circuit failure starts.
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3.16.5 Logic SIG
50PVT.En1
SIG
50PVT.En2
EN
[50PVT.En]
SIG
50PVT.Blk
& & 50PVT.On
&
>=1 [50PVT.t_Op]
&
SIG
FD.Pkp
SIG
VTS.Alm
SET
Ia>[50PVT.I_Set]
0ms
50PVT.Op
50PVT.St
& 50PVT.StA
& 50PVT.StB SET
Ib>[50PVT.I_Set]
& 50PVT.StC SET
Ic>[50PVT.I_Set]
&
Timer t
>=1
&
50PVT.Op [50PVT.t_Op]
SET
[50PVT.Opt_Curve]=DefTime
SIG
50GVT.En1
SIG
50GVT.En2
EN
[50GVT.En]
SIG
50GVT.Blk
SIG
FD.Pkp
SET
3I0>[50GVT.3I0_Set]
SIG
FD.ROC.Pkp
SIG
VTS.Alm
0
& & 50GVT.On
& & 50GVT.St
&
&
Timer t
>=1
&
50GVT.Op [50GVT.t_Op]
SET
0
[50GVT.Opt_Curve]=DefTime
Figure 3.16-1 Logic diagram of overcurrent protection for VT circuit failure
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3.16.6 Settings Table 3.16-3 Settings of overcurrent protection for VT circuit failure No. 1
Name 50PVT.I_Set
Range
Step
Unit
(0.050~30.000)×In
0.001
A
Remark Current setting of phase overcurrent protection when VT circuit failure Ttime delay of definite-time phase
2
50PVT.t_Op
0.000~10.000
0.001
s
overcurrent protection when VT circuit failure Enabling/disabling
phase
overcurrent protection when VT 3
50PVT.En
0 or 1
circuit failure 0: disable 1: enable
DefTime IECN IECV IECE IECST IECLT 4
50PVT.Opt_Curve
Option of characteristic curve for
ANSIE
inverse-time
ANSIV
phase
overcurrent
protection when VT circuit failure
ANSI ANSIM ANSILTE ANSILTV ANSILT UserDefine
Time 5
50PVT.TMS
0.010~200.000
0.001
multiplier
inverse-time
setting
phase
for
overcurrent
protection when VT circuit failure Minimum 6
50PVT.tmin
0.000~20.000
0.001
s
operating
inverse-time
phase
time
for
overcurrent
protection when VT circuit failure Constant 7
50PVT.Alpha
0.010~5.000
0.001
“α”
for
customized
inverse-time characteristic phase overcurrent protection when VT circuit failure Constant
8
50PVT.C
0.000~20.000
0.001
“C”
for
customized
inverse-time characteristic phase overcurrent protection when VT circuit failure
9
50PVT.K
0.050~20.000
0.001
Constant
“K”
for
customized
inverse-time characteristic phase 3-169
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Name
Range
Step
Unit
Remark overcurrent protection when VT circuit failure Current
10
50GVT.3I0_Set
(0.050~30.000)×In
0.001
A
setting
of
ground
overcurrent protection when VT circuit failure Time delay of definite-time ground
11
50GVT.t_Op
0.000~10.000
0.001
s
overcurrent protection when VT circuit failure Enabling/disabling
ground
overcurrent protection when VT 12
50GVT.En
0 or 1
circuit failure 0: disable 1: enable
DefTime IECN IECV IECE IECST IECLT 13
50GVT.Opt_Curve
Option of characteristic curve for
ANSIE
inverse-time
ANSIV
ground
overcurrent
protection when VT circuit failure
ANSI ANSIM ANSILTE ANSILTV ANSILT UserDefine
Time 14
50GVT.TMS
0.010~200.000
0.001
multiplier
inverse-time
setting
ground
for
overcurrent
protection when VT circuit failure Minimum 15
50GVT.tmin
0.000~20.000
0.001
s
operating
inverse-time
ground
time
for
overcurrent
protection when VT circuit failure Constant 16
50GVT.Alpha
0.010~5.000
0.001
“α”
for
customized
inverse-time characteristic ground overcurrent protection when VT circuit failure Constant
17
50GVT.C
0.000~20.000
0.001
“C”
for
customized
inverse-time characteristic ground overcurrent protection when VT circuit failure
18
50GVT.K
0.050~20.000
0.001
3-170
Constant
“K”
for
customized
inverse-time characteristic ground PCS-931 Line Differential Relay
Date: 2015-10-22
3 Operation Theory No.
Name
Range
Step
Unit
Remark overcurrent protection when VT circuit failure
3.17 Phase Current SOTF Protection 3.17.1 General Application When the circuit breaker is closed manually or automatically, it is possible to switch on to an existing fault. This is especially critical if the line in the remote station is grounded, since earth fault protection would not clear the fault until their time delays had elapsed. In this situation, however, the fastest possible clearance is desired. With phase current SOTF protection, a fast trip is achieved for a fault on the line when the line is being energized. It shall be responsive to all types of earth faults anywhere within the protected line, and it shall be enabled for the setting [SOTF.t_En] when the circuit is energized either manually or via an auto-reclosing system.
3.17.2 Function Description Phase current SOTF protection will operate to trip three-phase circuit breaker with a time delay of [50PSOTF.t_Op] when auto-reclosing or closing manually.
3.17.3 Function Block Diagram 50PSOTF 50PSOTF.En1
50PSOTF.On
50PSOTF.En2
50PSOTF.Op
50PSOTF.Blk
50PSOTF.St
3.17.4 I/O Signals Table 3.17-1 I/O signals of residual SOTF protection No.
Input Signal
1
50PSOTF.En1
2
50PSOTF.En2
3
50PSOTF.Blk
No.
Description Phase current SOTF protection enabling input 1, it is triggered from binary input or programmable logic etc. Phase current SOTF protection enabling input 2, it is triggered from binary input or programmable logic etc. Phase current SOTF protection blocking input, it is triggered from binary input or programmable logic etc.
Output Signal
Description
1
50PSOTF.On
Phase current SOTF protection is enabled.
2
50PSOTF.Op
Phase current SOTF protection operates.
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50PSOTF.St
Phase current SOTF protection starts.
3.17.5 Logic SIG 3-pole reclosing signal
>=1
SIG 1-pole reclosing signal SIG Manual closing signal SET Ia>[50PSOTF.I_Set]
>=1
SET Ib>[50PSOTF.I_Set] SET Ic>[50PSOTF.I_Set] SET Ua=1
SET Ub=1
SET Uca[50PSOTF.U2_Set]
EN
&
[50PSOTF.En_U2_OV]
SET U2>[50PSOTF.3U0_Set]
EN
&
&
[50PSOTF.En_3U0_OV]
>=1 >=1 EN
[50PSOTF.En_Up_UV]
EN
[50PSOTF.En_Upp_UV]
50PSOTF.St
& [50PSOTF.t_Op]
SIG FD.Pkp SIG 50PSOTF.En1
0ms
50PSOTF.Op
&
SIG 50PSOTF.En2
&
SIG 50PSOTF.Blk EN
50PSOTF.On
[50PSOTF.En]
Figure 3.17-1 Logic diagram of phase current SOTF protection
3.17.6 Settings Table 3.17-2 Settings of phase current SOTF protection No.
Name
Range
Step
Unit
1
50PSOTF.I_Set
(0.050~30.000)×In
0.001
A
2
50PSOTF.t_Op
0.000~10.000
0.001
s
3-172
Remark Current setting of phase current SOTF protection Time delay for phase current SOTF protection PCS-931 Line Differential Relay
Date: 2015-10-22
3 Operation Theory No.
Name
Range
Step
Unit
3
50PSOTF.Up_Set
(0~1) ×Un
0.001
V
4
50PSOTF.Upp_Set
(0~1) ×Un
0.001
V
Remark Voltage
setting
50PSOTF.U2_Set
(0~1) ×Un
0.001
V
phase
undervoltage supervision logic Voltage setting for phase-phase undervoltage supervision logic Voltage
5
for
setting
for
negative-sequence overvoltage supervision logic Voltage
6
50PSOTF.3U0_Set
(0~1) ×Un
0.001
V
setting
zero-sequence
for
overvoltage
supervision logic Enabling/disabling 7
50PSOTF.En
phase
current SOTF protection
0 or 1
0: disable 1: enable Enabling/disabling
phase
undervoltage supervision logic 8
50PSOTF.En_Up_UV
for
0 or 1
phase
current
SOTF
protection 0: disable 1: enable Enabling/disabling phase-phase undervoltage supervision logic
9
50PSOTF.En_Upp_UV
for
0 or 1
phase
current
SOTF
protection 0: disable 1: enable Enabling/disabling negative-sequence overvoltage
10
50PSOTF.En_U2_OV
supervision
0 or 1
logic
for
phase
current SOTF protection 0: disable 1: enable Enabling/disabling
11
50PSOTF.En_3U0_OV
0 or 1
zero-sequence
overvoltage
supervision
for
logic
phase
current SOTF protection 0: disable 1: enable
3.18 Residual Current SOTF Protection 3.18.1 General Application When the circuit breaker is closed manually or automatically, it is possible to switch on to an 3-173
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existing fault. This is especially critical if the line in the remote station is grounded, since earth fault protection would not clear the fault until their time delays had elapsed. In this situation, however, the fastest possible clearance is desired. Residual current SOTF (switch onto fault) protection is a complementary function to earth fault protection. With residual current SOTF protection, a fast trip is achieved for a fault on the line, when the line is being energized. It shall be responsive to all types of earth faults anywhere within the protected line, and it shall be enabled for the setting [SOTF.t_En] when the circuit is energized either manually or via an auto-reclosing system.
3.18.2 Function Description Residual current SOTF protection will operate to trip three-phase circuit breaker with a time delay of [50GSOTF.t_Op_1P] when 1-pole auto-reclosing. Residual current SOTF protection will operate to trip three-phase circuit breaker with a time delay of [50GSOTF.t_Op_3P] when 3-pole auto-reclosing or closing manually.
3.18.3 Function Block Diagram 50GSOTF 50GSOTF.En1
50GSOTF.On
50GSOTF.En2
50GSOTF.Op
50GSOTF.Blk
50GSOTF.St
3.18.4 I/O Signals Table 3.18-1 I/O signals of residual SOTF protection No.
Input Signal
1
50GSOTF.En1
2
50GSOTF.En2
3
50GSOTF.Blk
No.
Output Signal
Description Residual current SOTF protection enabling input 1, it is triggered from binary input or programmable logic etc. Residual current SOTF protection enabling input 2, it is triggered from binary input or programmable logic etc. Residual current SOTF protection blocking input, it is triggered from binary input or programmable logic etc. Description
1
50GSOTF.On
Residual current SOTF protection is enabled.
2
50GSOTF.Op
Residual current SOTF protection operates.
3
50GSOTF.St
Residual current SOTF protection starts.
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3.18.5 Logic EN
[50GSOTF.En_Hm2_Blk]
SIG
3-pole AR signal
SIG
Manual closing signal
SET
3I0>[50GSOTF.3I0_Set]
>=1 &
FD.ROC.Pkp
SIG
1-pole AR signal
SIG
50GSOTF.En1 50GSOTF.En2
SIG
50GSOTF.Blk
EN
[50GSOTF.En]
0ms
&
>=1 50GSOTF.Op
&
SIG
SIG
[50GSOTF.t_Op_3P]
[50GSOTF.t_Op_1P]
0ms
>=1 50GSOTF.St
& & 50GSOTF.On
Figure 3.18-1 Logic diagram of residual current SOTF protection
3.18.6 Settings Table 3.18-2 Settings of residual current SOTF protection No. 1
Name 50GSOTF.3I0_Set
Range
Step
Unit
(0.050~30.000)×In
0.001
A
Remark Current
setting
of
residual
current SOTF protection Time delay for residual current
2
50GSOTF.t_Op_3P
0.000~10.000
0.001
s
SOTF protection when 3 pole closed Time delay for residual current
3
50GSOTF.t_Op_1P
0.000~10.000
0.001
s
SOTF protection when 1 pole closed Enabling/disabling
4
50GSOTF.En
residual
current SOTF protection
0 or 1
0: disable 1: enable Enabling/disabling current
5
50GSOTF.En_Hm2_Blk
0 or 1
SOTF
residual protection
blocked by harmonic 0: disable 1: enable
3.19 Voltage Protection Voltage protection has the function of protecting device against undervoltage and overvoltage. Both operational states are unfavorable as overvoltage may cause insulation breakdown while undervoltage may cause stability problem. Each voltage protection function has three individual stages with respective time delay, but only one stage negative-sequence overvoltage protection is available. These voltage protection functions can be switched on or off separately. Selectable 3-175
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definite-time characteristic and multiple inverse-time characteristics are available.
3.19.1 Overvoltage Protection 3.19.1.1 General Application Abnormal high voltages often occur e.g. in low loaded, long distance transmission lines, in islanded systems when generator voltage regulation fails, or load rejection of a generator. Even if compensation reactors are provided to avoid line overvoltage by compensation of the line capacitance and thus reduction of the overvoltage, the overvoltage will endanger the insulation if the reactors fail. The line must be de-energized within a very short time. The overvoltage protection in this device detects the phase voltages Ua, Ub and Uc or the phase-to-phase voltages Uab, Ubc and Uca with an option of any phase or all phases operation for output. The overvoltage protection can be used for tripping purpose as well as to initiate transfer trip, which selectable controlled by local circuit breaker. 3.19.1.2 Function Description Phase overvoltage protection has following functions: 1.
Three stages phase overvoltage protection with independent logic, voltage and time delay settings.
2.
Overvoltage protection can be selected as definite-time or inverse-time characteristic. The inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics.
3.
Phase voltage or phase-to-phase voltage can be selected for protection calculation.
4.
“1-out-of-3” or “3-out-of-3” logic can be selected for protection criterion. (1-out-of-3 means any of three phase voltages, 3-out-of-3 means all three phase voltages)
1.
Operation Criterion
Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting [59Px.Opt_Up/Upp] is set to “0”, phase voltage criterion is selected and if [59Px.Opt_Up/Upp] is set to “1”, phase-to-phase voltage criterion is selected. When phase voltage or phase-to-phase voltage is greater than any enabled stage voltage setting, the stage protection picks up and operates after delay, which will drop off instantaneously when fault voltage disappears.
Phase voltage criterion
Two operation criteria of definite-time overvoltage protection are shown as follows, which of them is applied depending on the logic setting [59Px.Opt_1P/3P]. UΦ_max>[ 59Px.U_Set]
Equation 3.19-1
or Ua>[59Px.U_Set] & Ub>[59Px.U_Set] & Uc>[59Px.U_Set] 3-176
Equation 3.19-2
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3 Operation Theory
Where: UΦ_max is the maximum value among three phase-voltage. Ua, Ub, Uc are three phase voltages. [59Px.U_Set] is the setting of stage x (x=1, 2, 3) overvoltage protection. When [59Px.Opt_1P/3P] is set as “1”, “1-out-of-3” logic (Equation 3.19-1) is selected as operation criterion, and when set as “0”, “3-out-of-3” logic (Equation 3.19-2) is selected.
Phase-to-phase voltage criterion
Two operation criteria of definite-time overvoltage protection are shown as follows, which of them is applied depending on the logic setting [59Px.Opt_1P/3P]. UΦΦ_max>[ 59Px.U_Set]
Equation 3.19-3
or Uab>[59Px.U_Set] & Ubc>[59Px.U_Set] & Uca>[59Px.U_Set]
Equation 3.19-4
[59Px.U_Set] is the setting of stage x (x=1, 2, 3) overvoltage protection. When [59Px.Opt_1P/3P] is set as “1”, “1-out-of-3” logic (Equation 3.19-3) is selected as operation criterion, and when set as “0”, “3-out-of-3” logic (Equation 3.19-4) is selected. 2.
Characteristic Curve
Phase overvoltage protection can be selected as definite-time or inverse-time characteristic, and inverse-time operating time curve is as follows.
Equation 3.19-5
Where: Uset is the voltage setting [59Px.U_Set] (x=1, 2, 3). Tp is time multiplier setting [59Px.TMS]. K is a constant. C is a constant. α is a constant. U is the measured voltage Operating characteristic of overvoltage protection, can be chosen from definite-time characteristic and 12 inverse-time characteristics by setting the logic setting [59Px.Opt_Curve]. The parameters of each characteristic are listed in the following table.
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α
K
Time Characteristic
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
When inverse-time characteristic is selected, if calculated operating time is less than setting [59Px.tmin], then the operating time changes to the value of setting [59Px.tmin] automatically. Define-time or inverse-time phase overvoltage protection drops off instantaneously when measured voltage is lower than reset voltage. 3.19.1.3 Function Block Diagram 59Px 59Px.En1
59Px.On
59Px.En2
59Px.St
59Px.Blk
59Px.St1 59Px.St2 59Px.St3 59Px.Op 59Px.Alm 59Px.Op_InitTT
3.19.1.4 I/O Signals Table 3.19-2 I/O signals of overvoltage protection No.
Input Signal
1
59Px.En1
2
59Px.En2
Description Stage x of overvoltage protection enabling input 1, it is triggered from binary input or programmable logic etc. (x=1, 2, 3) Stage x of overvoltage protection enabling input 2, it is triggered from binary input
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Stage x of overvoltage protection blocking input, it is triggered from binary input or
59Px.Blk
No.
programmable logic etc. (x=1, 2, 3)
Output Signal
Description
1
59Px.On
Stage x of overvoltage protection is enabled. (x=1, 2, 3)
2
59Px.Op
Stage x of overvoltage protection operates. (x=1, 2, 3)
3
59Px.St
Stage x of overvoltage protection starts. (x=1, 2, 3)
4
59Px.St1
Stage x of overvoltage protection starts (A or AB). (x=1, 2, 3)
5
59Px.St2
Stage x of overvoltage protection starts (B or BC). (x=1, 2, 3)
6
59Px.St3
Stage x of overvoltage protection starts (C or CA). (x=1, 2, 3)
7
59Px.Op_InitTT
Stage x of overvoltage protection operates to initiate transfer trip. (x=1, 2, 3)
8
59Px.Alm
Stage x of overvoltage protection alarms. (x=1, 2, 3)
3.19.1.5 Logic EN
[59Px.En]
SIG
59Px.En1
SIG
59Px.En2
SIG
59Px.Blk
BI
[52b_PhA]
BI
[52b_PhB]
BI
[52b_PhC]
EN
[59Px.En_52b_TT]
EN
[59Px.En_TT]
EN
[59Px.En_Alm]
SIG
FD.Pkp
SIG
59Px.On
EN
[59Px.Opt_Up/Upp]
& & 59Px.On
& & & >=1 59Px.Op_InitTT
& &
&
& >=1
SET
Timer t t
UA>[59Px.U_Set]
& &
& SET
UAB>[59Px.U_Set]
&
& >=1
SET
Timer t
&
t
UB>[59Px.U_Set]
59Px.Op
& SET
&
UBC>[59Px.U_Set]
>=1 &
& >=1
SET
UC>[59Px.U_Set]
Timer t
>=1
t
& SET
59Px.Alm
&
>=1 59Px.St
UCA>[59Px.U_Set]
59Px.St1 59Px.St2 EN
[59Px.Opt_1P/3P]
59Px.St3
Figure 3.19-1 Logic diagram of stage x of overvoltage protection
x=1, 2, 3 3-179
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3.19.1.6 Settings Table 3.19-3 Settings of overvoltage protection No.
Name
Range
Step
Unit
1
59Px.U_Set
Un~2Unn
0.001
V
2
59Px.t_Op
0.000~30.000
0.001
s
Remark Voltage setting for stage x of overvoltage protection (x=1, 2, 3) Time delay for stage x of overvoltage protection (x=1, 2, 3) Enabling/disabling stage x of overvoltage
3
59Px.En
protection (x=1, 2, 3)
0 or 1
0: disable 1: enable Option of 1-out-of-3 mode or 3-out-of-3
4
59Px.Opt_1P/3P
mode (x=1, 2, 3)
0 or 1
0: 3-out-of-3 mode 1: 1-out-of-3 mode Option of phase-to-phase voltage or phase
5
59Px.Opt_Up/Upp
voltage (x=1, 2, 3)
0 or 1
0: phase voltage 1: phase-to-phase voltage Enabling/disabling stage x of overvoltage
6
59Px.En_Alm
protection for alarm purpose (x=1, 2, 3)
0 or 1
0: disable 1: enable Enabling/disabling transfer trip controlled by CB open position for stage x of
7
59Px.En_52b_TT
0 or 1
overvoltage protection (x=1, 2, 3) 0: disable 1: enable Enabling/disabling stage x of overvoltage protection operate to initiate transfer trip
8
59Px.En_TT
0 or 1
(x=1, 2, 3) 0: disable 1: enable
DefTime IECN IECV IECE 9
59Px.Opt_Curve
IECST
Option of characteristic curve for stage x of
IECLT
overvoltage protection (x=1, 2, 3)
ANSIE ANSIV ANSI ANSIM 3-180
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3 Operation Theory No.
Name
Range
Step
Unit
Remark
ANSILTE ANSILTV ANSILT Time multiplier setting for stage x of 10
59Px.TMS
0.010~200.000
0.001
inverse-time overvoltage protection (x=1, 2, 3)
11
59Px.tmin
0.050~20.000
0.001
Minimum delay for stage x of inverse-time
s
overvoltage protection (x=1, 2, 3)
3.19.2 Negative-sequence Overvoltage Protection 3.19.2.1 General Application On a healthy three-phase power system, negative-sequence voltage is nominally zero. However, when an unbalance situation occurs on the primary system, the negative-sequence voltage is produced. The device provides a one-stage negative-sequence overvoltage protection with definite time delay characteristic. 3.19.2.2 Function Block Diagram 59Q 59Q.En1
59Q.On
59Q.En2
59Q.Op
59Q.Blk
59Q.St
3.19.2.3 I/O Signals Table 3.19-4 I/O signals of negative-sequence overvoltage protection No.
Input Signal
1
59Q.En1
2
59Q.En2
3
59Q.Blk
No.
Description Negative-sequence overvoltage protection enabling input 1, it is triggered from binary input or programmable logic etc. Negative-sequence overvoltage protection enabling input 2, it is triggered from binary input or programmable logic etc. Negative-sequence overvoltage protection blocking input, it is triggered from binary input or programmable logic etc.
Output Signal
Description
1
59Q.On
Negative-sequence overvoltage protection is enabled.
2
59Q.Op
Negative-sequence overvoltage protection operates.
3
59Q.St
Negative-sequence overvoltage protection starts.
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3.19.2.4 Logic SIG
59Q.En1
SIG
59Q.En2
EN
[59Q.En]
SIG
59Q.Blk
& & 59Q.On
[59Q.t_Op]
&
59Q.Op
59Q.St SET
U2>[59Q.U_Set]
Figure 3.19-2 Logic diagram of negative-sequence overvoltage protection
3.19.2.5 Settings Table 3.19-5 Settings of negative-sequence overvoltage protection No.
Name
Range
Step
Unit
1
59Q.U_Set
0~Un
0.001
V
2
59Q.t_Op
0.000~30.000
0.001
s
Remark Voltage setting for negative-sequence overvoltage protection Time
delay
for
overvoltage protection Enabling/disabling
3
59Q.En
negative-sequence
negative-sequence
overvoltage protection
0 or 1
0: disable 1: enable
3.19.3 Residual Overvoltage Protection 3.19.3.1 General Application A single phase earth fault occurrence in ungrounded system or Peterson coil grounded system will result in residual overvoltage, so residual overvoltage protection is equipped to prevent protected equipment being damaged by residual overvoltage in this condition. 3.19.3.2 Function Description Residual overvoltage protection has following functions 1.
Three-stage residual overvoltage protection with independent logic, voltage and time delay settings.
2.
Stage 1 is definite-time characteristic, stage 2 and 3 can be selected as definite-time or inverse-time characteristic, only stage 3 can be defined for trip purpose or alarm purpose. The inverse-time characteristic is selectable among IEC and ANSI/IEEE standard inverse-time characteristics and a user-defined inverse-time curve.
3.
Define-time or inverse-time residual overvoltage protection drops off instantaneously.
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1. Operation Criterion 3U0> [59Gx.3U0_Set]
Equation 3.19-6
Where: 3U0 is calculated residual voltage. [59Gx.3U0_Set] is the voltage setting of stage x (x=1, 2 or 3) of residual overvoltage protection. If residual voltage is greater than the setting of any stage enabled residual overvoltage protection, the stage residual overvoltage protection will operate after time delay and the stage protection will drop off instantaneously after fault voltage disappears. 2. Time Curve Stage 1 of residual overvoltage protection is definite-time characteristic and can perform instantaneous operation with the corresponding time delay being set as “0”. Stage 2 and 3 can be selected as definite-time or inverse-time characteristic, and inverse-time operating time curve is as follows.
Equation 3.19-7
Where: Uset is residual voltage setting [59Gx.3U0_Set]. Tp is time setting [59Gx.TMS]. K and C are constants. α is a constant. U is actual measured residual voltage. The user can select the operating characteristic from various inverse-time characteristic curves by setting [59Gx.Opt_Curve], and parameters of available characteristics for selection are shown in the following table. Table 3.19-6 Inverse-time curve parameters of residual overvoltage protection 59Gx.Opt_Curve (x=2 or 3)
α
K
Time Characteristic
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
3-183
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α
K
Time Characteristic
C
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
UserDefine
Programmable user-defined
If all available curves do not comply with user application, user may configure setting [59Gx.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and constants K, α and C. 3.19.3.3 Function Block Diagram 59G 59Gx.En1
59Gx.On
59Gx.En2
59Gx.St
59Gx.Blk
59Gx.Op 59G3.Alm
3.19.3.4 I/O Signals Table 3.19-7 I/O signals of residual overvoltage protection No.
Signal
1
59Gx.En1
2
59Gx.En2
3
59Gx.Blk
No.
Signal
Description Stage x of residual overvoltage protection enabling input 1, it is triggered from binary input or programmable logic etc. (x=1, 2, 3) Stage x of residual overvoltage protection enabling input 2, it is triggered from binary input or programmable logic etc. (x=1, 2, 3) Stage x of overvoltage protection blocking input, it is triggered from binary input or programmable logic etc. (x=1, 2, 3) Description
1
59G x.On
Stage x of residual overvoltage protection is enabled. (x=1, 2, 3)
2
59G x.Op
Stage x of residual overvoltage protection operates. (x=1, 2, 3)
3
59Gx.St
Stage x of residual overvoltage protection start. (x=1, 2, 3)
4
59G3.Alm
Stage 3 of residual overvoltage protection operates to alarm.
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3 Operation Theory
3.19.3.5 Logic EN
[59G1.En]
SIG
59G1.En1
SIG
59G1.En2
SIG
59G1.Blk
SET
3U0>[59G1.3U0_Set]
& & 59G1.On
& 59G1.St [59G1.t_Op]
0
59G1.Op
Figure 3.19-3 Logic diagram of stage 1 of residual overvoltage protection EN
[59G2.En]
SIG
59G2.En1
SIG
59G2.En2
SIG
59G2.Blk
SET
3U0>[59G2.3U0_Set]
& & 59G2.On
& 59G2.St Timer t
&
t
>=1 59G2.Op
& [59G2.t_Op] SET
0
[59G2.Opt_Curve]=DefTime
Figure 3.19-4 Logic diagram of stage 2 of residual overvoltage protection EN
[59G3.En]
SIG
59G3.En1
SIG
59G3.En2
SIG
59G3.Blk
SET
3U0>[59G3.3U0_Set]
& & 59G3.On
& 59G3.St
&
Timer t t
>=1 & [59G3.t_Op] SET
[59G3.Opt_Curve]=DefTime
EN
[59G3.En_Trp]
0
& 59G3.Op
& 59G3.Alm
Figure 3.19-5 Logic diagram of stage 3 of residual overvoltage protection
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3.19.3.6 Settings Table 3.19-8 Settings of residual overvoltage protection No.
Name
Range
Step
Unit
1
59G1.3U0_Set
2.000~200.000
0.001
V
2
59G1.t_Op
0.000~3600.000
0.001
s
Remark Voltage setting of stage 1 of residual overvoltage protection. Time delay of stage 1 of residual overvoltage protection. Enabling/disabling stage 1 of residual
3
59G1.En
overvoltage protection.
0 or 1
0: disable 1: enable
4
59G2.3U0_Set
2.0000~200.000
0.001
V
5
59G2.t_Op
0.000~3600.000
0.001
s
6
59G2.tmin
0.000~20.000
0.001
s
7
59G2.TMS
0.050~3.200
0.001
Voltage setting of stage 2 of residual overvoltage protection. Time delay of stage 2 of residual overvoltage protection. Minimum operating time for stage 2 of residual overvoltage protection Time multiplier setting for stage 2 of residual overvoltage protection Constant “K” for stage 2 of customized
8
59G2.K
0.000~120.000
0.001
inverse-time
characteristic
residual
overvoltage protection Constant “C” for stage 2 of customized 9
59G2.C
0.000~20.000
0.001
inverse-time
characteristic
residual
overvoltage protection Constant “α” for stage 2 of customized 10
59G2.Alpha
0.020~5.000
0.001
inverse-time
characteristic
residual
overvoltage protection DefTime IECN IECV IECE IECST IECLT 11
59G2.Opt_Curve
ANSIE
Option of characteristic curve for stage 2
ANSIV
of residual overvoltage protection
ANSI ANSIM ANSILTE ANSILTV ANSILT UserDefine 12
59G2.En
0 or 1
Enabling/disabling stage 2 of residual
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Name
Range
Step
Unit
Remark overvoltage protection. 0: disable 1: enable
13
59G3.3U0_Set
2.0000~200.000
0.001
V
14
59G3.t_Op
0.000~3600.000
0.001
s
15
59G3.tmin
0.000~20.000
0.001
s
16
59G3.TMS
0.050~3.200
0.001
Voltage setting of stage 3 of residual overvoltage protection. Time delay of stage 3 of residual overvoltage protection. Minimum operating time for stage 3 of residual overvoltage protection Time multiplier setting for stage 3 of residual overvoltage protection Constant “K” for stage 3 of customized
17
59G3.K
0.000~120.000
0.001
inverse-time
characteristic
residual
overvoltage protection Constant “C” for stage 3 of customized 18
59G3.C
0.000~20.000
0.001
inverse-time
characteristic
residual
overvoltage protection Constant “α” for stage 3 of customized 19
59G3.Alpha
0.020~5.000
0.001
inverse-time
characteristic
residual
overvoltage protection DefTime IECN IECV IECE IECST IECLT 20
59G3.Opt_Curve
ANSIE
Option of characteristic curve for stage 3
ANSIV
of residual overvoltage protection
ANSI ANSIM ANSILTE ANSILTV ANSILT UserDefine Enabling/disabling stage 3 of residual 21
59G3.En
overvoltage protection.
0 or 1
0: disable 1: enable Enabling/disabling stage 3 of residual
22
59G3.En_Trp
overvoltage protection for trip purpose.
0 or 1
0: disable 1: enable
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3.19.4 Undervoltage Protection 3.19.4.1 General Application The undervoltage protection can be applied to trip when fault occurs in a system. Two stages of undervoltage protection are available measuring phase voltages U A, UB and UC or phase-to-phase voltages UAB, UBC and UCA. The protection output can be selected for either any phase or all phases operation. The undervoltage protection is normally used as decoupling system rather than load shedding. 3.19.4.2 Function Description Phase undervoltage protection has following functions: 1.
Three stages phase undervoltage protection with independent logic, voltage and time delay settings.
2.
Undervoltage protection can be selected as definite-time or inverse-time characteristic. The inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics.
3.
Phase voltage or phase-to-phase voltage can be selected for protection calculation.
4.
“1-out-of-3” or “3-out-of-3” logic can be selected for protection criterion. (1-out-of-3 means any of three phase voltages, 3-out-of-3 means all three phase voltages)
1.
Operation Criterion
Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting [27Px.Opt_Up/Upp] is set to “0”, phase voltage criterion is selected and if [27Px.Opt_Up/Upp] is set to “1”, phase-to-phase voltage criterion is selected. When phase voltage or phase-to-phase voltage is less than any enabled stage voltage setting, the stage protection picks up and operates after delay, which will drop off instantaneously when fault voltage disappears.
Phase voltage criterion
Two operation criteria of definite-time undervoltage protection are shown as follows, which of them is applied depending on the logic setting [27Px.Opt_1P/3P]. UΦ_min=1 UV_PhB_Curr_Rls
SIG
Ic>0.06In
>=1 UV_PhC_Curr_Rls & >=1 UV_PhAB_Curr_Rls & >=1 UV_PhBC_Curr_Rls & >=1 UV_PhCA_Curr_Rls
EN
27Px.En_Curr_Ctrl
EN
[27Px.En_Alm]
SET
[27P1.Opt_1P/3P]
SIG
27Px.On
SIG
Block UV
SET
[27Px.Opt_Up/Upp] &
SIG
UV_PhA_Curr_Rls
SET
UA=1
&
Timer t
27Px.Op
t
UB=1
UV_PhAB_Curr_Rls
27Px.Alm
& SET
UBC=1 &
SIG
UV_PhBC_Curr_Rls
SET
UC=1
Timer t t 27Px.St1
& SIG
UV_PhCA_Curr_Rls
SET
UCA=1 27Px.St
Figure 3.19-7 Logic diagram of stage x of undervoltage protection 3-193
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x=1, 2, 3 3.19.4.6 Settings Table 3.19-11 Settings of undervoltage protection No.
Name
Range
Step
Unit
1
27Px.U_Set
0~Unn
0.001
V
2
27Px.t_Op
0.000~30.000
0.001
s
Remark Voltage setting for stage x of undervoltage protection (x=1, 2, 3) Time delay for stage x of undervoltage protection (x=1, 2, 3) Enabling/disabling stage x of undervoltage
3
27Px.En
protection (x=1, 2, 3)
0 or 1
0: disable 1: enable Enabling/disabling stage x of undervoltage protection controlled by
4
27Px.En_FD_Ctrl
0 or 1
FD element
reflecting current (x=1, 2, 3) 0: disable 1: enable Enabling/disabling stage x of undervoltage protection controlled by current condition
5
27Px.En_Curr_Ctrl
0 or 1
(x=1, 2, 3) 0: disable 1: enable Enabling/disabling stage x of undervoltage protection controlled by VT circuit failure
6
27Px.En_VTS_Blk
0 or 1
(x=1, 2, 3) 0: disable 1: enable Option of 1-out-of-3 mode or 3-out-of-3 mode
7
27Px.Opt_1P/3P
0 or 1
for
stage
x
of
undervoltage
protection (x=1, 2, 3) 0: 3-out-of-3 mode 1: 1-out-of-3 mode Option
of
voltage
criterion
adopting
phase-to-phase voltage or phase voltage 8
27Px.Opt_Up/Upp
0 or 1
for stage x of undervoltage protection 0: phase voltage (x=1, 2, 3) 1: phase-to-phase voltage Enabling/disabling stage x of undervoltage
9
27Px.En_Alm
protection operate to alarm (x=1, 2, 3)
0 or 1
0: disable 1: enable
10
27Px.Opt_Curve
DefTime
Option of characteristic curve for stage x
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Name
Range
Step
Unit
IECN
Remark of undervoltage protection (x=1, 2, 3)
IECV IECE IECST IECLT ANSIE ANSIV ANSI ANSIM ANSILTE ANSILTV ANSILT Time multiplier setting for stage x of 11
27Px.TMS
0.010~200.000
0.001
inverse-time undervoltage protection (x=1, 2, 3)
12
27Px.tmin
0.050~20.000
0.001
s
Minimum delay for stage x of inverse-time undervoltage protection (x=1, 2, 3)
3.20 Frequency Protection 3.20.1 Overfrequency Protection 3.20.1.1 General Application If the power frequency of regional rises due to the active power excess demand, overfrequency protection operates to perform generator rejection to shed part of the generators automatically according to the rising frequency so that power supply and the load are re-balanced. 3.20.1.2 Function Description Overfrequency protection consists of the four stages (stage 1 to stage 4). When system frequency is greater than the setting [81O.f_Pkp], overfrequency protection will put into service. In order to prevent possible maloperation of overfreqency protection in conditions of high harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows: 1.
Blocking in undervoltage condition
If the positive voltage U1[81O.OFx.f_Set]
Equation 3.20-1
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Where: f is system frequency. [81O.OFx.f_Set] is the frequency setting of stage x (x=1, 2, 3, or 4) of overfrequency protection. 3.20.1.3 Function Block Diagram 81O.OFx 81O.En1
81O.OFx.On
81O.En2
81O.St
81O.Blk
81O.OFx.Op
3.20.1.4 I/O Signals Table 3.20-1 I/O signals of overfrequency protection No.
Input Signal
1
81O.En1
2
81O.En2
3
81O.Blk
No.
Description Overfrequency protection enabling input 1, it is triggered from binary input or programmable logic etc. Overfrequency protection enabling input 2, it is triggered from binary input or programmable logic etc. Overfrequency protection blocking input, it is triggered from binary input or programmable logic etc.
Output Signal
Description
1
81O.OFx.On
Stage x of overfrequency protection is enabled (x=1, 2, 3 or 4).
2
81O.OFx.Op
Stage x of overfrequency protection operates (x=1, 2, 3 or 4).
3
81O.St
Overfrequency protection starts.
3.20.1.5 Logic SIG
81O.En1
SIG
81O.En2
EN
[81O.OF1.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1[81O.f_Pkp]
& & 81O.OF1.On
& ≥1
& 50ms
0ms 81O.St1
& SET
f>[81O.OF1.f_Set]
EN
[81O.OF1.En]
[81O.OF1.t_Op]
&
0ms
81O.OF1.Op
Figure 3.20-1 Logic diagram of overfrequency protection (stage 1) 3-196
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81O.En1
SIG
81O.En2
EN
[81O.OF2.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1[81O.f_Pkp]
& & 81O.OF2.On
& ≥1
& 50ms
0ms 81O.St2
& SET
f>[81O.OF2.f_Set]
EN
[81O.OF2.En]
[81O.OF2.t_Op]
&
0ms
81O.OF2.Op
Figure 3.20-2 Logic diagram of overfrequency protection (stage 2) SIG
81O.En1
SIG
81O.En2
EN
[81O.OF3.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1[81O.f_Pkp]
& & 81O.OF3.On
& ≥1
& 50ms
0ms 81O.St3
& SET
f>[81O.OF3.f_Set]
EN
[81O.OF3.En]
[81O.OF3.t_Op]
&
0ms
81O.OF3.Op
Figure 3.20-3 Logic diagram of overfrequency protection (stage 3) SIG
81O.En1
SIG
81O.En2
EN
[81O.OF4.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1[81O.f_Pkp]
& & 81O.OF4.On
& ≥1
& 50ms
0ms 81O.St4
& SET
f>[81O.OF4.f_Set]
EN
[81O.OF4.En]
[81O.OF4.t_Op]
&
0ms
81O.OF4.Op
Figure 3.20-4 Logic diagram of overfrequency protection (stage 4)
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81O.St1
SIG
81O.St2
SIG
81O.St3
SIG
81O.St4
≥1
≥1 81O.St
≥1
Figure 3.20-5 Logic diagram of overfrequency protection (start)
3.20.1.6 Settings Table 3.20-2 Settings of overfrequency protection No.
Name
Range
Step
Unit
1
81O.f_Pkp
50.000~65.000 (Hz)
0.001
Hz
2
81O.OF1.f_Set
50.000~65.000 (Hz)
0.001
Hz
3
81O.OF1.t_Op
0.050~20.000 (s)
0.001
s
Remark Frequency
pickup
81O.OF1.En
for
overfrequency protection Frequency setting for stage 1 of overfrequency protection Time
delay
for
stage
1
of
1
of
overfrequency protection Enabling/disabling
4
setting
stage
overfrequency protection
0 or 1
0: disable 1: enable
5
81O.OF2.f_Set
50.000~65.000 (Hz)
0.001
Hz
6
81O.OF2.t_Op
0.050~20.000 (s)
0.001
s
Frequency setting for stage 2 of overfrequency protection Time
delay
for
81O.OF2.En
2
of
2
of
overfrequency protection Enabling/disabling
7
stage
stage
overfrequency protection
0 or 1
0: disable 1: enable
8
81O.OF3.f_Set
50.000~65.000 (Hz)
0.001
Hz
9
81O.OF3.t_Op
0.050~20.000 (s)
0.001
s
Frequency setting for stage 3 of overfrequency protection Time
delay
for
81O.OF3.En
3
of
3
of
overfrequency protection Enabling/disabling
10
stage
stage
overfrequency protection
0 or 1
0: disable 1: enable
11
81O.OF4.f_Set
50.000~65.000 (Hz)
0.001
Hz
12
81O.OF4.t_Op
0.050~20.000 (s)
0.001
s
13
81O.OF4.En
0 or 1
Frequency setting for stage 4 of overfrequency protection Time
delay
for
Enabling/disabling
3-198
stage
4
of
4
of
overfrequency protection stage
PCS-931 Line Differential Relay Date: 2015-10-22
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Name
Range
Step
Unit
Remark overfrequency protection 0: disable 1: enable
3.20.2 Underfrequency Protection 3.20.2.1 General Application In case of frequency decline due to lack of active power in the power system, underfrequency protection operates to shed part of the load according to the declined value of frequency to re-balance the power supply and the load. 3.20.2.2 Function Description Underfrequency protection consists of the four stages (stage 1 to stage 4). When system frequency is smaller than the setting [81U.f_Pkp], underfrequency protection will put into service. In order to prevent possible maloperation of underfrequency protection in conditions of high harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows: 1.
Blocking in undervoltage condition
If the positive voltage U1[CBx.50BF.I_Set]
SIG
CBx.BFI_C
& CBx.50BF.On
&
>=1
& >=1
&
>=1
&
>=1
&
[CBx.50BF.t_ReTrp] 0ms
CBx.50BF.Op_ReTrpA
[CBx.50BF.t_ReTrp] 0ms
CBx.50BF.Op_ReTrpB
[CBx.50BF.t_ReTrp] 0ms
CBx.50BF.Op_ReTrpC
&
&
BI
[CBx.50BF.ExTrpC]
SET
IC>[CBx.50BF.I_Set]
SIG
CBx.BFI_3P
BI
>=1 >=1 >=1
& &
[CBx.50BF.ExTrp3P_L]
>=1 [CBx.50BF.t_ReTrp] 0ms
>=1 BI
[CBx.50BF.ExTrp3P_GT]
BI
[CBx.50BF.ExTrp_WOI]
EN
[CBx.50BF.En_3I0_3P]
SET
3I0>[CBx.50BF.3I0_Set]
EN
[CBx.50BF.En_I2_3P]
SET
I2>[CBx.50BF.I2_Set]
EN
[CBx.50BF.En_CB_Ctrl]
BI
[CBx.52b_PhA]
BI
[CBx.52b_PhB]
BI
[CBx.52b_PhC]
SIG
CBx.50BF.On
SIG
FD.Pkp
>=1
[CBx.50BF.Op_ReTrp3P]
&
& &
& &
>=1
>=1
[CBx.50BF.t1_Op]
0ms
CBx.50BF.Op_t1
[CBx.50BF.t2_Op]
0ms
CBx.50BF.Op_t2
&
&
&
&
Figure 3.21-1 Logic diagram of breaker failure protection
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3.21.6 Settings Table 3.21-2 Settings of breaker failure protection No.
Name
Range
Step
Unit
Remark Current setting of phase current criterion for BFP
1
CBx.50BF.I_Set
(0.050~30.000 )×In
0.001
A
2
CBx.50BF.3I0_Set
(0.050~30.000 )×In
0.001
A
3
CBx.50BF.I2_Set
(0.050~30.000 )×In
0.001
A
4
CBx.50BF.t_ReTrp
0.000~10.000
0.001
s
Time delay of re-tripping for BFP
5
CBx.50BF.t1_Op
0.000~10.000
0.001
s
Time delay of stage 1 for BFP
6
CBx.50BF.t2_Op
0.000~10.000
0.001
s
Time delay of stage 2 for BFP
7
CBx.50BF.En
0 or 1
8
CBx.50BF.En_ReTrp
0 or 1
9
CBx.50BF.En_3I0_1P
0 or 1
10
CBx.50BF.En_3I0_3P
0 or 1
11
CBx.50BF.En_I2_3P
0 or 1
12
CBx.50BF.En_CB_Ctrl
0 or 1
Current setting of zero-sequence current criterion for BFP Current setting of negative-sequence current criterion for BFP
Enabling/disabling breaker failure protection 0: disable 1: enable Enabling/disabling re-trip function for BFP 0: disable 1: enable Enabling/disabling zero-sequence current criterion for BFP initiated by single-phase tripping contact 0: disable 1: enable Enabling/disabling zero-sequence current criterion for BFP initiated by three-phase tripping contact 0: disable 1: enable Enabling/disabling negative-sequence current criterion for BFP initiated by three-phase tripping contact 0: disable 1: enable Enabling/disabling breaker failure protection can be initiated by normally closed contact of circuit breaker 0: disable 1: enable
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3.22 Thermal Overload Protection 3.22.1 General Application During overload operation of a transmission line (specially for cable), great current results in greater heat to lead temperature increase and if the temperature reaches too high values the equipment might be damaged. Thermal overload protection estimates the internal heat content (temperature) continuously. This estimation is made by using a thermal model with two time constants, which is based on current measurement. When the temperature increases to the alarm value, the protection issues alarm signals to remind the operator for attention, and if the temperature continues to increase to the trip value, the protection sends trip command to disconnect the protected line.
3.22.2 Function Description Thermal overload protection has following functions:
Thermal time characteristic adopting IEC 60255-8
Two stages for alarm purpose and two stages for trip purpose
Thermal accumulation can be cleared by external input signal
The device provides a thermal overload model which is based on the IEC60255-8 standard. The thermal overload formulas are shown as below. 1.
Cold start characteristic:
2.
Hot start characteristic:
Where: T = Time to operate (in seconds)
= Thermal time constant of the equipment to be protected, the setting [49.Tau] IB = Full load current rating, the setting [49.Ib_Set] I = The RMS value of the largest phase current IP = Steady state pre-loading before application of the overload k = Factor associated to the thermal state formula, the setting [49.K] 3-209
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ln = Natural logarithm The characteristic curve of thermal overload model is shown in Figure 3.22-1. Refer to IEC60255-8
t
Ip P=— IB
P = 0.0 P = 0.6 P = 0.8 P = 0.9
kIB
I
Figure 3.22-1 Characteristic curve of thermal overload model
The hot start characteristic is adopted in the device. The calculation is carried out at zero of Ip, so users need not to set the value of Ip. Tripping outputs of the protection is controlled by current, even if the thermal accumulation value is greater than the setting for tripping, the protection drops off instantaneously when current disappears. Alarm outputs of the protection is not controlled by current, and only if the thermal accumulation value is greater than the setting for alarm, alarm output contacts, which can be connected to block the auto-reclosure, will operate.
3.22.3 Function Block Diagram 49 49.Clr_Cmd
49.On
49.En
49.St
49.Blk
49-1.Alm 49-1.Op 49-2.Alm 49-2.Op
3.22.4 I/O Signals Table 3.22-1 I/O signals of thermal overload protection No. 1
Input Signal 49.Clr_Cmd
Description Input signal of clear thermal accumulation value
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49.En
3
49.Blk
No.
Thermal overload protection enabling input, it is triggered from binary input or programmable logic etc. Thermal overload protection blocking input, it is triggered from binary input or programmable logic etc.
Output Signal
Description
1
49.On
Thermal overload protection is enabled.
2
49.St
Thermal overload protection starts.
3
49-1.Op
Stage 1 of thermal overload protection operates to trip.
4
49-2.Op
Stage 2 of thermal overload protection operates to trip.
5
49-1.Alm
Stage 1 of thermal overload protection operates to alarm.
6
49-2.Alm
Stage 2 of thermal overload protection operates to alarm.
3.22.5 Logic SIG
49.En
SIG
49.Blk
EN
[49-1.En_Trp]
EN
[49-1.En_Alm]
SIG
FD.Pkp
& & 49.On >=1
& 49.St &
Timer t
49-1.Op
t SIG
I3P &
SET
[49.Ib_Set]
BI
[49.Clr_Cmd]
Timer t
49-1.Alm
t
Figure 3.22-2 Logic diagram of thermal overload protection (stage 1)
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49.En
SIG
49.Blk
EN
[49-2.En_Trp]
EN
[49-2.En_Alm]
SIG
FD.Pkp
& & 49.On >=1
& 49.St Timer t
&
49-2.Op
t I3P
SIG
Timer t
& SET
[49.Ib_Set]
BI
[49.Clr_Cmd]
49-2.Alm
t
Figure 3.22-3 Logic diagram of thermal overload protection (stage 2)
3.22.6 Settings Table 3.22-2 Settings of thermal overload protection No.
Name
Range
Step
Unit
1
49-1.K
1.000~3.000
0.001
%
2
49-2.K
1.000~3.000
0.001
%
3
49.Ib_Set
(0.050~30.000 )×In
0.001
A
4
49.Tau
0.100~100.000
0.001
min
5
49-1.En_Alm
0 or 1
6
49-1.En_Trp
0 or 1
7
49-2.En_Alm
0 or 1
3-212
Remark The factor setting for stage 1 of thermal overload protection which is associated to the thermal state formula The factor setting for stage 2 of thermal overload protection which is associated to the thermal state formula The reference current setting of the thermal overload protection The time constant setting of the IDMT overload protection Enabling/disabling stage 1 of thermal overload protection for alarm purpose 0: disable 1: enable Enabling/disabling stage 1 of thermal overload protection for trip purpose 0: disable 1: enable Enabling/disabling stage 2 of thermal overload protection for alarm purpose 0: disable 1: enable
PCS-931 Line Differential Relay Date: 2015-10-22
3 Operation Theory No.
8
Name
49-2.En_Trp
Range
Step
Unit
Remark Enabling/disabling stage 2 of thermal overload protection for trip purpose 0: disable 1: enable
0 or 1
3.23 Stub Differential Protection 3.23.1 General Application Stub differential protection is mainly designed for one and a half breakers arrangement. When line disconnector is open and transmission line is put into maintenance, line VT is no voltage. Distance protection is disabled, and stub differential protection is enabled. It is used to protect stub section among two circuit breakers and line disconnector. Usually, stub differential protection is enabled automatically by normally closed auxiliary contact of line disconnector. CT1
CT2
Bus
Bus
To the device
Line
Line
Figure 3.23-1 3/2 breakers arrangement
3.23.2 Function Description 3.23.2.1 Stub Differential Element Stub differential element is composed of percentage differential principle. Stub differential element can be controlled by normally closed auxiliary contact of line disconnector to enabled or disabled. The normally closed auxiliary contact of line disconnector is closed when line disconnector is open. The operation criterion is: I 1 I 2 [87STB.I_Pkp] I I 1 2 [87STB.Slop e] I 1 I 2
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Where:
I 1 、 I 2 are secondary phase currents corresponding to both circuit breakers, are formed by phase A, B, C 3.23.2.2 Differential Current Alarm Under normal conditions, when stub differential protection is enabled, the device will issue the alarm signal [87STB.Alm_Diff] with the time delay if the following operation criterion is met. I 1 I 2 [87STB.I_Al m] I I 1 2 0.15 I 1 I 2
3.23.2.3 Disconnector Position Alarm The device will issue the alarm signal [87STB.Alm_89b_DS] with the time delay of 10s if the signal [87STB.89b_DS] is energized and the line is live, and the alarm signal will drop off with the time delay of 10s after the abnormality disappears. When the alarm signal of disconnector position appears, the operator should confirm the status of disconnector position in time. The user can use programable logic to determine whether the disconnector position alarm will blocked stub differential protection. 3.23.2.4 CT Saturation When there is an external fault, transient CT saturation may be happened. In order to prevent stub differential protection from undesired operation, the floating technology of adaptive restraint current is adopted to ensure that the device does not maloperate due to the serious saturation.
3.23.3 Function Block Diagram 87STB 87STB.En1
87STB.On
87STB.En2
87STB.On_Local
87STB.Blk
87STB.Op
87STB.89b_DS
87STB.St
87STB.89b_DS_Rmt
87STB.StA 87STB.StB 87STB.StC 87STB.Alm_Diff 87STB.Alm_89b_DS
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3.23.4 I/O Signals Table 3.23-1 I/O signals of stub differential protection No.
Input Signal
1
87STB.En1
2
87STB.En2
3
87STB.Blk
4
87STB.89b_DS
Description Stub differential protection enabling input 1, it is triggered from binary input or programmable logic etc. Stub differential protection enabling input 2, it is triggered from binary input or programmable logic etc. Stub differential protection blocking input, it is triggered from binary input or programmable logic etc. Normally closed auxiliary contact of line disconnector Normally closed auxiliary contact of line disconnector in remote end
5
87STB.89b_DS_Rmt
In general, it is configured as receiving the signal [87STB.On_Local] from the remote end.
No.
Output Signal
Description Stub differential protection is enabled. (Based on disconnector position signal
1
87STB.On
2
87STB.On_Local
3
87STB.Op
Stub differential protection operates.
4
87STB.St
Stub differential protection starts.
5
87STB.StA
Phase A of stub differential protection starts.
6
87STB.StB
Phase B of stub differential protection starts.
7
87STB.StC
Phase C of stub differential protection starts.
8
87STB.Alm_Diff
The alarm signal of differential current abnormality
9
87STB.Alm_89b_DS
The alarm signal of disconnector position abnormality
in both local end and remote end) Stub differential protection is enabled. (Based on disconnector position signal in local end)
3.23.5 Logic Based on calculating vector summation of currents from dual CTs, the logic scheme of stub differential protection is shown as Figure 3.23-2.
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Idiff>0.06In
SIG
87STB.89b_DS
SIG
87STB.En1
SIG
87STB.En2
EN
[87STB.En]
SIG
87STB.Blk
SIG
Enable 87STB
SIG
87STB.89b_DS
& 10s
10s
87STB.Alm_89b_DS
& & Enable 87STB
& 87STB.On_Local
>=1 &
SIG
87STB.89b_DS_Rmt
SET
Idiffa>[87STB.I_Alm]
SET
IdiffA>0.15×IBiasA
SET
Idiffb>[87STB.I_Alm]
87STB.On
& & &
>=1
&
& 10s
SET
IdiffB>0.15×IBiasB
SET
Idiffc>[87STB.I_Alm]
SET
IdiffC>0.15×IBiasC
En
[87STB.En_Alm]
SIG
87STB.Alm_Diff
SIG
87STB.En_CTS_Blk
SET
Idiffa>[87STB.I_Pkp]
SET
IdiffA>[87STB.Slope]×IBiasA
SET
Idiffb>[87STB.I_Pkp]
SET
IdiffB>[87STB.Slope]×IBiasB
SET
Idiffc>[87STB.I_Pkp]
SET
IdiffC>[87STB.Slope]×IBiasC
10s
87STB.Alm_Diff
& &
>=1
>=1
87STB.St [87STB.t_Op]
87STB.Op
& 87STB.StA
& &
87STB.StB
& &
87STB.StC
&
Figure 3.23-2 Logic diagram of stub differential protection
3.23.6 Settings Table 3.23-2 Settings of stub differential protection No. 1
Name 87STB.I_Pkp
Range
Step
Unit
(0.050~30.000)×In
0.001
A
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3 Operation Theory No.
Name
Range
Step
Unit A
2
87STB.I_ Alm
(0.050~30.000)×In
0.001
3
87STB.Slope
0.5~1
0.001
4
87STB.t_Op
0.000~10.000
0.001
Remark Current
setting
of
differential
current
differential
current alarm Slope
of
protection s
Time delay of stub differential protection Enabling/disabling stub differential
5
87STB.En
protection
0 or 1
1: enable 0: disable Enabling/disabling
6
87STB.En_Alm
differential
current alarm function
0 or 1
1: enable 0: disable Enabling/disabling stub differential protection controlled by CT circuit
7
87STB.En_CTS_Blk
0 or 1
failure 1: enable 0: disable
3.24 Dead Zone Protection 3.24.1 General Application Generally, fault current is very large when multi-phase fault occurs between CT and circuit breaker (i.e. dead zone) and it will have a greater impact on the system. Breaker failure protection can operate after a longer time delay, in order to clear the dead zone fault quickly and improve the system stability, dead zone protection with shorter time delay (compared with breaker failure protection) is adopted. NOTICE! For double circuit breakers mode, the device will provide indenpendent dead zone protection for CB1 and CB2 respectively. Both dead zone protections have the same logic.The difference is that the prefix “CBx.” is added to all signals and settings for circuit breaker No.x (x=1 or 2).
3.24.2 Function Description For some wiring arrangement (for example, circuit breaker is located between CT and the line), if fault occurs between CT and circuit breaker, line protection can operate to trip circuit breaker quickly, but the fault have not been cleared since local circuit breaker is tripped. Here dead zone protection is needed in order to trip relevant circuit breaker. The criterion for dead zone protection is: when dead zone protection is enabled, binary input of initiating dead zone protection is energized (by default, three-phase tripping signal is used to 3-217
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initiate dead zone protection), if overcurrent element for dead zone protection operates, then corresponding circuit breaker is tripped and three phases normally closed contact of the circuit breaker are energized, dead zone protection will operate to trip adjacent circuit breaker after a time delay.
3.24.3 Function Block Diagram 50DZ CBx.50DZ.En1
CBx.50DZ.On
CBx.50DZ.En2
CBx.50DZ.Op
CBx.50DZ.Blk
CBx.50DZ.St
CBx.50DZ.Init
3.24.4 I/O Signal Table 3.24-1 I/O signals of dead zone protection No.
Input Signal
Description
1
CBx.50DZ.En1
Dead zone protection enabling input 1, it can be binary inputs or logic link.
2
CBx.50DZ.En2
Dead zone protection enabling input 2, it can be binary inputs or logic link.
3
CBx.50DZ.Blk
4
CBx.50DZ.Init
No.
Dead zone protection blocking input, such as function blocking binary input. When the input is 1, dead zone protection is reset and time delay is cleared. Initiation signal input of the dead zone protection.
Output Signal
Description
1
CBx.50DZ.On
Dead zone protection is enabled.
2
CBx.50DZ.St
Dead zone protection starts.
3
CBx.50DZ.Op
Dead zone protection operates.
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3.24.5 Logic EN
[CBx.50DZ.En]
SIG
CBx.50DZ.En1
SIG
CBx.50DZ.En2
SIG
CBx.50DZ.Blk
& & CBx.50DZ.On
&
CBx.50DZ.St
& [CBx.50DZ.t_Op]
SIG
FD.Pkp
SIG
CBx.52b_PhA
SIG
CBx.52b_PhB
SIG
CBx.52b_PhC
SET
Ia > [CBx.50DZ.I_Set]
SET
Ib > [CBx.50DZ.I_Set]
SET
Ic > [CBx.50DZ.I_Set]
SIG
CBx.50DZ.Init
SIG
CBx.Trp
0ms
CBx.50DZ.Op
&
>=1
&
>=1
Figure 3.24-1 Dead zone protection
3.24.6 Settings Table 3.24-2 Settings of dead zone protection No.
Name
Range
Step
Unit
Remark Current
1
CBx.50DZ.I_Set
(0.050~30.000)×In
0.001
A
setting
for
dead
zone
protection. This setting shall ensure the protection being sensitive enough if dead zone fault occurs.
2
CBx.50DZ.t_Op
0.000~10.000
0.001
s
Time delay of dead zone protection. Enabling/disabling
3
CBx.50DZ.En
0 or 1
-
dead
zone
protection. 1: enable 0: disable
3.25 Pole Discrepancy Protection 3.25.1 General Application The pole discrepancy of circuit breaker may occur during operation of a breaker with segregated operating gears for the three phases. The reason could be an interruption in the tripping/closing circuits, or mechanical failure. A pole discrepancy can only be tolerated for a limited period. When there is loading, zero-sequence or negative-sequence current will be generated in the power system, which will result in overheat of the generator or the motor. With the load current increasing, overcurrent elements based on zero-sequence current or negative-sequence current may operate. 3-219
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Pole discrepancy protection is required to operate before the operation of these overcurrent elements. NOTICE! For double circuit breakers mode, the device will provide indenpendent pole discrepancy protection for CB1 and CB2 respectively. Both pole discrepancy protections have the same logic.The difference is that the prefix “CBx.” is added to all signals and settings for circuit breaker No.x (x=1 or 2).
3.25.2 Function Description Pole discrepancy protection determines three-phase breaker pole discrepancy condition by its phase segregated CB auxiliary contacts. In order to improve the reliability of pole discrepancy protection, the asymmetrical current component can be selected as addition criteria when needed.
3.25.3 Function Block Diagram 62PD CBx.62PD.En1
CBx.62PD.On
CBx.62PD.En2
CBx.62PD.Op
CBx.62PD.Blk
CBx.62PD.St
3.25.4 I/O Signals Table 3.25-1 I/O signals of pole discrepancy protection No.
Input Signal
1
CBx.62PD.En1
2
CBx.62PD.En2
3
CBx.62PD.Blk
No.
Description Pole discrepancy protection enabling input 1, it is triggered from binary input or programmable logic etc. Pole discrepancy protection enabling input 2, it is triggered from binary input or programmable logic etc. Pole discrepancy protection blocking input, it is triggered from binary input or programmable logic etc.
Output Signal
Description
1
CBx.62PD.On
Pole discrepancy protection is enabled.
2
CBx.62PD.Op
Pole discrepancy protection operates to trip
3
CBx.62PD.St
Pole discrepancy protection starts
3.25.5 Logic Phase-segregated circuit breaker auxiliary contacts are connected to the device. When the state of three phase-segregated circuit breaker auxiliary contacts are inconsistent, pole discrepancy protection will be started and initiate output after a time delay [CBx.62PD.t_Op].
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Pole discrepancy protection can be blocked by external input signal [62PD.Blk]. In general, this input signal is usually from the output of 1-pole AR initiation, so as to prevent pole discrepancy protection from operation during 1-pole AR initiation. SIG
CBx.62PD.En1
SIG
CBx.62PD.En2
EN
[CBx.62PD.En]
SIG
CBx.62PD.Blk
SIG
FD.Pkp
& & 62PD.On
&
EN
[CBx.62PD.En_3I0/I2_Ctrl]
SET
3I0>[CBx.62PD.3I0_Set]
SET
I2>[CBx.62PD.I2_Set]
BI
[CBx.52b_PhA]
>=1 >=1
& &
SIG
CBx.Ia[46BC.I_Min] >=1
SET
Ib>[46BC.I_Min]
SET
Ic>[46BC.I_Min]
SET
SET
&
I2/I1>[46BC.I2/I1_Set]
46BC.Op
[46BC.En_Trp] & 46BC.Alm
SET
[46BC.En_Alm]
Figure 3.26-1 Logic diagram of broken conductor protection 3-223
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3.26.6 Settings Table 3.26-2 Settings of broken conductor protection No.
Name
Range
Step
Unit
Remark Ratio
1
46BC.I2/I1_Set
0.20~1.00
0.001
setting
(negative-sequence
current to positive-sequence current) of broken conductor protection
2
46BC.t_Op
0.000~600.000
0.001
s
3
46BC.I_Min
(0.050~30.000)×In
0.001
A
Time
delay
of
broken
conductor
protection Minimum operation current of broken conductor protection Enabling/disabling broken conductor
4
46BC.En_Trp
protection to operate to trip
0 or 1
0: disable 1: enable Enabling/disabling broken conductor
5
46BC.En_Alm
protection to operate to alarm
0 or 1
0: disable 1: enable
3.27 Reverse Power Protection 3.27.1 General Application Due to various reasons lead to lose motivity, synchronous generator is changed to run as a motor state, Absorbing energy from the power grid to drive a turbine (gas turbine) operation. In order to prevent turbine blade or gas turbine gear from being damaged, reverse power protection (reversal direction) should be configured.
3.27.2 Function Description Reverse power protection provides two stages: stage 1 can be set as alarm purpose or tripping purpose, and stage 2 is only for tripping purpose. When reverse power value of the generator detected is greater than reverse power protection setting ([32R1.P_Set]), reverse power protection can operate to alarm or trip with the time delay. After overload protection, over-excitation protection or loss-of-excitation protection, such as abnormal operation protection operates, the generator needs sequential tripping. The steam valve of turbine has to be closed firstly, and sequential tripping reverse power protection blocked by position contact of steam valve and circuit breaker operates to trip with the time delay. Generator power is calculated by three-phase voltage and three-phase current of generator terminal. Positive sequence component of active power is calculated by fundamental wave of the voltage and current. The benefits is that reverse power protection is independent of the asymmetric component, so as to truly reflect the load of the engine power system. The level of generator absorbing the active power will depend on the need to overcome the friction loss, according to different types of generator units, the settings of reverse power protection will be 3-224
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different. During testing in the primary side of the generator unit, the active power absorbed by the generator can be measured by the device. When the device is equipped with power plant side, reverse power is negative value, and reverse power is positive value when it is equipped with substation side. The operation criterion: [32R.Opt_Dir]=Reverse AND P[32Rx.P_Set]
3.27.3 Function Block Diagram 32R 32Rx.En
P1
32Rx.Blk
32Rx.On 32Rx.St 32Rx.Op 32R1.Alm
3.27.4 I/O Signals Table 3.27-1 I/O signals of reverse power protection No.
Input Signal
1
32Rx.En
2
32Rx.Blk
No.
Description Enable stage x of reverse power protection input 1, it is triggered from binary input or programmable logic etc. (x=1, 2) Stage x of reverse power protection blocking input, it is triggered from binary input or programmable logic etc. (x=1, 2)
Output Signal
Description
1
P1
Positive-sequence active power
2
32Rx.On
Stage x of reverse power protection is enabled. (x=1, 2)
3
32Rx.St
Stage x of reverse power protection starts. (x=1, 2)
4
32Rx.Op
Stage x of reverse power protection operates to trip. (x=1, 2)
5
32R1.Alm
Stage 1 of reverse power protection operates to alarm. (x=1, 2)
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3.27.5 Logic SIG
32R1.En
SIG
32R1.Blk
EN
[32R1.En_Alm]
EN
[32R1.En_Trp]
SIG
32R1.On
SET
[32R.Opt_Dir]=Reverse
SIG
P1[32R1.P_Set]
32R1.On
>=1
& & 32R1.St
>=1 &
& EN
[32R1.t_Alm]
0s
32R1.Alm
[32R1.t_Trp]
0s
32R1.Op
[32R1.En_Alm]
& EN
[32R1.En_Trp]
Figure 3.27-1 Logic diagram of stage 1 of reverse power protection SIG
32R2.En
SIG
32R2.Blk
EN
[32R2.En_Trp]
SIG
32R2.On
SET
[32R.Opt_Dir]=Reverse
SIG
P1[32R2.P_Set]
& & 32R2.On
& 32R2.St
& >=1 &
& [32R2.t_Trp]
EN
0s
32R2.Op
[32R2.En_Trp]
Figure 3.27-2 Logic diagram of stage 2 of reverse power protection
When stage 2 of reverse power protection is used as sequential tripping reverse power protection, it can be selectable to be controlled by position contact of steam valve and circuit breaker
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3.27.6 Settings Table 3.27-2 Settings of broken conductor protection No.
Name
Range
Step
Unit
Remark Power setting of stage 1 of reverse
1
32R1.P_Set
(0.100~50.000)×In
0.01
W
power protection It should be greater 0.5 times the measured value of reverse power.
2
32R1.t_Alm
0.100~3000.000
0.01
s
3
32R1.t_Trp
0.100~3000.000
0.01
s
Time delay of stage 1 of reverse power protection for alarm purpose Time delay of stage 1 of reverse power protection for tripping purpose Enabling/disabling stage 1 of reverse
4
32R1.En_Trp
power protection to operate to trip
0 or 1
0: disable 1: enable Enabling/disabling stage 1 of reverse
5
32R1.En_Alm
power protection to operate to alarm
0 or 1
0: disable 1: enable Power setting of stage 2 of reverse
6
32R2.P_Set
(0.100~50.000)×In
0.01
W
power protection It should be greater 0.5 times the measured value of reverse power.
7
32R2.t_Trp
0.100~3000.000
0.01
s
Time delay of stage 2 of reverse power protection Enabling/disabling stage 2 of reverse
8
32R2.En_Trp
power protection to operate to trip
0 or 1
0: disable 1: enable
9
32R.Opt_Dir
The
Forward
directionality
direction
Reverse
or
option
reverse
(forward
direction)
of
reverse power protection
3.28 Synchrocheck 3.28.1 General Application The purpose of synchrocheck is to ensure two systems are synchronism before they are going to be connected. When two asynchronous systems are connected together, due to phase difference between the two systems, larger impact will be led to the system during closing. Thus auto-reclosing and manual closing are applied with the synchrocheck to avoid this situation and maintain the system stability. The synchrocheck includes synchronism check and dead charge check. 3-227
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NOTICE! For double circuit breakers mode, the device will provide indenpendent synchrocheck function for CB1 and CB2 respectively. Both synchrocheck functions have the same logic.The difference is that the prefix “CBx.” is added to all signals and settings for circuit breaker No.x (x=1 or 2).
3.28.2 Function Description The synchronism check function is mainly to measure the electrical quantities between both sides of the circuit breaker and compares them with the corresponding settings. The output is only given if all measured quantities are simultaneously within their set limits. The dead charge check function measures the amplitude of line voltage and bus voltage between both sides of the circuit breaker, and then compare them with the live check setting [CBx.25.U_Lv] and the dead check setting [CBx.25.U_Dd]. The output is only given when the measured quantities comply with the criteria. The synchrocheck in this device can be used for auto-reclosing and manual closing for both single circuit breaker and dual circuit breakers. When applied for single circuit breaker, the comparison relationship between reference voltage (CBx.Uref) and synchronism voltage (CBx.Usyn) for synchronism check is as shown in Figure 3.28-1. CBx.Uref
CBx.Usyn
Figure 3.28-1 Relationship between reference voltage and synchronism voltage
When both line and busbar are live, the synchronism check element operates if voltage difference, phase angle difference and frequency difference are all within their setting values. 1.
The voltage difference is checked by the following equations.
CBx.Usyn≥[CBx.25.U_Lv] CBx.Uref≥[CBx.25.U_Lv] [CBx.25.U_Diff]≥|CBx.Usyn-CBx.Uref| 2.
The phase difference is checked by the following equations.
CBx.Usyn×CBx.Uref×cosØ≥0
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CBx.Usyn×CBx.Uref×sin([CBx.25.phi_Diff])≥CBx.Usyn×CBx.Uref×|sinØ| Where, Ø is phase difference between Usyn and Uref 3.
The frequency difference is checked by the following equations.
|f(CBx.Usyn)-f(CBx.Uref)|≤[CBx.25.f_Diff] If frequency check is disabled (i.e. [CBx.25.En_fDiffChk] is set as “0”), a detected maximum slip cycle can also be determined by the following equation based on phase difference setting and the synchronism check time setting: f =[CBx.25.phi_Diff]/(180×[CBx.25.t_SynChk]) Where: f is slip cycle If frequency check is enabled (i.e. [CBx.25.En_fDiffChk] is set as “1”), [CBx.25.t_SynChk] can be set to be a very small value (default value is 50ms). This function module supports voltage switching. In general, voltage switching is fulfilled by external circuit, and the busbar arrangement should be determined, including three options, single busbar arrangement, double busbars arrangement and 1½ breakers arrangement, if using this module to fulfill voltage switching. Analog input defines four voltage inputs, UL1, UB1, UL2, UB2, and their usage are as follow: UL1: it connects with three-phase protection voltages (from line or busbar), which mainly are used by distance protection, voltage protection and so on. UB1: it connects with single synchronism voltage (from line or busbar). UL2: it connects with single synchronism voltage (from the other line of the same diameter in 1½ breakers arrangement). When voltage switching is available, it is only used by 1½ breakers arrangement. UB2: it connects with single synchronism voltage (from busbar). When voltage switching is available, it is only used by double busbars arrangement and 1½ breakers arrangement. The reference voltage (Uref) is determined to use phase voltage or phase-to-phase voltage (UL1) from three-phase protection voltages and by the setting [CBx.25.Opt_Source_UL1]. The synchronism voltage (Usyn) always connects with UB1 if not adopting voltage switching. It connects with one of UB1, UL2 and UB2 according to the result of voltage switching if adopting voltage switching. 3.28.2.1 Single Busbar Arrangement Voltage selection function is not required for this busbar arrangement, the connection of the voltage signals and respective VT MCB auxiliary contacts to the device is shown in the Figure 3.28-2 and Figure 3.28-3. 3-229
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1.
Three-phase bus voltage used for protection ([CBx.VTS.En_LineVT]=0) Bus
UL1
Ua CB
Ub Uc
25.MCB_VT_UL1
UB1 25.MCB_VT_UB1
Line
Figure 3.28-2 Voltage connection for single busbar arrangement
2.
Three-phase line voltage used for protection ([CBx.VTS.En_LineVT]=1) Bus
CB
UB1 25.MCB_VT_UB1
UL1
Ua Ub Uc
25.MCB_VT_UL1
Line
Figure 3.28-3 Voltage connection for single busbar arrangement
In the figures, the setting [CBx.VTS.En_LineVT] is used to determine protection voltage signals (Ua, Ub, Uc) from line VT or bus VT according to the condition.
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3.28.2.2 Double Busbars Arrangement Bus2 Bus1
B1D B2D
UB1 25.MCB_VT_UB1 UB2 25.MCB_VT_UB2 25.NC_UB1DS 25.NO_UB1DS
CB
25.NC_UB2DS 25.NO_UB2DS
UL1
Ua Ub
Line
Uc
25.MCB_VT_UL1
Figure 3.28-4 Voltage connection for double busbars arrangement
For double busbars arrangement, selection of appropriate voltage signals from Bus 1 and Bus 2 for synchronizing are required. Line VT signal is taken as reference to check synchronizing with the voltage after voltage selection function. Selection approach is as follows. For the disconnector positions, the normally open (NO) and normally closed (NC) contacts of the disconnector for bus 1 and bus 2 are required to determine the disconnector open and closed positions. The voltage selection logic is as follows. 25.NC_UB1DS
BI
25.NO_UB1DS
BI
25.NC_UB2DS
BI
25.NO_UB2DS
&
&
Voltage Selection Logic
BI
CBx.UB1_Sel
CBx.UB2_Sel
& CBx.Alm_Invalid_Sel
UB1
CBx.Usyn
UB2
Figure 3.28-5 Voltage selection for double busbars arrangement
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After acquiring the disconnector open and closed positions of double busbars, use the following logic to acquire the feeder voltage of double busbars. DS2 CLOSED
DS2 OPEN
DS1 CLOSED
Keep original value
Voltage from Bus 1 VT (CBx.UB1_Sel=1)
DS1 OPEN
Voltage from Bus 2 VT (CBx.UB2_Sel=1)
Keep original value
DS1 is disconnector of Bus 1 DS2 is disconnector of Bus 2 If voltage selection is invalid (CBx.Alm_Invalid_Sel=1), keep original selection and without switchover. 3.28.2.3 One and A Half Breakers Arrangement For one and a half breakers arrangement, selection of appropriate voltage signals among Line1 VT, Line2 VT and Bus 2 VT as reference voltage to check synchronizing with Bus 1 voltage signal for closing breaker at Bus 1 side. Bus1
UB1 25.MCB_VT_UB1 25.NC_UB1DS
B1D
25.NO_UB1DS
UL1
Ua
Line 1
Ub Uc
25.MCB_VT_UL1
L1D
25.NC_UL1DS 25.NO_UL1DS
Line 2
UL2 25.MCB_VT_UL2 25.NC_UL2DS 25.NO_UL2DS L2D
25.NC_UB2DS 25.NO_UB2DS UB2 25.MCB_VT_UB2 B2D Bus2
Figure 3.28-6 Voltage connection for one and a half breakers arrangement 3-232
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For the circuit breaker at bus side (take bus breaker of bus 1 as an example), the device acquires the disconnector open and closed positions of two feeders and bus 2. The voltage selection logic is as follows. BI
25.NC_UL1DS
& CBx.UL1_Sel
BI
25.NO_UL1DS
BI
25.NC_UL2DS
BI
25.NO_UL2DS
BI
25.NC_UB2DS
BI
25.NO_UB2DS
& CBx.UL2_Sel
& &
CBx.UB2_Sel
& &
CBx.Alm_Invalid_Sel
UL1
CBx.Uref
UL2 UB2 UB1
CBx.Usyn
Figure 3.28-7 Voltage selection for one and a half breakers arrangement
For the tie breaker, the device acquires the disconnector open and closed positions of two feeders and two busbars. Either Line 1 VT or Bus 1 VT signal is selected as reference voltage to check synchronizing with the selected voltage between Line 2 VT and Bus 2 VT. The voltage selection logic is as follows.
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25.NC_UL1DS
& CBx.UL1_Sel
BI
25.NO_UL1DS
BI
25.NC_UB1DS
BI
25.NO_UB1DS
& CBx.UB1_Sel
& &
UL1
CBx.Uref
UB1 BI
25.NC_UL2DS
BI
25.NO_UL2DS
BI
25.NC_UB2DS
BI
25.NO_UB2DS
& CBx.UL2_Sel
& CBx.UB2_Sel
& >=1 &
UL2
CBx.Alm_Invalid_Sel
CBx.Usyn
UB2
Figure 3.28-8 Voltage selection for one and a half breakers arrangement
When the voltage selection fails (including VT circuit failure and MCB failure), the device will issue the corresponding failure signal. If the voltage selection is invalid (CBx.Alm_Invalid_Sel=1), keep original selection and without switchover. In order to simplify description, one of the two voltages used in the synchrocheck (synchronism check and dead charge check) which obtained after voltage selection function is regarded as line voltage, and another is bus voltage. 3.28.2.4 Synchronism Voltage Circuit Failure Supervision If synchronism voltage and reference voltage are used for auto-reclosing with synchronism or dead line or busbar check, the VT circuit of synchronism voltage and reference voltage are monitored. Under normal conditions, the circuit breaker is in closed position but the synchronism voltage is lower than the setting [CBx.25.U_Lv], it means that synchronism voltage circuit fails and an alarm [CBx.25.Alm_VTS_Usyn] or [CBx.25.Alm_VTS_Uref] will be issued with a time delay of 10s. If MCB of synchronism voltage or reference voltage is open, an alarm [CBx.25.Alm_VTS_Usyn] or [CBx.25.Alm_VTS_Uref] will be issued instantaneously. After synchronism voltage reverted to normal condition, the alarm will be reset automatically with a time delay of 10s. When synchronism voltage circuit failure is detected, dead check in auto-reclosing logic will be disabled. If the logic setting [CBx.25.En_NoChk] is set as “1”, synchronism voltage circuit failure supervision will be 3-234
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disabled. SIG
FD.Pkp
SIG
CBx.79.Inprog
SIG
CBx.Uref=1 & 10s
10s
>=1 & CBx.25.Alm_VTS_Uref
>=1 >=1 &
Figure 3.28-9 Reference voltage circuit failure supervision logic SIG
FD.Pkp
SIG
CBx.79.Inprog
SIG
CBx.Usyn=1 & 10s
10s
>=1 & CBx.25.Alm_VTS_Usyn
>=1 >=1 &
Figure 3.28-10 Synchronism voltage circuit failure supervision logic
As shown in Figure 3.28-9 and Figure 3.28-10, 25.MCB_VT_Uref is MCB signal corresponding to reference voltage after switching and 25.MCB_VT_Usyn is MCB signal corresponding to synchronism voltage after switching.
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3.28.3 Function Block Diagram 25 CBx.25.Blk_Chk
CBx.UL1_Sel
CBx.25.Blk_SynChk
CBx.UL2_Sel
CBx.25.Blk_DdChk
CBx.UB1_Sel
CBx.25.Start_Chk
CBx.UB2_Sel
CBx.25.Start_3PLvChk CBx.25.Sel_SynChk
CBx.Alm_Invalid_Sel CBx.25.Ok_fDiffChk
CBx.25.Sel_DdL_DdB
CBx.25.Ok_UDiffChk
CBx.25.Sel_DdL_LvB
CBx.25.Ok_phiDiffChk
CBx.25.Sel_LvL_DdB
CBx.25.Ok_DdL_DdB
CBx.25.Sel_NoChk
CBx.25.Ok_DdL_LvB
CBx.25.Blk_VTS_Uref
CBx.25.Ok_LvL_DdB
CBx.25.Blk_VTS_Usyn
CBx.25.Chk_LvL
25.MCB_VT_UL1
CBx.25.Chk_DdL
25.MCB_VT_UL2
CBx.25.Chk_LvB
25.MCB_VT_UB1
CBx.25.Chk_DdB
25.MCB_VT_UB2
CBx.25.Ok_DdChk
25.NC_UL1DS
CBx.25.Ok_SynChk
25.NO_UL1DS
CBx.25.Ok_Chk
25.NC_UB1DS
CBx.25.Ok_3PLvChk
25.NO_UB1DS
CBx.25.Alm_VTS_Uref
25.NC_UL2DS
CBx.25.Alm_VTS_Usyn
25.NO_UL2DS
CBx.25.f_Ref
25.NC_UB2DS
CBx.25.f_Syn
25.NO_UB2DS
CBx.25.U_Diff CBx.25.f_Diff CBx.25.Phi_Diff
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3.28.4 I/O Signals Table 3.28-1 I/O signals of synchrocheck No.
Input Signal
Description
1
CBx.25.Blk_Chk
2
CBx.25.Blk_SynChk
3
CBx.25.Blk_DdChk
4
CBx.25.Start_Chk
5
CBx.25.Start_3PLvChk
6
CBx.25.Sel_ SynChk
Synchronism check is selected.
7
CBx.25.Sel_DdL_DdB
Dead line and dead bus check is selected.
8
CBx.25.Sel_DdL_LvB
Dead line and live bus check is selected.
9
CBx.25.Sel_ LvL_DdB
Live line and live bus check is selected.
10
CBx.25.Sel_ NoChk
No check is selected.
11
CBx.25.Blk_VTS_Usyn
VT circuit supervision (Usyn) is blocked
12
CBx.25.Blk_VTS_Uref
VT circuit supervision (Uref) is blocked
13
25.MCB_VT_UL1
Binary input for VT MCB auxiliary contact (UL1)
14
25.MCB_VT_UL2
Binary input for VT MCB auxiliary contact (UL2)
15
25.MCB_VT_UB1
Binary input for VT MCB auxiliary contact (UB1)
16
25.MCB_VT_UB2
Binary input for VT MCB auxiliary contact (UB2)
17
25.NC_UL1DS
Normally closed contact of disconnector (UL1)
18
25.NO_UL1DS
Normally open contact of disconnector (UL1)
19
25.NC_UB1DS
Normally closed contact of disconnector (UB1)
20
25.NO_UB1DS
Normally open contact of disconnector (UB1)
21
25.NC_UL2DS
Normally closed contact of disconnector (UL2)
22
25.NO_UL2DS
Normally open contact of disconnector (UL2)
23
25.NC_UB2DS
Normally closed contact of disconnector (UB2)
24
25.NO_UB2DS
Normally open contact of disconnector (UB2)
No.
Input signal of blocking synchrocheck function for AR. Input signal of blocking synchronism check for AR. If the value is “1”, the output of synchronism check is “0”. Input signal of blocking dead charge check for AR. Input signal of starting synchronism check, usually it was starting signal of AR from auto-reclosing module. Input signal of starting live three-phase check, usually it was starting signal of 1-pole AR
Output Signal
Description
1
CBx.UL1_Sel
To select voltage of Line 1
2
CBx.UL2_Sel
To select voltage of Line 2
3
CBx.UB1_Sel
To select voltage of Bus 1
4
CBx.UB2_Sel
To select voltage of Bus 2
5
CBx.Alm_Invalid_Sel
Voltage selection is invalid.
6
CBx.25.Ok_fDiffChk
7
CBx.25.Ok_UDiffChk
8
CBx.25.Ok_phiDiffChk
To indicate that frequency difference condition for synchronism check of AR is met, frequency difference between UB and UL is smaller than [25.f_Diff]. To indicate that voltage difference condition for synchronism check of AR is met, voltage difference between UB and UL is smaller than [25.U_Diff] To indicate phase difference condition for synchronism check of AR is met, phase difference between UB and UL is smaller than [25.phi_Diff].
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CBx.25.Ok_DdL_DdB
Dead line and dead bus condition is met
10
CBx.25.Ok_DdL_LvB
Dead line and live bus condition is met
11
CBx.25.Ok_LvL_DdB
Live line and dead bus condition is met
12
CBx.25.Chk_LvL
Line voltage is greater than the voltage setting [25.U_Lv]
13
CBx.25.Chk_DdL
Line voltage is smaller than the voltage setting [25.U_Dd]
14
CBx.25.Chk_LvB
Bus voltage is greater than the voltage setting [25.U_Lv]
15
CBx.25.Chk_DdB
Bus voltage is smaller than the voltage setting [25.U_Dd]
16
CBx.25.Ok_DdChk
To indicate that dead charge check condition of AR is met
17
CBx.25.Ok_SynChk
To indicate that synchronism check condition of AR is met
18
CBx.25.Ok_Chk
To indicate that synchrocheck condition of AR is met
19
CBx.25.Ok_3PLvChk
To indicate that live three-phase check condition is met
20
CBx.25.Alm_VTS_Uref
Reference voltage circuit is abnormal
21
CBx.25.Alm_VTS_Usyn
Synchronism voltage circuit is abnormal
22
CBx.25.f_Ref
Frequency of the voltage used by protection calculation
23
CBx.25.f_Syn
Frequency of the voltage used by synchrocheck
24
CBx.25.U_Diff
Voltage difference for synchronism check
25
CBx.25.f_Diff
Frequency difference for synchronism check
26
CBx.25.phi_Diff
Phase difference for synchronism check
3.28.5 Logic 3.28.5.1 Synchronism Check Logic The frequency difference, voltage difference, and phase difference of voltages from both sides of the circuit breaker are calculated in the device, they are used as input conditions of the synchronism check. When the synchronism check function is enabled and the voltages of both ends meets the requirements of the voltage difference, phase difference, and frequency difference, and there is no synchronism check blocking signal, it is regarded that the synchronism check conditions are met. Synchronism check logic is usually used for 3-pole AR, and 1-pole AR usually adopts no check logic. However, the circuit breaker at local end can not reclosed unless the circuit breaker at remote end is reclosed successfully. In order to meet this requirement, live three-phase check can be used for 1-pole AR, determined by the setting [CBx.25.En_3PLvChk], ensure that three-phase voltages is restored to normal at local end after the circuit breaker at remote end is reclosed. Synchrocheck mode can be determined by the setting [CBx.25.SetOpt] or external signal. As shown in Figure 3.28-11, when the setting [CBx.25.SetOpt] is set as “1”, synchrocheck mode is determined by the setting. Otherwise, synchrocheck mode is determined by external signal.
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EN
[CBx.25.En_SynChk]
SIG
CBx.25.Sel_SynChk
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_DdL_DdB]
SIG
CBx.25.Sel_SynChk
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_LvL_DdB]
SIG
CBx.25.Sel_LvL_DdB
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_DdL_LvB]
CBx.25.On_SynChk 0
1 CBx.25.On_DdL_DdB 0
1 CBx.25.On_LvL_DdB 0
1 CBx.25.On_DdL_LvB
SIG
CBx.25.Sel_DdL_LvB
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_NoChk]
SIG
CBx.25.Sel_NoChk
EN
[CBx.25.SetOpt]
0
1 CBx.25.On_NoChk 0
Figure 3.28-11 Synchrocheck mode selection EN
[CBx.25.En_3PLvChk]
>=1
SIG CBx.Uref.a>[CBx.25.U_Lv]
&
SIG CBx.Uref.b>[CBx.25.U_Lv] SIG CBx.Uref.c>[CBx.25.U_Lv]
& 200ms
SIG CBx.25.Start_3PLvChk
SIG CBx.25.Blk_Chk
0ms
CBx.25.Ok_3PLvChk
>=1 &
SIG CBx.25.Blk_SynChk
&
SIG CBx.25.On_SynChk SIG CBx.25.Start_Chk SIG CBx.Usyn>[CBx.25.U_Lv] SIG CBx.Uref>[CBx.25.U_Lv]
&
& 50ms
0ms
&
[CBx.25.t_SynChk]
0ms
CBx.25.Ok_SynChk
SIG CBx.25.Ok_UdiffChk SIG CBx.25.Ok_phiDiffChk SIG CBx.25.Ok_fDiffChk
Figure 3.28-12 Synchronism check
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3.28.5.2 Dead Charge Check Logic The dead charge check conditions have three types, namely, live-bus and dead-line check, dead-bus and live-line check and dead-bus and dead-line check. The above three modes can be enabled and disabled by the corresponding logic settings. The device can calculate the measured bus voltage and line voltage at both sides of the circuit breaker and compare them with the settings [CBx.25.U_Lv] and [CBx.25.U_Dd]. When the voltage is higher than [CBx.25.U_Lv], the bus/line is regarded as live. When the voltage is lower than [CBx.25.U_Dd], the bus/line is regarded as dead. SIG
CBx.25.Blk_Chk
SIG
CBx.25.Blk_DdChk
>=1 & & [CBx.25.t_DdChk]
>=1
SIG
CBx.25.Start_Chk
SIG
CBx.25.On_DdL_DdB
SIG
CBx.Uref=1 CBx.25.Ok_Chk
Figure 3.28-14 Synchrocheck logic
3.28.6 Settings Table 3.28-2 Synchrocheck settings No.
Name
1
CBx.25.Opt_Source_UL1
Range
Step
Ua
Unit
Remark Voltage selecting mode of line 1.
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Name
Range
Step
Unit
Remark
Ub
Ua: A-phase voltage
Uc
Ub: B-phase voltage
Uab
Uc: C-phase voltage
Ubc
Uab: AB-phase voltage
Uca
Ubc: BC-phase voltage Uca: CA-phase voltage Voltage selecting mode of bus 1.
Ua
Ua: A-phase voltage
Ub 2
CBx.25.Opt_Source_UB1
Ub: B-phase voltage
Uc
Uc: C-phase voltage
Uab
Uab: AB-phase voltage
Ubc
Ubc: BC-phase voltage
Uca
Uca: CA-phase voltage Voltage selecting mode of line 2.
Ua
Ua: A-phase voltage
Ub 3
CBx.25.Opt_Source_UL2
Ub: B-phase voltage
Uc
Uc: C-phase voltage
Uab
Uab: AB-phase voltage
Ubc
Ubc: BC-phase voltage
Uca
Uca: CA-phase voltage Voltage selecting mode of bus 2.
Ua
Ua: A-phase voltage
Ub 4
CBx.25.Opt_Source_UB2
Ub: B-phase voltage
Uc
Uc: C-phase voltage
Uab
Uab: AB-phase voltage
Ubc
Ubc: BC-phase voltage
Uca
Uca: CA-phase voltage Option
of
circuit
breaker
configuration, and it should be set as “NoVoltSel” if no voltage selection is adopted.
5
NoVoltSel
DblBusOneCB:
DblBusOneCB
breaker for double busbar
3/2BusCB
3/2BusCB:
3/2TieCB
breaker for one and a half
CBx.CBConfigMode
bus
one
side
circuit
circuit
breakers 3/2TieCB:
line
side
circuit
breaker for one and a half breakers 6
CBx.25.U_Dd
0.05Un~0.8Un
0.001
V
Voltage threshold of dead check
7
CBx.25.U_Lv
0.5Un~Un
0.001
V
Voltage threshold of live check
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Name
Range
8
CBx.25.K_Usyn
0.20-5.00
9
CBx.25.phi_Diff
0~ 89
Step
Unit
Remark Compensation
coefficient
synchronism voltage 1
deg
Phase
difference
CBx.25.phi_Comp
0~359
1
deg
limit
of
synchronism check for AR Compensation
10
for
difference
for
phase
between
two
synchronism voltages 11
CBx.25.f_Diff
0.02~1.00
0.01
Hz
12
CBx.25.U_Diff
0.02Un~0.8Un
V
13
CBx.25.t_DdChk
0.010~25.000
s
14
CBx.25.t_SynChk
0.010~25.000
s
Frequency difference limit of synchronism check for AR Voltage
difference
CBx.25.En_fDiffChk
of
synchronism check for AR Time delay to confirm dead check condition Time
delay
to
confirm
synchronism check condition Enabling/disabling
15
limit
frequency
difference check
0 or 1
0: disable 1: enable Synchrocheck mode selection
16
CBx.25.SetOpt
0, 1
1
0: determined by external signal 1: determined by the setting Enabling/disabling synchronism
17
CBx.25.En_SynChk
check
0 or 1
0: disable 1: enable Enabling/disabling dead line and
18
CBx.25.En_DdL_DdB
dead bus (DLDB) check
0 or 1
0: disable 1: enable Enabling/disabling dead line and
19
CBx.25.En_DdL_LvB
live bus (DLLB) check
0 or 1
0: disable 1: enable Enabling/disabling live line and
20
CBx.25.En_LvL_DdB
dead bus (LLDB) check
0 or 1
0: disable 1: enable Enabling/disabling AR without
21
CBx.25.En_NoChk
any check
0 or 1
0: disable 1: enable
22
CBx.25.En_3PLvChk
0 or 1
Enabling/disabling
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Name
Range
Step
Unit
Remark three-phase check of line 0: disable 1: enable
3.29 Automatic Reclosure 3.29.1 General Application To maintain the integrity of the overall electrical transmission system, the device is installed on the transmission system to isolate faulted segments during system disturbances. Faults caused by lightning, wind, or tree branches could be transient in nature and may disappear once the circuit is de-energized. According to statistics, for overhead transmission line, 80%~90% of the faults on overhead lines are the transient faults. Auto-reclosing systems are installed to restore the faulted section of the transmission system once the fault is extinguished (providing it is a transient fault). For certain transmission systems, auto-reclosure is used to improve system stability by restoring critical transmission paths as soon as possible. Besides overhead lines, other equipment failure, such as cables, busbar, transformer fault and so on, are generally permanent fault, and auto-reclosing is not initiated after faulty feeder is tripped. For some mixed circuits, such as overhead line with a transformer unit, hybrid transmission lines, etc., it is required to ensure that auto-reclosing is only initiated for faults overhead line section, or make a choice according to the situation. NOTICE! For double circuit breakers mode, the device will provide indenpendent automatic reclosure function for CB1 and CB2 respectively. Both automatic reclosure functions have the same logic.The difference is that the prefix “CBx.” is added to all signals and settings for circuit breaker No.x (x=1 or 2).
3.29.2 Function Description This auto-reclosing logic can be used with either integrated device or external device. When the auto-reclosure is used with integrated device, the internal protection logic can initiate AR, moreover, a tripping contact from external device can be connected to the device via opto-coupler input to initiate integrated AR function. When external auto-reclosure is used, the device can output some configurable output to initiate external AR, such as, contact of initiating AR, phase-segregated tripping contact, single-phase tripping contact, three-phase tripping contact and contact of blocking AR. According to requirement, these contacts can be selectively connected to external auto-reclosure device to initiate AR. For phase-segregated circuit breaker, AR mode can be 1-pole AR for single-phase fault and 3-pole AR for multi-phase fault, or always 3-pole AR for any kinds of fault according to system requirement. For persistent fault or multi-shot AR number preset value is reached, the device will send final tripping command. The device will provide appropriate tripping command based on
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faulty phase selection if adopting 1-pole AR. AR can be enabled or disabled by logic setting or external signal via binary input. When AR is enabled, the device will output contact [CBx.79.On], otherwise, output contact [CBx.79.Off]. After some reclosing conditions, such as, CB position, CB pressure and so on, is satisfied, the device will output contact [CBx.79.Ready]. According to requirement, the device can be set as one-shot or multi-shot AR. When adopting multi-shot AR, the AR mode of first time reclosing can be set as 1-pole AR, 3-pole AR or 1/3-pole AR. The rest AR mode is only 3-pole AR and its number is determined by the maximum 3-pole reclosing number. For one-shot AR or first reclosing of multi-shot AR, AR mode can be selected by logic setting [CBx.79.En_1PAR], [CBx.79.En_3PAR] and [CBx.79.En_1P/3PAR] or external signal via binary inputs. When 3-pole or 1/3-pole AR mode is selected, the following three types of check modes can be selected: dead charge check, synchronism check and no check.
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3.29.3 Function Block Diagram 79 CBx.79.En
CBx.79.On
CBx.79.Blk
CBx.79.Off
CBx.79.Sel_1PAR
CBx.79.Close
CBx.79.Sel_3PAR
CBx.79.Ready
CBx.79.Sel_1P/3PAR
CBx.79.AR_Blkd
CBx.79.Trp
CBx.79.Active
CBx.79.Trp3P
CBx.79.Inprog
CBx.79.TrpA
CBx.79.Inprog_1P
CBx.79.TrpB
CBx.79.Inprog_3P
CBx.79.TrpC
CBx.79.Inprog_3PS1
CBx.79.LockOut
CBx.79.Inprog_3PS2
CBx.79.PLC_Lost
CBx.79.Inprog_3PS3
CBx.79.WaitMaster
CBx.79.Inprog_3PS4
CBx.79.CB_Healthy
CBx.79.WaitToSlave
CBx.79.Clr_Counter
CBx.79.Perm_Trp1P
CBx.79.Ok_Chk
CBx.79.Perm_Trp3P
CBx.79.Ok_3PLvChk
CBx.79.Rcls_Status CBx.79.Fail_Rcls CBx.79.Succ_Rcls CBx.79.Fail_Chk CBx.79.Mode_1PAR CBx.79.Mode_3PAR CBx.79.Mode_1/3PAR
3.29.4 I/O Signals Table 3.29-1 I/O signals of auto-reclosing No.
Input Signal
1
CBx.79.En
2
CBx.79.Blk
Description Binary input for enabling AR. If the logic setting [79.En_ExtCtrl]=1, enabling AR will be controlled by the external signal via binary input Binary input for disabling AR. If the logic setting [79.En_ExtCtrl]=1, disabling AR will be controlled by the external input 3-245
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3
CBx.79.Sel_1PAR
4
CBx.79.Sel_3PAR
5
CBx.79.Sel_1P/3PAR
6
CBx.79.Trp
Input signal of single-phase tripping from line protection to initiate AR
7
CBx.79.Trp3P
Input signal of three-phase tripping from line protection to initiate AR
8
CBx.79.TrpA
Input signal of A-phase tripping from line protection to initiate AR
9
CBx.79.TrpB
Input signal of B-phase tripping from line protection to initiate AR
10
CBx.79.TrpC
Input signal of C-phase tripping from line protection to initiate AR
breaker Input signal for selecting 3-pole AR mode of corresponding circuit breaker Input signal for selecting 1/3-pole AR mode of corresponding circuit breaker
Input signal of blocking reclosing, usually it is connected with the 11
CBx.79.LockOut
operating signals of definite-time protection, transformer protection and busbar differential protection, etc.
12
CBx.79.PLC_Lost
13
CBx.79.WaitMaster
14
CBx.79.CB_Healthy
15
CBx.79.Clr_Counter
Clear the reclosing counter
16
CBx.79.Ok_Chk
Synchrocheck condition of AR is met
17
CBx.79.Ok_3PLvChk
Live three-phase check condition of AR is met
No.
Input signal of indicating the alarm signal that signal channel is lost Input signal of waiting for reclosing permissive signal from master AR (when reclosing multiple circuit breakers) The input for indicating whether circuit breaker has enough energy to perform the close function
Output Signal
Description
1
CBx.79.On
Automatic reclosure is enabled
2
CBx.79.Off
Automatic reclosure is disabled
3
CBx.79.Close
Output of auto-reclosing signal
4
CBx.79.Ready
Automatic reclosure have been ready for reclosing cycle
5
CBx.79.AR_Blkd
Automatic reclosure is blocked
6
CBx.79.Active
Automatic reclosing logic is actived
7
CBx.79.Inprog
Automatic reclosing cycle is in progress
8
CBx.79.Inprog_1P
The first 1-pole AR cycle is in progress
9
CBx.79.Inprog_3P
3-pole AR cycle is in progress
10
CBx.79.Inprog_3PS1
First 3-pole AR cycle is in progress
11
CBx.79.Inprog_3PS2
Second 3-pole AR cycle is in progress
12
CBx.79.Inprog_3PS3
Third 3-pole AR cycle is in progress
13
CBx.79.Inprog_3PS4
Fourth 3-pole AR cycle is in progress
14
CBx.79.WaitToSlave
15
CBx.79.Perm_Trp1P
16
CBx.79.Perm_Trp3P
17
CBx.79.Rcls_Status
Waiting signal of automatic reclosing which will be sent to slave (when reclosing multiple circuit breakers) Single-phase circuit breaker will be tripped once protection device operates Three-phase circuit breaker will be tripped once protection device operates Automatic reclosure status
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CBx.79.Fail_Rcls
Auto-reclosing fails
19
CBx.79.Succ_Rcls
Auto-reclosing is successful
20
CBx.79.Fail_Chk
Synchrocheck for AR fails
21
CBx.79.Mode_1PAR
Output of 1-pole AR mode
22
CBx.79.Mode_3PAR
Output of 3-pole AR mode
23
CBx.79.Mode_1/3PAR
Output of 1/3-pole AR mode Automatic reclosure counter
24
CBx.79.N_Total_Rcls
Recorded number of all reclosing attempts
25
CBx.79.N_1PS1
Recorded number of first 1-pole reclosing attempts
26
CBx.79.N_3PS1
Recorded number of first 3-pole reclosing attempts
27
CBx.79.N_3PS2
Recorded number of second 3-pole reclosing attempts
28
CBx.79.N_3PS3
Recorded number of third 3-pole reclosing attempts
29
CBx.79.N_3PS4
Recorded number of fourth 3-pole reclosing attempts
3.29.5 Logic 3.29.5.1 AR Ready For the first reclosing of multi-shot AR, AR mode can be 1-pole AR or 3-pole AR, however, the selection is valid only to the first reclosing, after that it can only be 3-pole AR. When logic setting [CBx.79.SetOpt] is set as “1”, AR mode is determined by logic settings. When logic setting [CBx.79.SetOpt] is set as “0”, AR mode is determined by external signal via binary inputs. An auto-reclosure must be ready to operate before performing reclosing. The output signal [CBx.79.Ready] means that the auto-reclosure can perform at least one time of reclosing function, i.e., breaker open-close-open. When the device is energized or after the settings are modified, AR can not be ready unless the following conditions are met: 1.
AR function is enabled.
2.
The circuit breaker is ready, such as, normal storage energy and no low pressure signal.
3.
The duration of the circuit breaker in closed position before fault occurrence is not less than the setting [CBx.79.t_CBClsd].
4.
There is no block signal of auto-reclosing.
After the auto-reclosure operates, the auto-reclosure must reset, i.e., [CBx.79.Active]=0, in addition to the above conditions for reclosing again. When there is a fault on an overhead line, the concerned circuit breakers will be tripped normally. After fault is cleared, the tripping command will drop off immediately. In case the circuit breaker is in failure, etc., and the tripping signal of the circuit breaker maintains and in excess of the time delay [CBx.79.t_PersistTrp], AR will be blocked, as shown in Figure 3.29-1. 3-247
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Any tripping signal
SIG
CBx.79.LockOut
SIG
1-pole AR Initiation
SIG
Any tripping signal
EN
[CBx.79.En_PDF_Blk]
SIG
CBx.79.Sel_1PAR
EN
[CBx.79.N_Rcls]=1
SIG
Three phase trip
SIG
Phase A open
SIG
Phase B open
[CBx.79.t_PersistTrp]
0ms
>=1 0ms [CBx.79.t_DDO_BlkAR] [CBx.79.t_SecFault] 0ms
>=1 CBx.79.AR_Blkd
&
& & >=1 &
&
>=1
& SIG
Phase C open
Figure 3.29-1 Logic diagram of AR block
The input signal [CBx.79.CB_Healthy] must be energized before auto-reclosure gets ready. Because most circuit breakers can finish one complete process: open-closed-open, it is necessary that circuit breaker has enough energy before reclosing. When the time delay of AR is exhausted, AR will be blocked if the input signal [CBx.79.CB_Healthy] is still not energized within time delay [CBx.79.t_CBReady]. If this function is not required, the input signal [CBx.79.CB_Healthy] can be not to configure, and its state will be thought as “1” by default. In orde to block AR reliably even if the signal of manually open circuit breaker not connected to the input of blocking AR, when the circuit breaker is open by manually and there is CB position input under normal conditions, AR will be blocked with the time delay of 100ms if AR is not initated and no any trip signal. When auto-reclosure is blocked, auto-reclosing failure, synchrocheck failure or last shot is reached, or when the internal blocking condition of AR is met (such as, zone 3 of distance protection operates, the device operates for multi-phase fault, three-phase fault and so on. These flags of blocking AR have been configured in the device, additional configuration is not required.), auto-reclosure will be discharged immediately and next auto-reclosing will be disabled. When the input signal [CBx.79.LockOut] is energized, auto-reclosure will be blocked immediately. The blocking flag of AR will be also controlled by the internal blocking condition of AR. When the blocking flag of AR is valid, auto-reclosure will be blocked immediately. The logic of AR ready is shown in Figure 3.29-2.
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>=1 SIG
3 CB closed
[CBx.79.t_CBClsd]
SIG
CBx.79.Active
>=1
SIG
Any tripping signal
100ms
&
&
& 100ms
SIG
CBx.79.Inprog
SIG
[CBx.79.CB_Healthy]
0ms
SIG
CBx.79.AR_Blkd
>=1
SIG
CBx.TRP.BlkAR
SIG
CBx.79.Fail_Rcls
SIG
CBx.79.Fail_Chk
SIG
Last shot is made
EN
[CBx.79.En]
EN
[CBx.79.En_ExtCtrl]
SIG
CBx.79.En
SIG
CBx.79.Blk
[CBx.79.t_CBReady]
0
CBx.79.Ready
&
>=1 & >=1
& >=1 CBx.79.On
& &
Figure 3.29-2 Logic diagram of AR ready
When a fault occurs under pole disagreement condition, blocking AR can be enabled or disabled. The time delay [CBx.79.t_SecFault] is used to discriminate another fault which begins after 1-pole AR initiated. AR will be blocked if another fault happens after this time delay if the logic setting [CBx.79.En_PDF_Blk] is set as “1”, and 3-pole AR will be initiated if [CBx.79.En_PDF_Blk] is set as “1”. AR will be blocked immediately once the blocking condition of AR appears, but the blocking condition of AR will drop off with a time delay [CBx.79.t_DDO_BlkAR] after blocking signal disappears. When one-shot and 1-pole AR is enabled, auto-reclosure will be blocked immediately if there are binary inputs of multi-phase CB position is energized. When any protection element operates to trip, the device will output a signal [CBx.79.Active] until AR drop off (Reset Command). Any tripping signal can be from external protection device or internal protection element. AR function can be enabled by internal logic settings of AR mode or external signal via binary inputs in addition to internal logic setting [CBx.79.En]. When logic setting [CBx.79.En_ExtCtrl] is set as “1”, AR enable are determined by external signal via binary inputs and logic settings. When logic setting [CBx.79.En_ExtCtrl] set as “0”, AR enable are determined only by logic settings. 3-249
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For one-shot reclosing, if 1-pole AR mode is selected, auto-reclosure will reset when there is three-phase tripping signal or input signal of multi-phase open position. SIG
CBx.79.On
SIG
CBx.79.Mode_3PAR
SIG
CBx.79.Ready
SIG
CBx.79.Trp
SIG
CBx.79.Trp3P
SIG
CBx.79.TrpA
SIG
CBx.79.TrpB
SIG
CBx.79.TrpC
SIG
Phase A open
SIG
Phase B open
SIG
Phase C open
Logic
CBx.79.Perm_Trp3P CBx.79.Perm_Trp1P
Figure 3.29-3 Logic diagram of tripping condition output
When AR is enabled, the device will output the signal [CBx.79.Perm_Trp3P] if AR is not ready, or AR mode is set as 3-Pole AR, or another fault occurs after the circuit breaker is open. 3.29.5.2 AR Initiation AR mode can be selected by external signal via binary inputs or internal logic settings. If the logic setting [CBx.79.SetOpt] set as “1”, AR mode is determined by the internal logic settings. If the logic settings [CBx.79.SetOpt] set as “0”, AR mode is determined by the external inputs. 1.
AR initiated by tripping signal of line protection
AR can be initiated by tripping signal of line protection, and the tripping signal may be from internal trip signal or external trip signal. When selecting 1-pole AR or 1/3-pole AR, line single-phase fault will trigger 1-pole AR. When AR is ready to reclosing (“CBx.79.Ready”=1) and the single-phase tripping command is received, this single-phase tripping command will be kept in the device, and 1-pole AR will be initiated after the single-phase tripping command drops off. The single-phase tripping command kept in the device will be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is shown in Figure 3.29-4.
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Reset Command
& >=1
SIG
Single-phase Trip
& & SIG
CBx.79.Ready
1-pole AR Initiation
SIG
CBx.79.Sel_1PAR
SIG
CBx.79.Sel_1P/3PAR
>=1
Figure 3.29-4 Single-phase tripping initiating AR
When selecting 3-pole AR or 1/3-pole AR, three-phase tripping will trigger 3-pole AR. When AR is ready to reclosing (“CBx.79.Ready”=1) and the three-phase tripping command is received, this three-phase tripping command will be kept in the device, and 3-pole AR will be initiated after the three-phase tripping command drops off. The three-phase tripping command kept in the device will be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is shown in Figure 3.29-5. SIG
Reset Command
& >=1
SIG
Three-phase Trip
& & SIG
CBx.79.Ready
3-pole AR Initiation
SIG
CBx.79.Sel_3PAR
SIG
CBx.79.Sel_1P/3PAR
>=1
Figure 3.29-5 Three-phase tripping initiating AR
2.
AR initiated by CB state
A logic setting [CBx.79.En_CBInit] is available for selection that AR is initiated by CB state. Under normal conditions, when AR is ready to reclosing (“CBx.79.Ready”=1), AR will be initiated if circuit breaker is open and corresponding phase current is nil. AR initiated by CB state can be divided into initiating 1-pole AR and 3-pole AR, their logics are shown in Figure 3.29-6 and Figure 3.29-7 respectively. Usually normally closed contact of circuit breaker is used to reflect CB state.
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Phase A open
SIG
Phase B open
>=1 & &
SIG
Phase C open
EN
[CBx.79.En_CBInit]
SIG
CBx.79.Ready
SIG
CBx.79.Sel_1PAR
SIG
CBx.79.Sel_1P/3PAR
& & 1-pole AR Initiation
>=1
Figure 3.29-6 1-pole AR initiation
SIG
Phase A open
SIG
Phase B open
SIG
Phase C open
EN
[CBx.79.En_CBInit]
&
&
& 3-pole AR Initiation
SIG
CBx.79.Ready
EN
[CBx.79.Sel_3PAR]
EN
[CBx.79.Sel_1P/3PAR]
>=1
Figure 3.29-7 3-pole AR initiation
3.29.5.3 AR Reclosing After AR is initiated, the device will output the initiating contact of AR. For 1-pole AR, in order to prevent pole discrepancy protection from maloperation under pole discrepancy conditions, the contact of “1-pole AR initiation” can be used to block pole discrepancy protection. When the dead time delay of AR expires after AR is initiated, as for 1-pole AR, when the setting [CBx.25.En_3PLvChk] is set as “0”, the result of synchronism check will not be judged, and reclosing command will be output directly. When the setting [CBx.25.En_3PLvChk] is set as “1”, the reclosing is not permissible unless live three-phase check is met. As far as the 3-pole AR, if the synchronism check is enabled, the release of reclosing command shall be subject to the result of synchronism check. After the dead time delay of AR expires, if the synchronism check is still unsuccessful within the time delay [CBx.79.t_wait_Chk], the signal of synchronism check failure (CBx.79.Fail_Syn) will be output and the AR will be blocked. If 3-pole AR with no-check is enabled, the condition of synchronism check success (CBx.25.Ok_Chk) will always be established. And the signal of synchronism check success (CBx.25.Ok_Chk) from the synchronism check logic can be applied by auto-reclosing function inside the device or external auto-reclosure device. 3-252
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1-pole AR Initiation
SIG
3-pole AR Initiation
>=1 CBx.79.Inprog
CBx.79.Inprog_3P SIG
1-pole AR Initiation
[CBx.79.t_Dd_1PS1]
0ms
& >=1 AR Pulse
& SIG
CBx.79.Ok_3PLvChk
SIG
3-pole AR Initiation
[CBx.79.t_Dd_3PS1]
0ms
& >=1 [CBx.79.t_Wait_Chk] 0ms
& SIG
CBx.79.Fail_Chk
CBx.79.Ok_Chk
Figure 3.29-8 One-shot AR
In the process of channel abnormality, an internal fault occurs on the transmission line, backup protection at both ends of line will operate to trip the circuit breaker of each end. The operation time of backup protection at both ends of the line is possibly non-accordant, whilst the time delay of AR needs to consider the arc-extinguishing and insulation recovery ability for transient fault, so the time delay of AR shall be considered comprehensively according to the operation time of the device at both ends. When the communication channel of main protection is abnormal (input signal [CBx.79.PLC_Lost] is energized), and the logic setting [CBx.79.En_AddDly] is set as “1”, then the dead time delay of AR shall be equal to the original dead time delay of AR plus the extra time delay [CBx.79.t_AddDly], so as to ensure the recovery of insulation intensity of fault point when reclosing after transient fault. This extra time delay [CBx.79.t_AddDly] is only valid for the first shot AR.
>=1 SIG
Any tripping signal
SIG
CBx.79.PLC_Lost
SIG
CBx.79.Active
EN
[CBx.79.En_AddDly]
& & & Extend AR time
Figure 3.29-9 Extra time delay of AR
Reclosing pulse length may be set through the setting [CBx.79.t_PW_AR]. For the circuit breaker without anti-pump interlock, a logic setting [CBx.79.En_CutPulse] is available to control the reclosing pulse. When this function is enabled, if the device operates to trip during reclosing, the
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reclosing pulse will drop off immediately, so as to prevent multi-shot reclosing onto fault. After the reclosing command is issued, AR will drop off with time delay [CBx.79.t_Reclaim], and can carry out next reclosing. SIG
SIG
WaitMasterValid
& 0ms
50ms
0ms
[CBx.79.t_PW_AR]
AR Pulse
SIG
Single-phase Trip
SIG
Three-phase Trip
EN
[CBx.79.En_CutPulse]
>=1 CBx.79.AR_Out
&
>=1 &
>=1 & SIG
[CBx.79.t_Reclaim]
CBx.79.AR_Out
0ms
Reset Command
Figure 3.29-10 Reclosing output logic
The reclaim timer defines a time from the issue of the reclosing command, after which the reclosing function resets. Should a new trip occur during this time, it is treated as a continuation of the first fault. The reclaim timer is started when the CB closing command is given. SIG
1-pole AR Initiation
>=1 0ms
SIG
3-pole AR Initiation
SIG
CBx.79.Fail_Rcls
SET
[CBx.79.Opt_Priority]=High
[CBx.79.t_Fail]
>=1 & CBx.79.WaitToSlave
Figure 3.29-11 Wait to slave signal
The output signal “CBx.79.WaitToSlave” is usually configured to the signal “CBx.79.WaitMaster” of slave AR. Slave AR is permissible to reclosing only if master AR is reclosed successfully. 3.29.5.4 Reclosing Failure and Success For transient fault, the fault will be cleared after the device operates to trip. After the reclosing command is issued, AR will drop off after time delay [CBx.79.t_Reclaim], and can carry out next reclosing. When the reclosing is unsuccessful or the reclosing condition is not met after AR initiated, the reclosing will be considered as unsuccessful, including the following cases. 1.
If any protection element operates to trip when AR is enabled ([CBx.79.On]=1) and AR is not ready ([CBx.79.Ready]=0), the device will output the signal (CBx.79.Fail_Rcls).
2.
For one-shot AR, if the tripping command is received again within reclaim time after the
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reclosing pulse is issued, the reclosing shall be considered as unsuccessful. 3.
For multi-shot AR, if the reclosing times are equal to the setting value of AR number and the tripping command is received again after the last reclosing pulse is issued, the reclosing shall be considered as unsuccessful.
4.
The logic setting [CBx.79.En_FailCheck] is available to judge whether the reclosing is successful by CB state, when it is set as “1”. If CB is still in open position with a time delay [CBx.79.t_Fail] after the reclosing pulse is issued, the reclosing shall be considered as unsuccessful. For this case, the device will issue a signal (CBx.79.Fail_Rcls) to indicate that the reclosing is unsuccessful, and this signal will drop off after (Reset Command). AR will be blocked if the reclosing shall be considered as unsuccessful.
SET
[CBx.79.Opt_Priority]=Low
SIG
CBx.79.WaitMaster
SIG
CBx.79.On
SIG
CBx.79.Ready
SIG
Any tripping command
SIG
Last shot is made
SIG
CBx.79.Inprog
SIG
CBx.79.AR_Blkd
SIG
WaitMasterValid
& WaitMaster Valid
&
&
>=1 0ms
200ms
>=1 CBx.79.Fail_Rcls
&
& [CBx.79.t_WaitMaster]
0ms
>=1 & SIG
AR Pulse
SIG
3 CB closed
EN
[CBx.79.En_FailCheck]
[CBx.79.t_Fail] 0ms
&
& &
CBx.79.Succ_Rcls
0ms [CBx.79.t_Fail]
Figure 3.29-12 Reclosing failure and success
After unsuccessful AR is confirmed, AR will be blocked. AR will not enter into the ready state unless the circuit breaker position drops off , and can only begin to enter into the ready state again after the circuit breaker is closed. 3.29.5.5 Reclosing Numbers Control The device may be set up into one-shot or multi-shot AR. Through the setting [CBx.79.N_Rcls], the maximum number of reclosing attempts may be set up to 4 times. Generally, only one-shot AR is selected. Some corresponding settings may be hidden if one-shot AR is selected. 3-255
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1.
1-pole AR
[CBx.79.N_Rcls]=1 means one-shot reclosing. For one-shot 1-pole AR mode, 1-pole AR will be initiated only for single-phase fault and respective faulty phase selected, otherwise, AR will be blocked. For single-phase transient fault on the line, line protection device will operate to trip and 1-pole AR is initiated. After the dead time delay for 1-pole AR is expired, the device will send reclosing pulse, and then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed, and the device will output the signal of reclosing failure [CBx.79.Fail_Rcls]. [CBx.79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1-pole AR mode, the first reclosing is 1-pole AR, and the subsequent reclosing can only be 3-pole AR. For single-phase transient fault on the line, line protection device will operate to trip and then 1-pole AR is initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing pulse, and then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed, and then 3-pole AR is initiated. At this time, the time delay applies the setting [CBx.79.t_Dd_3PS2]. After the time delay is expired, if the reclosing condition is met, the device will send reclosing pulse. The sequence is repeated until the reclosing is successful or the maximum permit reclosing number [CBx.79.N_Rcls] is reached. If the first fault is multi-phase fault, the device operates to trip three-phase and initiate 3-pole AR. At this time, the time delay applies the setting [CBx.79.t_Dd_3PS1]. For the possible reclosing times of 3-pole AR in 1-pole AR mode, please refer to Table 3.29-2. 2.
3-pole AR
[CBx.79.N_Rcls]=1 means one-shot reclosing. For one-shot 3-pole AR mode, line protection device will operate to trip when a transient fault occurs on the line and 3-pole AR will be initiated. After the dead time delay for 3-pole AR is expired, the device will send reclosing pulse, and then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed, and the device will output the signal of reclosing failure [CBx.79.Fail_Rcls]. [CBx.79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 3-pole AR mode, line protection device will operate to trip when a transient fault occurs on the line and 3-pole AR will be initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing pulse, and then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay for AR is expired, the device will send reclosing pulse. The sequence is repeated until the reclosing is successful or the maximum permit reclosing number [CBx.79.N_Rcls] is reached. 3.
1/3-pole AR
[CBx.79.N_Rcls]=1 means one-shot reclosing. For one-shot 1/3-pole AR mode, line protection device will operate to trip when a transient fault occurs on the line and 1-pole AR will be initiated for single-phase fault and 3-pole AR will be initiated for multi-phase fault. After respective dead time delay for AR is expired, the device will send reclosing pulse, and then the auto-reclosure will 3-256
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drop off after the time delay [CBx.79.t_Reclaim] to ready for the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed, and the device will output the signal of reclosing failure [CBx.79.Fail_Rcls]. [CBx.79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1/3-pole AR mode, line protection device will operate to trip when a transient fault occurs on the line and AR will be initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing pulse, and then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay for AR is expired, the device will send reclosing pulse. The sequence is repeated until the reclosing is successful or the maximum permit reclosing number [CBx.79.N_Rcls] is reached. For the possible reclosing times of 3-pole AR in 1/3-pole AR mode, please refer to Table 3.29-2. The table below shows the number of reclose attempts with respect to the settings and AR modes. Table 3.29-2 Reclosing number
Setting Value
1-pole AR
3-pole AR
1/3-pole AR
N-1AR
N-3AR
N-1AR
N-3AR
N-1AR
N-3AR
1
1
0
0
1
1
1
2
1
1
0
2
1
2
3
1
2
0
3
1
3
4
1
3
0
4
1
4
N-1AR: the reclosing number of 1-pole AR N-3AR: the reclosing number of 3-pole AR 4.
Coordination between dual auto-reclosures
Duplicated protection configurations are normally applied for UHV lines. If reclosing function is integrated within line protections, the auto-reclosing function can be enabled in any or both of the line protections without coordination. If both sets of reclosing functions are enabled, when one of them first recloses onto a permanent fault, the other will block the reclosing pulse according to the latest condition of the faulty phase. For one-shot AR mode, if the current is detected in the faulty phase, AR will be blocked immediately to prevent the circuit breaker from repetitive reclosing. For multi-shot AR mode, if the current is detected in the faulty phase, the current reclosing pulse will be blocked and go into the next reclosing pulse logic automatically. If the maximum permitted reclosing number [CBx.79.N_Rcls] is reached, the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim]. For one-shot or multi-shot AR, there is a corresponding reclosing counter at each stage. After reclosing pulse is sent, the corresponding reclosing counter will plus 1 and the reclosing counter may be cleared by the submenu “Clear Counter”. If the circuit breaker is reclosed by other devices during AR initiation, the auto-reclosure will go into the next reclosing pulse logic.
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3.29.5.6 AR Time Sequence Diagram The following two examples indicate typical time sequence of AR process for transient fault and permanent fault respectively. Signal
Fault Trip CB 52b
Open [CBx.79.t_Reclaim]
CBx.79.t_Reclaim CBx.79.Active CBx.79.Inprog
[CBx.79.t_Dd_1PS1]
CBx.79.Inprog_1P
[CBx.79.t_Dd_1PS1]
CBx.79.Ok_Chk AR Out
[CBx.79.t_PW_AR]
CBx.79.Perm_Trp3P CBx.79.Fail_Rcls Time
Figure 3.29-13 Single-phase transient fault
Signal
Fault Trip 52b
Open
Open [CBx.79.t_Reclaim]
CBx.79.t_Reclaim CBx.79.Active CBx.79.Inprog CBx.79.Inprog_1P CBx.79.Inprog_3PS2
[CBx.79.t_Dd_1PS1] [CBx.79.t_Dd_3PS2]
CBx.79.Ok_Chk AR Out
[CBx.79.t_PW_AR]
[CBx.79.t_PW_AR]
CBx.79.Perm_Trp3P CBx.79.Fail_Rcls
200ms Time
Figure 3.29-14 Single-phase permanent fault ([CBx.79.N_Rcls]=2)
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3.29.6 Settings Table 3.29-3 Auto-reclosing settings No.
Name
Range
Step
Unit
Remark Maximum
1
CBx.79.N_Rcls
1~4
1
2
CBx.79.t_Dd_1PS1
0.000~600.000
0.001
s
3
CBx.79.t_Dd_3PS1
0.000~600.000
0.001
s
4
CBx.79.t_Dd_3PS2
0.000~600.000
0.001
s
5
CBx.79.t_Dd_3PS3
0.000~600.000
0.001
s
6
CBx.79.t_Dd_3PS4
0.000~600.000
0.001
s
7
CBx.79.t_CBClsd
0.000~600.000
0.001
s
number
of
reclosing
attempts Dead time of first shot 1-pole reclosing Dead time of first shot 3-pole reclosing Dead time of second shot 3-pole reclosing Dead time of third shot 3-pole reclosing Dead time of fourth shot 3-pole reclosing Time delay of circuit breaker in closed position before reclosing Time delay to wait for CB healthy, and begin to timing when the input
8
CBx.79.t_CBReady
0.000~600.000
0.001
s
signal
[79.CB_Healthy]
de-energized
and
if
it
is is
not
energized within this time delay, AR will be blocked. 9
CBx.79.t_Wait_Chk
0.000~600.000
0.001
s
Maximum wait time for synchronism check Time delay allow for CB status
10
CBx.79.t_Fail
0.000~600.000
0.001
s
change
to
conform
reclosing
successful 11
CBx.79.t_PW_AR
0.000~600.000
0.001
s
Pulse width of AR closing signal
12
CBx.79.t_Reclaim
0.000~600.000
0.001
s
Reclaim time of AR
13
CBx.79.t_PersistTrp
0.000~600.000
0.001
s
Time delay of excessive trip signal to block auto-reclosing Drop-off time delay of blocking AR,
14
CBx.79.t_DDO_BlkAR
0.000~600.000
0.001
s
when
blocking
signal
for
AR
disappears, AR blocking condition drops off after this time delay
15
CBx.79.t_AddDly
0.000~600.000
0.001
s
16
CBx.79.t_WaitMaster
0.000~600.000
0.001
s
17
CBx.79.t_SecFault
0.000~600.000
0.001
s
Additional
time
delay
for
auto-reclosing Maximum wait time for reclosing permissive signal from master AR Time delay of discriminating another fault, and begin to times after 1-pole
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Name
Range
Step
Unit
Remark AR initiated, 3-pole AR will be initiated if another fault happens during this time delay. AR will be blocked if another fault happens after that. Enabling/disabling
auto-reclosing
blocked when a fault occurs under 18
CBx.79.En_PDF_Blk
0 or 1
pole disagreement condition 0: disable 1: enable Enabling/disabling
19
CBx.79.En_AddDly
auto-reclosing
with an additional dead time delay
0 or 1
0: disable 1: enable Enabling/disabling adjust the length
20
CBx.79.En_CutPulse
of reclosing pulse
0 or 1
0: disable 1: enable Enabling/disabling confirm whether AR is successful by checking CB
21
CBx.79.En_FailCheck
0 or 1
state 0: disable 1: enable Enabling/disabling auto-reclosing
22
CBx.79.En
0 or 1
0: disable 1: enable Enabling/disabling AR by external input signal besides logic setting
23
CBx.79.En_ExtCtrl
[79.En]
0 or 1
0: only logic setting 1: logic setting and external input signal Enabling/disabling AR be initiated by
24
CBx.79.En_CBInit
open state of circuit breaker
0 or 1
0: disable 1: enable Option of AR priority None: single-breaker arrangement
25
CBx.79.Opt_Priority
None, High or
High: master AR of multi-breaker
Low
arrangement Low: slave AR of multi-breaker arrangement
26
CBx.79.SetOpt
0 or 1
Control option of AR mode
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Name
Range
Step
Unit
Remark 1: select AR mode by internal logic settings 0: select AR mode by external input signals Enabling/disabling 1-pole AR mode
27
CBx.79.En_1PAR
0 or 1
0: disable 1: enable Enabling/disabling 3-pole AR mode
28
CBx.79.En_3PAR
0 or 1
0: disable 1: enable Enabling/disabling
29
CBx.79.En_1P/3PAR
1/3-pole
AR
mode
0 or 1
0: disable 1: enable
3.30 Transfer Trip 3.30.1 General Application This function module provides a binary input [TT.Init] for receiving transfer trip from the remote end. This feature ensures simultaneous tripping at both ends.
3.30.2 Function Description Transfer trip can be controlled by local fault detector by logic settings [TT.En_FD_Ctrl]. In addition, the binary input [TT.Init] is always supervised, and the device will issue an alarm [TT.Alm] and block transfer trip once the binary input is energized for longer than 4s and drop off after resumed to normal with a time delay of 10s.
3.30.3 Function Block Diagram TT TT.Init
TT.Alm
TT.En
TT.Op
TT.Blk
TT.On
3.30.4 I/O Signals Table 3.30-1 I/O signals of transfer trip No.
Input Signal
Description
1
TT.Init
Input signal of initiating transfer trip after receiving transfer trip
2
TT.En
Transfer trip enabling input, it is triggered from binary input or programmable logic 3-261
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Transfer trip blocking input, it is triggered from binary input or programmable logic
TT.Blk
No.
etc.
Output Signal
Description
1
TT.Alm
Input signal of receiving transfer trip is abnormal
2
TT.Op
Transfer trip operates
3
TT.On
Transfer trip is enabled
3.30.5 Logic SIG
TT.En
SIG
TT.Blk
& TT.On
4s
BI
[TT.Init]
SIG
TT.Alm
EN
[TT.En_FD_Ctrl]
SIG
FD.Pkp
BI
[TT.Init]
10s
TT.Alm
& TT.Op
>=1
Figure 3.30-1 Logic diagram of transfer trip
3.30.6 Settings Table 3.30-2 Settings of transfer trip No. 1
2
Name TT.t_Op
TT.En_FD_Ctrl
Range
Step
Unit
0.000~600.000
0.001
s
Remark Time delay of transfer trip Transfer trip controlled by local fault detector element 0: not controlled by local fault detector element 1: controlled by local fault detector element
0 or 1
3.31 Trip Logic 3.31.1 General Application For any enabled protection tripping elements, their operation signal will convert to appropriate tripping signals through trip logics and then trigger output contacts by configuration. NOTICE! For double circuit breakers mode, the device will provide indenpendent trip logic for CB1 and CB2 respectively. Both trip logics have the same logic.The difference is that the prefix “CBx.” is added to all signals for circuit breaker No.x (x=1 or 2). For trip logic 3-262
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settings, only the setting [En_Trp3P] will be added the prefix “CBx.” for circuit breaker No.x, which means that both circuit breakers corresponding to the same line protection can be set different trip mode.
3.31.2 Function Description This module gathers signals from phase selection and protection tripping elements and then converts the operation signal from protection tripping elements to appropriate tripping signals. The device can implement phase-segregated tripping or three-phase tripping, and may output the contact of blocking AR and the contact of initiating breaker failure protection.
3.31.3 Function Block Diagram TRP CBx.TRP.En
CBx.TrpA
CBx.TRP.Blk
CBx.TrpB
Faulty phase selection
CBx.TrpC
CBx.PrepTrp3P
CBx.Trp
Line tripping element
CBx.Trp3P
Breaker tripping element
CBx.BFI_A
Initiating BFP element
CBx.BFI_B CBx.BFI_C CBx.BFI CBx.Trp3P_PSFail CBx.TRP.BlkAR CBx.TRP.On
3.31.4 I/O Signals Table 3.31-1 I/O signals of trip logic No.
Input Signal
Description Trip enabling input, it is triggered from binary input or programmable
1
CBx.TRP.En logic etc. Trip blocking input, it is triggered from binary input or programmable
2
CBx.TRP.Blk logic etc.
3
4
Faulty phase selection (phase
The result of fault phase selection
A, phase B, phase C)
If multi-phase is selected, three-phase breakers will be tripped.
CBx.PrepTrp3P
Input signal of permitting three-phase tripping When this signal is valid, three-phase tripping will be adopted for any
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Line tripping element
6
Breaker tripping element
7
Initiating BFP element
All operation signals of various line protection tripping elements, such as distance protection, overcurrent protection, etc. All protection tripping elements concerned with breaker, such as pole discrepancy protection, etc. Tripping element to initiate BFP, except undervoltage protection, tripping elements of all protections initiate BFP
No.
Output Signal
Description
1
CBx.TRP.On
Tripping logic is enabled.
2
CBx.TrpA
Tripping A-phase circuit breaker
3
CBx.TrpB
Tripping B-phase circuit breaker
4
CBx.TrpC
Tripping C-phase circuit breaker
5
CBx.Trp
Tripping any phase circuit breaker
6
CBx.Trp3P
Tripping three-phase circuit breaker
7
CBx.BFI_A
8
CBx.BFI_B
9
CBx.BFI_ C
10
CBx.BFI
11
CBx.Trp3P_PSFail
Initiating three-phase tripping due to failure in fault phase selection
12
CBx.TRP.BlkAR
Blocking auto-reclosing
Protection tripping signal of A-phase configured to initiate BFP, BFI signal shall be reset immediately after tripping signal drops off. Protection tripping signal of B-phase configured to initiate BFP, BFI signal shall be reset immediately after tripping signal drops off. Protection tripping signal of C-phase configured to initiate BFP, BFI signal shall be reset immediately after tripping signal drops off. Protection tripping signal configured to initiate BFP, BFI signal shall be reset immediately after tripping signal drops off.
3.31.5 Logic After tripping signal is issued, the tripping pulse will be kept as same as the setting [t_Dwell_Trp] at least. When the time delay is expired, for phase-segregated tripping, the tripping signal will drop off immediately if the faulty current of corresponding phase is less than 0.06In (In is secondary rated current), otherwise the tripping signal will be always kept until the faulty current of corresponding phase is less than 0.06In. For three-phase tripping, the tripping signal will drop off immediately if three-phase currents are all less than 0.06In, otherwise the tripping signal will be always kept until three-phase currents are all less than 0.06In.
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SIG FPS (phase A)
&
SIG FPS (phase B)
&
SIG FPS (phase C)
&
&
>=1
&
>=1
&
>=1
SIG Line tripping element SIG CBx.TRP.En
& CBx.TRP.On
SIG CBx.TRP.Blk
&
SIG Breaker tripping element SIG CBx.PrepTrp3P
>=1
>=1 &
EN
[CBX.En_3PTrp]
SIG CBx.Trp SIG Line tripping element
&
SIG FPS (phase A)
&
SIG FPS (phase B)
&
SIG FPS (phase C)
&
>=1
>=1
CBx.Trp3P_PSFail
>=1 & 200ms
0ms
SIG Line tripping element SIG CBx.TrpA
& [t_Dwell_Trp]
0
&
[t_Dwell_Trp]
0
&
[t_Dwell_Trp]
0
&
CBx.TrpA
SIG Ia=1 &
Except undervoltage protection,
tripping elements of all protections all initiate BFP SIG
CBx.BFI
Initiating BFP element
& CBx.BFI_A
SIG
CBx.TrpA
& CBx.BFI_B SIG
CBx.TrpB
& CBx.BFI_C SIG
CBx.TrpC
Figure 3.31-2 Breaker failure initiation logic
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85-1.Op_DEF
SIG
85-2.Op_DEF
EN
[85.DEF.En_BlkAR]
SIG
78.Op
SIG
Yx.ZP.Op
>=1 &
&
>=1
>=1 >=1
EN
[Yx.ZP.En_BlkAR]
SIG
Yx.ZG.Op
EN
[Yx.ZG.En_BlkAR]
SIG
50/51Pm.Op
EN
[50/51Pm.En_BlkAR]
SIG
50/51Gm.Op
EN
[50/51Gm.En_BlkAR]
SIG
50/51Qm.Op
EN
[50/51Qm.En_BlkAR]
SIG
50PVT.Op
SIG
50GVT.Op
SIG
46BC.Op
SIG
81O.OFx.Op
SIG
81U.UFx.Op
SIG
TT.Op
SIG
CBx.50BF.Op_t1
SIG
CBx.50BF.Op_t2
SIG
CBx.50DZ.Op
SIG
49-1.Op
SIG
49-2.Op
SIG
50STB.Op
SIG
32R2.Op
SIG
32R1.Op
SIG
CBx.62PD.Op
SIG
59Pz.Op
SIG
59Gz.Op
SIG
59Q.Op
SIG
27Pz.Op
EN
En_MPF_Blk_AR
SIG
Multi-phase fault
EN
En_3PF_Blk_AR
SIG
Three-phase fault
EN
En_PhSF_Blk_AR
SIG
Phase selection failure
SIG
21SOTF.Op
SIG
50PSOTF.Op
SIG
50GSOTF.Op
SIG
Manual closing signal
&
&
&
>=1
&
>=1
>=1
>=1
>=1
>=1 >=1
>=1
>=1 CBx.BlkAR
>=1
>=1 >=1
&
&
>=1
&
>=1
>=1 &
Figure 3.31-3 Blocking AR logic 3-267
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Y can be 21M or 21Q x can be 1, 2, 3, 4 or 5 m can be 1, 2, 3 or 4 z can be 1, 2 or 3
3.31.6 Settings Table 3.31-2 Settings of trip logic No.
Name
Range
Step
Unit
Remark Enabling/disabling
1
En_MPF_Blk_AR
auto-reclosing
blocked
when multi-phase fault happens
0 or 1
0: disable 1: enable Enabling/disabling
2
En_3PF_Blk_AR
auto-reclosing
blocked
when three-phase fault happens
0 or 1
0: disable 1: enable Enabling/disabling 3
En_PhSF_Blk_AR
auto-reclosing
blocked
when faulty phase selection fails
0 or 1
0: disable 1: enable Enabling/disabling three-phase tripping mode 4
CBx.En_Trp3P
for any fault conditions
0 or 1
0: disable 1: enable The dwell time of tripping command, empirical value is 0.04
5
t_Dwell_Trp
0.000~10.000
0.001
s
The tripping contact shall drop off under conditions of no current or protection tripping element drop-off.
3.32 VT Circuit Supervision 3.32.1 General Application The purpose of VT circuit supervision is to detect whether VT circuit is normal. Because some protection functions, such as distance protection, under-voltage protection and so on, will be influenced by VT circuit failure, these protection functions should be disabled when VT circuit fails. VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault, poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should not be issued when the following cases happen. 1.
Line VT is used as protection VT and the protected line is out of service.
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2.
Only current protection functions are enabled and VT is not connected to the device.
3.32.2 Function Description VT circuit supervision can detect failure of single-phase, two-phase and three-phase on protection VT. Under normal condition, the device continuously supervises input voltage from VT, VT circuit failure signal will be activated if residual voltage exceeds the threshold value or positive-sequence voltage is lower than the threshold value. If the device is under pickup state due to system fault or other abnormality, VT circuit supervision will be disabled. Under normal conditions, the device detect residual voltage greater than 8% of Unn to determine single-phase or two-phase VT circuit failure, and detect positive-sequence voltage less than 0.3Unn to determine three-phase VT circuit failure. Upon detecting abnormality on VT circuit, an alarm will comes up with the time delay [VTS.t_DPU] and drop off with the time delay [VTS.t_DDO] after VT circuit restored to normal. VT (secondary circuit) MCB auxiliary contact as a binary input can be connected to the binary input circuit of the device. If MCB is open (i.e. [VTS.MCB_VT] is energized), the device will consider the VT circuit is not in a good condition and issues an alarm without a time delay. When VT is not connected into the device, the alarm will be not issued if the logic setting [VTS.En_Out_VT] is set as “1”. However, the alarm is still issued if the binary input [VTS.MCB_VT] is energized, no matter that the logic setting [VTS.En_Out_VT] is set as “1” or “0”. When VT neutral point fails, third harmonic of residual voltage is comparatively large. If third harmonic amplitude of residual voltage is larger than 0.2Unn and without operation of fault detector element, VT neutral point failure alarm signal [VTNS.Alm] will be issued with the time delay [VTS.t_DPU] and drop off with the time delay [VTS.t_DDO] after three phases voltage restored to normal.
3.32.3 Function Block Diagram VTS
VTS.En
VTNS
VTNS.En
VTS.Alm
VTS.Blk
VTNS.Alm
VTNS.Blk
VTS.MCB_VT
3.32.4 I/O Signals Table 3.32-1 I/O signals of VT circuit supervision No.
Input Signal
1
VTS.En
2
VTS.Blk
Description VT supervision enabling input, it is triggered from binary input or programmable logic etc. VT supervision blocking input, it is triggered from binary input or programmable
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3
VTNS.En
4
VTNS.Blk
5
VTS.MCB_VT
No.
programmable logic etc. VT neutral point supervision blocking input, it is triggered from binary input or programmable logic etc. Binary input for VT MCB auxiliary contact
Output Signal
Description
1
VTS.Alm
Alarm signal to indicate VT circuit fails
2
VTNS.Alm
Alarm signal to indicate VT neutral point fails
3.32.5 Logic
& SIG
FD.Pkp
SIG
79.Inprog
SIG
3U0>0.08Unn
SIG
U1=1
>=1 & >=1
If the signal [FD.Pkp] or [79.Inprog] operates, then circuit of time delay will be interrupted.
&
[VTS.t_DPU] [VTS.t_DDO]
BI
& >=1
>=1 &
VTS.Alm
[VTS.MCB_VT]
EN
[VTS.En]
SIG
[VTS.En]
SIG
[VTS.Blk]
&
Figure 3.32-1 Logic of VT circuit supervision
& SIG
FD.Pkp
SIG
79.Inprog
>=1 If the signal [FD.Pkp] or [79.Inprog] operates, then circuit of time delay will be interrupted.
OTH
U03>0.2Unn
&
>=1 [VTS.t_DPU]
EN
[VTS.En_Out_VT]
EN
[VTS.En]
SIG
[VTNS.En]
SIG
[VTNS.Blk]
[VTS.t_DDO]
&
VTNS.Alm
&
Figure 3.32-2 Logic of VT neutral point supervision
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Where: Unn: rated phase-to-phase voltage U03: third harmonic amplitude of neutral point residual voltage If there is already a VTS alarm before FD operated, VTS will continue to block distance protection, that is VTS will be latched when FD operates.
3.32.6 Settings Table 3.32-2 VTS settings No.
Name
Range
Step
Unit
Remark
1
VTS.t_DPU
0.200~100.000
0.001
s
Pickup time delay of VT circuit supervision
2
VTS.t_DDO
0.200~100.000
0.001
s
Dropoff time delay of VT circuit supervision No voltage used for protection calculation 1: enable
3
VTS.En_Out_VT
0: disable
0 or 1
In general, when VT is not connected to the device, this logic setting should be set as “1” Voltage selection for protection calculation
4
VTS.En_LineVT
from busbar VT or line VT
0 or 1
1: line VT 0: busbar VT Alarm function of VT circuit supervision
5
VTS.En
0 or 1
1: enable 0: disable
3.33 CT Circuit Supervision 3.33.1 General Application The purpose of the CT circuit supervision is to detect any abnormality on CT secondary circuit. NOTICE! For double circuit breakers mode, the device will provide indenpendent CT circuit supervision function for CB1 and CB2 respectively. Both CT circuit supervision functions have the same logic.The difference is that the prefix “CBx.” is added to all signals for circuit breaker No.x (x=1 or 2).
3.33.2 Function Description Under normal conditions, CT secondary signal is continuously supervised by detecting the residual current and voltage. If residual current is larger than 10%In whereas residual voltage is less than 3V, an error in CT circuit is considered, the concerned protection functions are blocked and an alarm is issued with a time delay of 10s and drop off with a time delay of 10s after CT circuit is restored to normal condition. 3-271
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3.33.3 Function Block Diagram CTS CBx.CTS.En
CBx.CTS.Alm
CBx.CTS.Blk
3.33.4 I/O Signals Table 3.33-1 I/O signals of CT circuit supervision No.
Input Signal
1
CBx.CTS.En
2
CBx.CTS.Blk
No. 1
Description CT circuit supervision enabling input, it is triggered from binary input or programmable logic etc. CT circuit supervision blocking input, it is triggered from binary input or programmable logic etc.
Output Signal CBx.CTS.Alm
Description Alarm signal to indicate CT circuit fails
3.33.5 Logic SIG
CBx.CTS.En
SIG
CBx.CTS.Blk
SIG
3I0>0.1In
SIG
3U0=1 &
SIG BIinput.RmtCtrl
>=1
& [CSWI01.t_PW_Cls]
SIG CSWI01.Cmd_RmtCtrl SIG CSWI01.LocCtrl
0ms
CSWI01.Op_Cls
>=1 &
SIG BIinput.LocCtrl SIG CSWI01.ManSynCls
>=1
SIG CSWI01.Cmd_LocCtrl SIG MCBrd.CB1.25.On_SynChk
>=1
SIG MCBrd.CB1.25.Ok_Chk SIG MCBrd.CB1.Alm_VTS
&
& &
EN
[MCBrd.CB1.En_Alm_VTS]
EN
[MCBrd.CB1.25.En_VTS_Blk_SynChk]
EN
[MCBrd.CB1.En_Alm_VTS]
& &
SIG MCBrd.CB1.Alm_VTS EN
[MCBrd.CB1.25.En_VTS_Blk_DdChk]
EN
[MCBrd.CB1.25.En_LvL_DdB]
EN
[MCBrd.CB1.25.En_DdL_LvB]
EN
[MCBrd.CB1.25.En_DdL_DdB]
>=1
&
>=1
>=1
SIG MCBrd.CB1.25.Ok_Chk SIG MCBrd.CB1.25.On_NoChk
Figure 3.34-2 Logic diagram of closing circuit breaker 1 3-274
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SIG CSWI02.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1 EN
[CSWI02.En_Cls_Blk]
SIG CSWI02.CILO.EnCls SIG CSWI02.RmtCtrl
>=1 &
SIG BIinput.RmtCtrl
>=1
& [CSWI02.t_PW_Cls]
SIG CSWI02.Cmd_RmtCtrl SIG CSWI02.LocCtrl
0ms
CSWI02.Op_Cls
>=1 &
SIG BIinput.LocCtrl SIG CSWI02.ManSynCls
>=1
SIG CSWI02.Cmd_LocCtrl SIG MCBrd.CB2.25.On_SynChk
>=1
SIG MCBrd.CB2.25.Ok_Chk SIG MCBrd.CB2.Alm_VTS
&
& &
EN
[MCBrd.CB2.En_Alm_VTS]
EN
[MCBrd.CB2.25.En_VTS_Blk_SynChk]
EN
[MCBrd.CB2.En_Alm_VTS]
& &
SIG MCBrd.CB2.Alm_VTS EN
[MCBrd.CB2.25.En_VTS_Blk_DdChk]
EN
[MCBrd.CB2.25.En_LvL_DdB]
EN
[MCBrd.CB2.25.En_DdL_LvB]
EN
[MCBrd.CB2.25.En_DdL_DdB]
>=1
&
>=1
>=1
SIG MCBrd.CB2.25.Ok_Chk SIG MCBrd.CB2.25.On_NoChk
Figure 3.34-3 Logic diagram of closing circuit breaker 2
As shown in Figure 3.34-3, for double circuit breakers application, both the first closing command “CSWI01.Op_Cls” and the second closing command “CSWI02.Op_Cls”, which are controlled by synchrocheck logic, can be used for CB closing, otherwise, the logic of the second closing command “CSWI02.Op_Cls” should comply with Figure 3.34-4. After receiving a closing command, this device will continuously check whether the 2 voltages (Incoming voltage and reference voltage) involved in synchronism check (or dead check) can meet the criteria. Within the duration of [MCBrd.CBx.25.t_Wait_Chk], if the synchronism check (or dead check) criteria are not met, the signal “MCBrd.CBx.25.Ok_Chk” will be set as “0”; if the synchronism check (or dead check) criteria are met, the signal “MCBrd.CBx.25.Ok_Chk” will be set as “1”.
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When any of the following criteria is fulfilled, an alarm signal [MCBrd.CBx.Alm_VTS] will be issued with a time delay of 1.25s, and drop off with a time delay of 10s after three phases voltage restored to normal. The alarm signal will block the closing command for circuit breaker. 1.
The negative-sequence voltage is greater than 8V.
2.
The positive-sequence voltage is smaller than 30V, and any phase current is greater than 0.04In.
SIG
CSWIxx.CILO.Disable
SIG
BIinput.CILO.Disable
EN
[CSWIxx.En_Cls_Blk]
SIG
CSWIxx.CILO.EnCls
SIG
CSWIxx.RmtCtrl
SIG
BIinput.RmtCtrl
SIG
CSWIxx.Cmd_RmtCtrl
SIG
CSWIxx.LocCtrl
SIG
BIinput.LocCtrl
SIG
CSWIxx.Cmd_LocCtrl
>=1
>=1
& [CSWIxx.t_PW_Cls]
0ms
[CSWIxx.Op_Cls]
>=1
& >=1
>=1
&
Figure 3.34-4 Logic diagram of closing switch (xx=02~10)
Access the menu “Local Cmd→Control” to issue control command locally, and this signal “CSWIxx.Cmd_LocCtrl” will be set as “1”. Remote control commands from SCADA/CC can be transmitted via IEC 60870-5-103 protocol or IEC 61850 protocol, and this signal “CSWIxx.Cmd_RmtCtrl” will be set as “1”. SIG CSWI01.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1 EN
[CSWI01.En_Opn_Blk]
& [CSWI01.t_PW_Opn]
SIG CSWI01.CILO.EnOpn SIG CSWI01.RmtCtrl
0ms
CSWI01.Op_Opn
>=1 &
SIG BIinput.RmtCtrl
>=1
SIG CSWI01.Cmd_RmtCtrl SIG CSWI01.LocCtrl
>=1 &
SIG BIinput.LocCtrl SIG CSWI01.ManOpn
>=1
SIG CSWI01.Cmd_LocCtrl
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>=1
SIG BIinput.CILO.Disable
>=1 EN
[CSWI02.En_Opn_Blk]
& [CSWI02.t_PW_Opn]
0ms
CSWI02.Op_Opn
0ms
CSWIxx.Op_Opn
SIG CSWI02.CILO.EnOpn SIG CSWI02.RmtCtrl
>=1 &
SIG BIinput.RmtCtrl
>=1
SIG CSWI02.Cmd_RmtCtrl SIG CSWI02.LocCtrl
>=1 &
SIG BIinput.LocCtrl SIG CSWI02.ManOpn
>=1
SIG CSWI02.Cmd_LocCtrl
Figure 3.34-5 Logic diagram of open circuit breaker SIG CSWIxx.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1 EN
[CSWIxx.En_Opn_Blk]
& [CSWIxx.t_PW_Opn]
SIG CSWIxx.CILO.EnOpn SIG CSWIxx.RmtCtrl
>=1 &
SIG BIinput.RmtCtrl
>=1
SIG CSWIxx.Cmd_RmtCtrl SIG CSWIxx.LocCtrl
>=1 &
SIG BIinput.LocCtrl SIG CSWIxx.Cmd_LocCtrl
Figure 3.34-6 Logic diagram of open switch (xx=02~10)
The control output fulfills signal output circuit, and opens or closes circuit breaker, disconnector and earth switch according to the control command. Object manipulation strictly performs three steps: selection, check and excute, and perform output relay check, to ensure that the remote control can be excuted safely and reliably. When logic interlock is enabled, the device can receive the programmable interlock logic. The device can automatically initiate the interlock logic to determine whether to allow control operations. The device provides corresponding settings ([CSWIxx.En_Opn_Blk] and [CSWIxx.En_Cls_Blk]) for each control object. When they are set as “1”, the interlock function of the corresponding control object is enabled. The interlock logic can be configured by using
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PCS-Explorer, and downloaded to the device via the Ethernet port. If the interlock function is enabled, but it is not configured the interlock logic, the result of the logic output is 0. The control record is a file which is used to store remote control command records of this device circularly. If the record number is to 256, the storage area of the control record will be full. If this device has received a new remote command, this device will delete the oldest remote control record, and then store the latest remote control record. There are 10 configuration pages corresponding to 10 control outputs in totall respectively. Each configuration page can finish some signals configuration, including remote control, local control, disable interlock blocking, and so on. In order to conveniently configure control output, the same output signals, including “BIinput.RmtCtrl”, “BIinput.LocCtrl” and “BIinput.CILO.Disable”, are available after processing binary signals internally, as shown in figure below.
Figure 3.34-7 Configuration page of control output 01 (default configration)
Figure 3.34-8 Configuration page of control output 02 (default configration)
Control output 03~10 is as same as control output 02. The configuration rule about remote control and local control to binary outputs is as bellow: X means that it is not configured.
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Local
CSWIxx.
BIinput.
CSWIxx.
BIinput.
RmtCtrl
RmtCtrl
LocCtrl
LocCtrl
X
X
X
X
0
X
X
X
X
0
X
X
1
X
X
X
X
1
X
X
X
X
0
X
X
X
X
0
X
X
1
X
X
X
X
1
0
X
0
X
0
X
X
0
X
0
0
X
X
0
X
0
0
X
1
X
X
0
1
X
0
X
X
1
X
0
X
1
1
X
0
X
1
X
X
0
X
1
0
X
X
1
X
0
1
X
1
X
1
X
X
1
X
1
1
X
X
1
X
1
Control Mode
Neither Local control nor remote control are permissible. Only local control is permissible.
Only remote control is permissible.
Only remote control is permissible.
Only local control is permissible.
Neither Local control nor remote control are permissible.
Only local control is permissible.
Only remote control is permissible.
Both Local control and remote control are permissible.
For remote control or local control, they can be configured by either of “CSWIxx.RmtCtrl” and “BIinput.RmtCtrl”, or either of “CSWIxx.LocCtrl” and “BIinput.LocCtrl”. 2. Synchrocheck Three synchrocheck modes are designed for CB closing: no check mode, dead check mode and synchronism check mode, if any one of the condition of three synchrocheck modes satisfied, then synchrocheck signal “MCBrd.CBx.25.Ok_Chk” will be asserted. The synchronism check function measures the conditions across the circuit breaker and compares them with the corresponding settings. The output is only given if all measured quantities are simultaneously within their set limits. Compared to the synchronism check for auto-reclosing, an additional criterion is applied to check the rate of frequency change (df/dt) between both sides of the CB. When the following four conditions are all met, the synchronism check is successful.
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1) Phase angle difference between incoming voltage and reference voltage is less than the setting [MCBrd.CBx.25.phi_Diff] 2) Frequency difference between incoming voltage and reference voltage is less than [MCBrd.CBx.25.f_Diff] 3) Voltage difference between between incoming voltage and reference voltage is less than [MCBrd.CBx.25.U_Diff] 4) Rate of frequency change between incoming voltage and reference voltage is less than [MCBrd.CBx.25.df/dt] The dead check function measures the amplitude of line voltage and bus voltage at both sides of the circuit breaker, and then compare them with the live check setting [MCBrd.CBx.25.U_Lv] and the dead check setting [MCBrd.CBx.25.U_Dd]. The dead check is successful when the measured quantities comply with the criteria. When this device is set to work in no check mode and receives a closing command, CB will be closed without synchronism check and dead check. Synchrocheck for manual closing also supports voltage switching. In general, voltage switching is fulfilled by external circuit ([CBx.CBConfigMode]=NoVoltSel). If using this module to fulfill voltage switching, the busbar arrangement should be determined by the setting [CBx.CBConfigMode], including:
Double busbars arrangement ([CBx.CBConfigMode]=DblBusOneCB)
1½ breakers arrangement ([CBx.CBConfigMode]=3/2BusCB or 3/2TieCB)
Analog input defines four voltage inputs, UL1, UB1, UL2, UB2, and their usage are as follow: UL1: it connects with three-phase protection voltages (from line or busbar), which mainly are used by distance protection, voltage protection and so on. According to the voltage switching result, synchrocheck logic choose one voltage to be used for synchrocheck function, synchrocheck function requires to judgment the phase identification information of the voltage, which is determined by the setting [MCBrd.CBx.25.Opt_Source_UL1]. If voltage switching function is not used, the reference voltage will be selected from UL1 fixedly. UB1: according to the voltage switching result, synchrocheck logic determined whether the voltage is used for synchrocheck function. Synchrocheck function requires to judgment the phase identification information of the voltage, which is determined by the setting [MCBrd.CBx.25.Opt_Source_UB1]. If voltage switching function is not used, UB1 will be taken as the synchronism voltage. UL2: according to the voltage switching result, synchrocheck logic determined whether the voltage is used for synchrocheck function. Synchrocheck function requires to judgment the phase identification information of the voltage, which is determined by the setting [MCBrd.CBx.25.Opt_Source_UL2]. When voltage switching is available, it is only available for 1½ breakers arrangement, it is fixedly connected to the voltage of the other line of the same diameter in 1½ breakers arrangement.
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UB2: according to the voltage switching result, synchrocheck logic determined whether the voltage is used for synchrocheck function. Synchrocheck function requires to judgment the phase identification information of the voltage, which is determined by the setting [MCBrd.CBx.25.Opt_Source_UB2]. When voltage switching is available, it is connected to synchronism voltage for double busbars arrangement or 1½ breakers arrangement. Synchrocheck for manual closing supports voltage switching function, and the switching logic is as same as that of synchrocheck for protection closing. The setting [CBx.CBConfigMode] should be set according to the actual primary busbar arrangement, otherwise, the voltage switching of synchrocheck for manual closing will fail, so as to block manual closing with synchrocheck. During dead charge check, when only single-phase voltage is connected to UL1, live voltage is valid if the setting [VTS.En] should be set as “0” and the connected single-phase voltage is higher than the setting [MCBrd.CBx.25.U_Lv], otherwise, live voltage is regarded as live only when three phases voltages are all higher than [MCBrd.CBx.25.U_Lv].
3.34.3 Function Block Diagram CSWI01 CSWI01.CILO.EnOpn
CSWI01.Op_Opn
CSWI01.CILO.EnCls
CSWI01.Op_Cls
CSWI01.RmtCtrl CSWI01.LocCtrl CSWI01.CILO.Disable
CSWI02 CSWI02.CILO.EnOpn
CSWI02.Op_Opn
CSWI02.CILO.EnCls
CSWI02.Op_Cls
CSWI02.RmtCtrl CSWI02.LocCtrl CSWI02.CILO.Disable
CSWIxx CSWIxx.CILO.EnOpn
CSWIxx.Op_Opn
CSWIxx.CILO.EnCls
CSWIxx.Op_Cls
CSWIxx.RmtCtrl CSWIxx.LocCtrl CSWIxx.CILO.Disable
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BIinput.RmtCtrl
BIinput.LocCtrl
BIinput.LocCtrl
BIinput.CILO.Disable
BIinput.CILO.Disable
CSWI01.ManSynCls CSWI01.ManOpn CSWI02.ManSynCls CSWI02.ManOpn
xx can be from 02 or 03 to 10
3.34.4 I/O Signals Table 3.34-1 I/O signals of control No.
Input Signal
Description From receiving a closing command, this device will continuously check whether the 2 voltages (Incoming voltage and reference voltage) involved in synchronism check(or dead check) can meet the criteria.
1
MCBrd.CBx.25.Ok_Chk
Within the duration of [MCBrd.CBx.25.t_Wait_Chk], if the synchronism check(or dead check) criteria are not met, [MCBrd.CBx.25.Ok_Chk] will be set as “0”; if the synchronism check (or dead check) criteria are met, [MCBrd.CBx.25.Ok_Chk] will be set as “1”.
2
CSWIxx.CILO.EnOpn
3
CSWIxx.CILO.EnCls
It is the interlock status of No.xx open output of BO module (xx=01~10) It is the interlock status of No.xx closing output of BO module (xx=01~10) It is used to select the local control to No.xx controlled object
4
CSWIxx.LocCtrl
(CB/DS/ES). When the local control is active, No.xx binary outputs can only be locally controlled. (xx=01~10) It is used to select the remote control to No.xx controlled object
5
CSWIxx.RmtCtrl
(CB/DS/ES). When the remote control is active, No.xx binary outputs can only be remotely controlled by SCADA or control centers. (xx=01~10) It is used to disable the interlock blocking function for control output. If
6
CSWIxx.CILO.Disable
the signal “CSWIxx.CILO.Disable” is “1”, No.xx binary outputs of the device will not be blocked by interlock conditions. (xx=01~10) It is used to select the remote control to controlled object (CB/DS/ES).
7
BIinput.RmtCtrl
When the remote control is active, all binary outputs can only be remotely controlled by SCADA or control centers.
8
BIinput.LocCtrl
It is used to select the local control to controlled object (CB/DS/ES). When the local control is active, all binary outputs can only be locally
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the signal “BIinput.CILO.Disable” is “1”, all binary outputs of this device
BIinput.CILO.Disable
will not be blocked by interlock conditions. When the condition of local control is met and the signal 10
“CSWI01.ManSynCls” is “1”, the output contact [BO_CtrlCls01] is closed
CSWI01.ManSynCls
to execute manually closing the circuit breaker with synschrochcek. When the condition of local control is met and the signal 11
“CSWI01.ManOpn” is “1”, the output contact [BO_CtrlOpn01] is closed
CSWI01.ManOpn
to execute manually open the circuit breaker. When the condition of local control is met and the signal 12
“CSWI02.ManSynCls” is “1”, the output contact [BO_CtrlCls02] is closed
CSWI02.ManSynCls
to execute manually closing the circuit breaker with synschrochcek. (for double circuit breakers application) When the condition of local control is met and the signal
13
“CSWI02.ManOpn” is “1”, the output contact [BO_CtrlOpn02] is closed
CSWI02.ManOpn
to execute manually open the circuit breaker. (for double circuit breakers application)
14
MCBrd.CBx.25.Sel_SynChk
Synchronism check for manual closing is selected.
15
MCBrd.CBx.25.Sel_NoChk
No check for manual closing is selected.
No.
Output Signal
Description
1
CSWIxx.Op_Opn
No.xx command output for open. (xx=01~10)
2
CSWIxx.Op_Cls
No.xx command output for closing. (xx=01~10)
3
BIinput.RmtCtrl
In order to be convenient to user configure control output, three same
4
BIinput.LocCtrl
output signals with input signals are available. The relationship with 10 binary output have been configured inside the device. The user only assigns a specific binary input to input signal, the relevant function can
5
be gained. If some binary output need not be controlled by three signals,
BIinput.CILO.Disable
please cancle the configuration by PCS-Explorer, and configure it independently. 6
VT circuit of circuit breaker No.x is abnormal.
MCBrd.CBx.Alm_VTS
3.34.5 Settings Table 3.34-2 Control settings No.
Name
Range
Step
Unit
Remark No.xx holding time of a normal open contact
1
CSWIxx.t_PW_Opn
0~65535
1
ms
of remote opening CB, disconnector or for signaling purpose. (xx=01, 02….10) No.xx closing time of a normal open contact
2
CSWIxx.t_PW_Cls
0~65535
1
ms
of remote closing CB, disconnector or for signaling purpose. (xx=01, 02….10) 3-283
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Name
Range
Step
Unit
Remark These settings are applied to configure the
3
CSWIxx.t_DPU_DPS
0~60000
1
ms
debouncing time. “DPU” is the abbreviation of “Delay Pick Up”. (xx=01, 02….10) Enabling/disabling No.xx open output of the BO module be controlled by the interlocking
4
CSWIxx.En_Opn_Blk
logic
0 or 1
0: disable 1: enable (xx=01, 02….10) Enabling/disabling No.xx closing output of the BO module be controlled by the interlocking 5
CSWIxx.En_Cls_Blk
logic
0 or 1
0: disable 1: enable (xx=01, 02….10) Table 3.34-3 Synchrocheck settings No.
Name
Range
Step
Unit
Remark Enabling/disabling
alarm
function when VT circuit is 1
MCBrd.CBx.En_Alm_VTS
0 or 1
abnormal 0: disable 1: enable
Table 3.34-4 Synchrocheck settings No.
Name
Range
Step
Unit
Remark Voltage selecting mode of
1
MCBrd.CBx.25.Opt_Source_UL1
Ua
line 1
Ub
Ua: A-phase voltage
Uc
Ub: B-phase voltage
Uab
Uc: C-phase voltage
Ubc
Uab: AB-phase voltage
Uca
Ubc: BC-phase voltage Uca: CA-phase voltage Voltage selecting mode of
2
MCBrd.CBx.25.Opt_Source_UB1
Ua
bus 1
Ub
Ua: A-phase voltage
Uc
Ub: B-phase voltage
Uab
Uc: C-phase voltage
Ubc
Uab: AB-phase voltage
Uca
Ubc: BC-phase voltage Uca: CA-phase voltage
3
MCBrd.CBx.25.Opt_Source_UL2
Ua
Voltage selecting mode for
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Name
Range
Step
Unit
Remark
Ub
line 2
Uc
Ua: A-phase voltage
Uab
Ub: B-phase voltage
Ubc
Uc: C-phase voltage
Uca
Uab: AB-phase voltage Ubc: BC-phase voltage Uca: CA-phase voltage Voltage selecting mode for
4
MCBrd.CBx.25.Opt_Source_UB2
Ua
bus 2
Ub
Ua: A-phase voltage
Uc
Ub: B-phase voltage
Uab
Uc: C-phase voltage
Ubc
Uab: AB-phase voltage
Uca
Ubc: BC-phase voltage Uca: CA-phase voltage
5
MCBrd.CBx.25.U_Dd
0.05Un~0.8Un
0.001
V
6
MCBrd.CBx.25.U_Lv
0.5Un~Un
0.001
V
Voltage threshold of dead check for manual closing Voltage threshold
of
live
check for manual closing Compensation coefficient of
7
MCBrd.CBx.25.K_Usyn
0.20-5.00
synchronism
voltage
for
manual closing Phase difference limit 8
MCBrd.CBx.25.phi_Diff
0~ 89
1
deg
synchronism
check
of for
manual closing Compensation 9
MCBrd.CBx.25.phi_Comp
0~359
difference
1
of
phase
between
synchronous
two
voltages
for
manual closing Frequency difference limit of 10
MCBrd.CBx.25.f_Diff
0.02~1.00
0.01
Hz
synchronism
check
for
manual closing Voltage difference limit of 11
MCBrd.CBx.25.U_Diff
0.02Un~0.8Un
0.01
V
synchronism
check
for
manual closing Synchrocheck
mode
selection for manual closing 12
MCBrd.CBx.25.SetOpt
0, 1
1
0: determined by external signal 1: determined by the setting Enabling/disabling
13
MCBrd.CBx.25.En_SynChk
0 or 1
synchronism
check
for
manual clsoing 3-285
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Name
Range
Step
Unit
Remark 0: disable 1: enable Enabling/disabling dead line and dead bus (DLDB) check
14
MCBrd.CBx.25.En_DdL_DdB
0 or 1
for manual closing 0: disable 1: enable Enabling/disabling dead line and live bus (DLLB) check
15
MCBrd.CBx.25.En_DdL_LvB
0 or 1
for manual closing 0: disable 1: enable Enabling/disabling live line and dead bus (LLDB) check
16
MCBrd.CBx.25.En_LvL_DdB
0 or 1
for manual closing 0: disable 1: enable Enabling/disabling
17
MCBrd.CBx.25.En_NoChk
manual
closing without any check
0 or 1
0: disable 1: enable Threshold
of
rate
of
frequency change between 18
MCBrd.CBx.25.df/dt
0.00~3.00
0.01
Hz/s
both
sides
synchronism
of
CB
for
check
of
manual closing Circuit breaker closing time for manual closing 19
MCBrd.CBx.25.t_Close_CB
20~1000
1
ms
It is the time from receiving closing command pulse till the CB is completely closed. From receiving a closing command, this device will continuously check whether between incoming voltage and
20
MCBrd.CBx.25.t_Wait_Chk
5~30
0.001
s
reference
involved
in
voltage
synchronism
check (or dead check) can meet
the criteria. If the
synchronism check (or dead check) criteria are not met within the duration of this time delay, the failure of
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Name
Range
Step
Unit
Remark synchronism-check (or dead check) will be confirmed. Enabling/disabling synchronism
21
MCBrd.CBx.25.En_VTS_Blk_SynChk
0 or 1
block
check
for
manual closing when VT circuit is abnormal 0: disable 1: enable Enabling/disabling dead
22
MCBrd.CBx.25.En_VTS_Blk_DdChk
0 or 1
check
for
block manual
closing when VT circuit is abnormal 0: disable 1: enable
3.35 Faulty Phase Selection 3.35.1 General Application Fault phase selection logic can be implemented by the following methods: 1.
Detecting the variation of operating voltage
2.
Detecting the phase difference between I0 and I2A
The logic makes the device ideal for single-phase tripping applications.
3.35.2 Function Description 3.35.2.1 Variation of Operating Voltage (Faulty Phase Selection Element 1) 1.
Variation of phase operating voltage
1)
Phase A: ΔUOPA
2)
Phase B: ΔUOPB
3)
Phase C: ΔUOPC
2.
Variation of phase-to-phase operating voltage
1)
Phase AB: ΔUOPAB
2)
Phase BC: ΔUOPBC
3)
Phase CA: ΔUOPCA
ΔUOΦMAX=Max(ΔUOPA, ΔUOPB, ΔUOPC) ΔUOΦΦMAX=Max(ΔUOPAB, ΔUOPBC, ΔUOPCA) If ΔUOΦMAX is several times higher than the variation of operating voltages of other two phases, the 3-287
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single-phase fault is ensured, otherwise, the multi-phase fault is ensured. Table 3.35-1 Relation between ΔUOΦMAX and faulty phase ΔUOΦMAX or ΔUOΦΦMAX
Fault phase
ΔUOPA
Phase A
ΔUOPB
Phase B
ΔUOPC
Phase C
ΔUOPAB
Phase AB
ΔUOPBC
Phase BC
ΔUOPCA
Phase CA
3.35.2.2 I0 and I2A (Faulty Phase Selection Element 2) The phase selection algorithm uses the angle relation between I 0 and I2A of the device. As shown in Figure 3.35-1, there are three faulty phase selection regions.
Region A 60°
-60°
Region B
Region C
180°
Figure 3.35-1 The region of faulty phase selection
Depended on the phase relation between I0 and I2A, the faulty phase can be determined. 1.
-60º
